Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments in “Remarks - 05/04/2026 - Applicant Arguments/Remarks Made in an Amendment", have been fully considered, but they are not persuasive, because of the following:
Applicant’s amendment of claims 1, 9, 21, 23 and 25, and cancellation of claims 6, 16-20 and 24, and submission of new claims 26-27 in “Claims - 05/04/2026” is acknowledged.
But, amendments to the independent claims 1, 9, and 21, specifically, noted infra, is not supported in the method claims originally elected “Group I, claims 1-15 and cancels claims 16-20. In addition, Applicant has added new claims 21-25, which are also elected” in “Response to Election / Restriction Filed - 12/15/2025” against the “Requirement for Restriction/Election - 10/14/2025”. The following newly amended features are not part of method claim, instead part of device claim group II identified in “Requirement for Restriction/Election - 10/14/2025”.
Features in Claim 1: a dielectric fin (26; Fig 31; paragraphs [0070]) in the recess: forming a dummy gate over the dielectric fin (26; Fig 31; paragraphs [0070]) and the second semiconductor fin; replacing the dummy gate with a gate stack
Features in Claim 9: forming “a dielectric fin” (26; Fig 31; paragraphs [0070]) between the first fin and the second fin: forming an isolation region surrounding the first fin and surrounding the second fin, and the dielectric fin (26; Fig 31; paragraphs [0070]);
Features in Claim 21: forming a dielectric fin a dielectric fin (26; Fig 31; paragraphs [0070]) between the first semiconductor fin and the second semiconductor fin: forming an isolation region surrounding the first semiconductor fin and the second semiconductor fin , and the dielectric fin (26; Fig 31; paragraphs [0070]), wherein the isolation region contacts a sidewall of the dielectric fin (26; Fig 31; paragraphs [0070])
The instant published (PGPUB) discloses in paragraphs “ [0008] FIGS. 31 and 32 illustrate cross-sectional views of FinFET devices in accordance with other embodiments”.
The method claims are disclosed in [0005] FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10A, 10B, 11, 12A, 12B, 13A, 13B, 14, 15A, 15B, 16, 17A, 17B, 18, 19A, 19B, 20, 21A, and 21B illustrate various views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments. [0006] FIGS. 22, 23, 24A, 24B, 24C, 25A, 25B, 25C, 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, 28C, 29A, 29B, 29C, and 29D illustrate various views of intermediate stages in the manufacturing of gate isolation regions, in accordance with some embodiments. And [0007] FIGS. 30A, 30B, 30C, and 30D illustrate cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.
However “a dielectric fin” (26; Fig 31; paragraphs [0070]) and associated features are disclosed anywhere in Fig.2 to Fig 30D.
In view of the above, the amended limitations, as indicated supra, is not part of the elected group I. Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, amended claims in “Claims - 05/04/2026” as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
Moreover, since the Applicant’s amendment to independent claims 1, 9, 21 includes original non-elected features, which are not separatable, this office action considers claims 1-15 and 21-25 in 12/15/2025 for further examination. Applicant’s arguments are all based on new limitation, which are from non-elected group. As the applicant's arguments are not persuasive, this Office Action maintains the rejection of the “Non-Final Rejection - 01/16/2026” except some minor update.
Claim Objections
Claim 25 is objected to because of the following informalities:
25. (New) The method of claim 21, wherein the dielectric fill material compressively stresses the first semiconductor fin and the second semiconductor fin.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries “wherein the first dielectric material is a more flexible material than the second dielectric material”. The claim is indefinite because of the following:
The term “flexible” is a relative term which renders the claim indefinite. The term “flexible” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For examination purposes, the examiner interprets flexible to be able to conformally deposit on the surfaces of the trench.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 2021/0313181 in view of Song et al. US 2017/0162568.
Regarding claim 1, Chen et al. in Figs. 26A and 27A discloses a method comprising:
etching a gate stack 60 to form a trench 74 extending through the gate stack, the gate stack comprising a metal gate electrode 56 [0042] and a gate dielectric 52, wherein forming the trench removes a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion;
extending the trench 74 through an isolation region 22 under the gate stack 60 and into a semiconductor substrate 20 under the isolation region 22.
Chen et al. in [0057] further discloses forming an isolation region 82 and an air gap 84 within the isolation region 82 by depositing a dielectric material into trench 74. Chen et al. does not expressly disclose conformally depositing a first dielectric material on surfaces in the trench; and depositing a second dielectric material on the first dielectric material to fill the trench, wherein the first dielectric material is a more flexible material than the second dielectric material.
Song et al. teaches the formation of an isolation film for cutting a gate electrode which results in enhanced performance. Fig. 9 and [0126]-[0129] teaches conformally depositing a first isolation material I6-1 on surfaces in a trench; and depositing a second isolation material I6-2 on the first dielectric material I6-1 to fill the trench, wherein the first dielectric material is able to conformally deposit on the surfaces of the trench more than the second dielectric material. Song et al. further teaches that the isolation materials I6-1 and I6-2 may include different materials, having different stress characteristics which determines the overall stress of the isolation film pattern I6.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Song et al. in the method of Chen et al. for the purpose of enhancing the performance of the device. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 2, Chen et al. in view of Song et al. teaches the method of claim 1. Although Song et al. does not expressly teach wherein the first dielectric material is silicon oxide, the material differences are considered obvious design choices and are not patentable unless obvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious before the effective filing date of the invention. See MPEP 2144.07
Regarding claim 3, Chen et al. in view of Song et al. teaches the method of claim 1. Although Song et al. does not expressly teach wherein the second dielectric material is silicon nitride, the material differences are considered obvious design choices and are not patentable unless obvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious before the effective filing date of the invention. See MPEP 2144.07
Regarding claim 4, Chen et al. in view of Song et al. teaches the method of claim 1, Chen et al. teaches in [0057] wherein forming the dielectric material in trench 74 may be deposited using an Atomic Layer Deposition (ALD) process.
Regarding claim 5, Chen et al. in view of Song et al. teaches the method of claim 1. Chen et al. teaches in Fig. 28, the method of claim 1, further comprising forming a hard mask 66 on the gate stack 60, wherein the first dielectric material 82 physically contacts a sidewall of the hard mask 66.
Regarding claim 6, Chen et al. in view of Song et al. teaches the method of claim 1 but does not expressly teach wherein the trench extends a depth into the semiconductor substrate that is in the range of 0 nm to 25 nm.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 7, Chen et al. in view of Song et al. teaches the method of claim 1. Song et al. teaches wherein the second dielectric material I6-2 is free of seams.
Regarding claim 8, Chen et al. in view of Song et al. teaches the method of claim 1 but does not expressly teach wherein the first dielectric material has a thickness in the range of 2 nm to 10 nm.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 9, Chen et al. in Figs. 26A and 27A discloses a method comprising:
forming a first fin 24 and a second fin 24 over a substrate 20;
forming an isolation region 22 surrounding the first fin 24 and surrounding the second fin 24;
forming a gate structure 60 extending over the first fin 24 and the second fin 24;
forming an opening 74 extending through the gate structure and the isolation region to expose the substrate 20, wherein the opening is between the first fin 24 and the second fin 24;
depositing a conformal layer of a first dielectric material 82 in the opening, wherein the first dielectric material in the opening physically contacts the gate structure 60, the isolation region 22, and the substrate 20.
Chen et al. does not expressly disclose depositing a second dielectric material on the first dielectric material in the opening, wherein the first dielectric material reduces stresses exerted between the second dielectric material and the substrate.
Song et al. teaches the formation of an isolation film for cutting a gate electrode which results in enhanced performance. Fig. 9 and [0126]-[0129] teaches conformally depositing a conformal layer of a first isolation material I6-1 in the opening; and depositing a second isolation material I6-2 on the first dielectric material I6-1 to fill the trench. Song et al. further teaches that the isolation materials I6-1 and I6-2 may include different materials, having different stress characteristics which determines the overall stress of the isolation film pattern I6.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Song et al. in the method of Chen et al. for the purpose of enhancing the performance of the device. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 10, Chen et al. in view of Song et al. teaches the method of claim 9. Chen et al. in [0057] teaches wherein the first dielectric material 82 comprises silicon oxide.
Regarding claim 11, Chen et al. in view of Song et al. teaches the method of claim 9. Although Song et al. does not expressly teach wherein the second dielectric material is silicon nitride, the material differences are considered obvious design choices and are not patentable unless obvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious before the effective filing date of the invention. See MPEP 2144.07
Regarding claim 12, Chen et al. in view of Song et al. teaches the method of claim 11. Although Song et al. does not expressly teach wherein the second dielectric material has a silicon concentration in the range of 5% to 30%, the material differences are considered obvious design choices and are not patentable unless obvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious before the effective filing date of the invention. See MPEP 2144.07
Regarding claim 13, Chen et al. in view of Song et al. teaches the method of claim 9. Song et al. teaches wherein the opening near the substrate has the same sidewall profile before and after depositing the second dielectric material I6-2.
Regarding claim 14, Chen et al. in view of Song et al. teaches the method of claim 9, Chen et al. teaches in [0057] wherein forming the dielectric material in trench 74 may be deposited using an Atomic Layer Deposition (ALD) process.
Regarding claim 15, Chen et al. in view of Song et al. teaches the method of claim 9. Chen et al. teaches in Fig. 28, the method of claim 1, further comprising forming a hard mask 66 on the gate stack 60, wherein the first dielectric material 82 physically contacts a sidewall of the hard mask 66.
Claim(s) 21, 22 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. US 2017/0162568.
Regarding claim 21, Song et al. in Figs. 1 and 9 discloses a method comprising:
forming a first semiconductor fin F2 and a second semiconductor fin F3 over a substrate 10;
forming an isolation region 20 surrounding the first semiconductor fin F2 and the second semiconductor fin F3;
forming a first gate stack 200 over the first semiconductor fin F2 and a second gate stack 201 over the second semiconductor fin F3; and
forming a gate isolation region I6 separating the first gate stack 200 from the second gate stack 201,
wherein forming the gate isolation region comprises:
conformally depositing a layer I6-1 that physically contacts the first gate stack 200 and the second gate stack 201; and
depositing a dielectric fill material I6-2 on the layer.
Song et al. does not expressly disclose a layer I6-1 of silicon oxide.
Song et al. teaches the formation of an isolation film for cutting a gate electrode which results in enhanced performance. Fig. 9 and [0126]-[0129] further teaches that the isolation materials I6-1 and I6-2 may include different materials, having different stress characteristics which determines the overall stress of the isolation film pattern I6.
Therefore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 22, Song et al. teaches the method of claim 21. Although Song et al. does not expressly teach wherein the dielectric fill material is silicon nitride, the material differences are considered obvious design choices and are not patentable unless obvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious before the effective filing date of the invention. See MPEP 2144.07
Regarding claim 25, Song et al. teaches the method of claim 21, wherein the dielectric fill material compressively stresses the first semiconductor fin and the second semiconductor fin [0097].
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. as applied to claim 21 above, and further in view of Chen et al. US 2021/0313181.
Regarding claim 23, Song et al. teaches the method of claim 21 but does not expressly teach wherein the layer of silicon oxide (e.g. dielectric (isolation) material) physically contacts the substrate.
Chen et al. in Fig. 26A and [0051] teaches a method of forming a dielectric region between two cut gates to help prevent or reduce current leakage from one gate to another. Chen et al. further teaches the dielectric region has a trench 74 formed in a substrate 20 and the dielectric material 82 (e.g. silicon oxide) physically contacts the substrate.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chen et al. in the method of Song et al. for the purpose of enhancing the performance of the device.
Claim(s) 21, 22 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. US 2021/0335674.
Regarding claim 21, Lin et al. in Figs. 4-20 discloses a method comprising:
forming a first semiconductor fin 404A and a second semiconductor fin 404B over a substrate 302;
forming an isolation region 700 surrounding the first semiconductor fin 404A and the second semiconductor fin 404B;
forming a first gate stack 2004A over the first semiconductor fin 404A and a second gate stack 2004B over the second semiconductor fin 404B; and
forming a gate isolation region 1600 separating the first gate stack 2004A from the second gate stack 2004B, wherein forming the gate isolation region comprises:
conformally depositing a layer of silicon oxide 1601 [0079] that physically contacts the first gate stack 2004A and the second gate stack 2004B; and
depositing a dielectric fill material 1602 on the layer of silicon oxide [0079].
Lin et al. in [0079] provides a list of dielectric materials, e.g. silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or combinations thereof, used as conformal layer 1601 and fill material 1602.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try any of the materials in the gate isolation region, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious.
KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 22, Lin et al. discloses the method of claim 21, wherein the dielectric fill material 1602 is silicon nitride [0079].
Regarding claim 24, Lin et al. discloses the method of claim 21 further comprising forming a dielectric fin 600 between the first semiconductor fin 404A and the second semiconductor fin 404B, wherein the layer of silicon oxide 1601 physically contacts a top surface of the dielectric fin 600, Fig. 18.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
September 21, 2026
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