DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on July 28, 2025. Claims 1-3, 6, 14-15 and 18-19 have been amended. New claim 21 has been added. Claim 5 has been canceled. Currently, claims 1-4 and 6-21 are pending.
Applicant’s amendment to claims 1, 6, 14, 15 and 19 successfully overcomes the 112(b) rejection of claims 1, 6, 14, 15 and 19 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments with respect to claims 1, 14 and 19 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 1 is objected to because of the following informalities: “an entirety the second semiconductor region” should read, “an entirety of the second semiconductor region”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2 and 21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 2 and 21, the limitation, “wherein the first conductivity type is an N conductivity type and the second conductivity type is a P conductivity type” does not have support in the disclosure.
As per the specification and figures the first conductivity type is P conductivity type, that is the doped region 15 and the semiconductor layer 19 are P-type and the second conductivity type is N conductivity type that is, the substrate 13 is N-type.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 4-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 3, the limitation, “..PN junction between the first semiconductor region and the substrate”, is indefinite as “substrate” lacks antecedent basis.
Claims 4 and 6 depend upon claim 3 and do not rectify the problem therefore, they are also rejected.
Regarding claim 7, the limitation, “wherein the semiconductor layer has the second conductivity type”, is indefinite since as per claim 1 the semiconductor layer has a first conductivity type whereas claim 7 contradicts this by reciting that the semiconductor layer has a second conductivity type.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 3-4, 6-7, 9-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Arnaud et al. (US 2019/0296004 A1; hereafter Arnaud) in view of Ohashi et al. (US 2016/0247884 A1; hereafter Ohashi) and Reiner et al. (US 2016/0260817 A1; hereafter Reiner).
Regarding claim 1, Arnaud teaches a method for manufacturing a device (see e.g., electrostatic discharge (ESD) protection circuit, Figures 1 and 2), comprising:
Arnaud discloses the steps to form the ESD device in paragraph [0048], “The method further comprises steps of forming layer 40 by epitaxy, of forming regions 42 and 44 in layer 40, of forming insulating wells 32 between the different areas, of forming layer 50, and of forming conductive layers 52. The method also comprises the steps of doping the different regions and layers.”
Arnaud does not explicitly teach their sequence. However, it is reasonably understood that the layers would be formed sequentially.
First, the n-type substrate 34/36 and the p-type doped region 38, which is flush with its surface are formed. Only after this step can the p-type epitaxial layer 40 be deposited, with its upper portion doped with n-type dopants to form for example, region 42 and made flush with the surface. Subsequently, an insulating layer 50 may be formed over the structure.
forming a first semiconductor region of a first conductivity type (see e.g., heavily doped p-type region 38, Para [0047], Figure 2) in a first upper portion of a semiconductor substrate with a second conductivity type opposite to the first conductivity type (see e.g., region 38 formed in the upper portion of the n-type substrate 34/36, Para [0048], Figure 2), the first semiconductor region being flush with a first upper surface of the first upper portion of the semiconductor substrate (see e.g., region 38 is flushed with the upper surface of the substrate 34/36, Figure 2);
after forming the first semiconductor region of the first conductivity type in the first upper portion of the semiconductor substrate, forming, on the first upper portion of the semiconductor substrate having a first the second conductivity type, a semiconductor layer of the first conductivity type (see e.g., p-type epitaxial layer 40 formed on the upper surface of the substrate 34/36 and region 38, Para [0048], Figure 2);
after forming the semiconductor layer, forming a second semiconductor region in a second upper portion of the semiconductor layer by implanting dopant elements at a second upper surface of the second upper portion of the semiconductor layer (see e.g., forming heavily doped n-type region for example, 42a in the upper portion of the layer 40), the second semiconductor region being flush with the second upper surface of the second upper portion (see e.g., the upper surface of region 40 is flushed with the upper surface of layer 40, Figure 2);
forming an electrically-insulating layer over and contacting the upper surface of the semiconductor layer (see e.g., insulator 50 formed on the upper surface of layer 40 with openings exposing region 42, Para [0043], Figure 2).
Arnold does not explicitly teach
“treating an entirety of the second upper surface and an entirety the second semiconductor region in the second upper portion with…. fluorine atoms … implanted in the second upper portion of the semiconductor layer”;
In a similar field of endeavor Ohashi teaches
treating an entirety of the second upper surface and an entirety the second semiconductor region in the second upper portion with…. fluorine atoms … implanted in the second upper portion of the semiconductor layer (see e.g., the first interface region 40 having fluorine distribution formed over the upper surface of drift layer 14 and the p-type doped regions 20 and n-type doped regions 18, Para [0041], [0053], Figure 5);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Ohashi’s teachings of treating an entirety of the second upper surface and an entirety the second semiconductor region in the second upper portion with…. fluorine atoms … implanted in the second upper portion of the semiconductor layer in the method of Arnaud so that fluorine may bond to the dangling bond of silicon in the top portion of the semiconductor layer and form the termination structure.
Arnaud does not explicitly teach
“treating ……with a fluorinated-plasma in upper surface of the semiconductor layer during a fluorinated-plasma treatment process”
In a similar field of endeavor Reiner teaches
treating ……with a fluorinated-plasma in upper surface of the semiconductor layer during a fluorinated-plasma treatment process (see e.g., the first lateral surface section 112 of the substrate 100 is fluorine treated by a fluorine plasma 116. The fluorine plasma 116, i.e., a plasma that at least partially includes fluorine molecules or atoms, is generated by an RF signal that causes particles in the fluorine injection gas mixture 126 to ionize and transform the fluorine injection gas mixture 126 into a plasma state. The fluorine injection gas mixture 126 may include CF.sub.4 (Tetrafluormethan), C.sub.2F.sub.6 (Hexafluorethan), C.sub.3F.sub.8 (Perfluorpropan), C.sub.4F.sub.6 (Perfluorbutadien), Paras [0035], [0037], [0039]- [0043], Figures 4-9);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Reiner’s teachings of treating ……with a fluorinated-plasma in upper surface of the semiconductor layer during a fluorinated-plasma treatment process in the method of Arnaud as it is one of the various methods available to provide the surface of the semiconductor layer with fluorine atoms.
Regarding claim 3, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud further teaches
comprising forming a first PN junction between the first semiconductor region and the substrate (see e.g., the PN junction between the n-type silicon substrate 34/ 36 and the p-type region 38 forms a Zener diode, Paras [0029], [0041], Figures 1 and 2).
Regarding claim 4, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 3 as mentioned above. Arnaud further teaches
wherein the first PN junction is a Zener diode (see e.g., the PN junction between the n-type silicon substrate including regions 34 and 36 and the p-type region 38 forms a Zener diode, Paras [0029], [0041], Figures 1 and 2).
Regarding claim 6, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 3 as mentioned above. Arnaud further teaches
comprising forming a PN junction between the semiconductor layer and the second semiconductor region constitutes a diode (see e.g., the PN junction between the n-type doped region 42a and the p-type silicon epitaxial layer 40 forms a diode of the ESD protection circuit, Para [0041], Figures 1 and 2).
Regarding claim 7, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud further teaches
wherein the semiconductor layer has the second conductivity type (see e.g., the silicon epitaxial layer 40 has p-type doping, Para [0040], Figure 2).
Regarding claim 9, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud does not explicitly teach
“wherein the fluorinated-plasma is a carbon fluoride plasma”.
In a similar field of endeavor Reiner teaches
wherein the fluorinated-plasma is a carbon fluoride plasma (see e.g., The fluorine injection gas mixture 126 may include CF.sub.4 (Tetrafluormethan), C.sub.2F.sub.6 (Hexafluorethan), C.sub.3F.sub.8 (Perfluorpropan), C.sub.4F.sub.6 (Perfluorbutadien), Para [0039], Figures 4-9).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Reiner’s teachings of wherein the fluorinated-plasma is a carbon fluoride plasma in the method of Arnaud in order to prevent the unstable behavior between the dielectric and the semiconductor substrate.
Regarding claim 10, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud does not explicitly teach
“wherein the fluorinated-plasma is an inductive-coupling plasma”.
In a similar field of endeavor Reiner teaches
wherein the fluorinated-plasma is an inductive-coupling plasma (see e.g., fluorine plasma is generated by applying RF signal to an inductive coil 131, Para [0041], Figures 7)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Reiner’s teachings of wherein the fluorinated-plasma is an inductive-coupling plasma in the method of Arnaud so that the plasma is substantially devoid of ionic state fluorine particles.
Regarding claim 11, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud further teaches
wherein the electrically-insulating layer is a silicon oxide layer (see e.g., the insulator layer 50 is a thermal oxide that is silicon oxide, Para [0043], Figure 2).
Regarding claim 12, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud further teaches
wherein the substrate and the semiconductor layer include silicon (see e.g., the substrate 34/ 36 and the epitaxial layer 40 include silicon, Paras [0036], [0037], [0040], Figure 2).
Regarding claim 13, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud further teaches
wherein the substrate has a N-type doping and the semiconductor layer has a P-type doping (see e.g., the silicon substrate including regions 34 and 36 is n-type doped and the silicon epitaxial layer 40 is p-type doped, Paras [0036], [0040], Figure 2).
Regarding claim 14, Arnaud teaches a method (see e.g., electrostatic discharge (ESD) protection circuit, Figures 1 and 2) comprising:
Arnaud discloses the steps to form the ESD device in paragraph [0048], “The method further comprises steps of forming layer 40 by epitaxy, of forming regions 42 and 44 in layer 40, of forming insulating wells 32 between the different areas, of forming layer 50, and of forming conductive layers 52. The method also comprises the steps of doping the different regions and layers.”
Arnaud does not explicitly teach their sequence. However, it is reasonably understood that the layers would be formed sequentially.
First, the n-type substrate 34/36 and the p-type doped region 38, which is flush with its surface are formed. Only after this step can the p-type epitaxial layer 40 be deposited, with its upper portion doped with n-type dopants to form for example, region 42 and made flush with the surface. Subsequently, an insulating layer 50 may be formed over the structure.
forming a first semiconductor layer of a first conductivity type (see e.g., N-type silicon substrate 34, Para [0036], Figure 2) having a first surface opposite a second surface along a first direction, the first semiconductor layer having a first thickness along the first direction and a first width along a second direction that is transverse to the first direction (see e.g., silicon substrate 34 has a first surface opposite a second surface along a first direction and has a first thickness along the first direction and a first width along a second direction that is traverse to the first direction as shown in Figure 2);
after forming the first semiconductor layer of the first conductivity type, forming a first semiconductor area of a second conductivity type opposite to the first conductivity type in the first semiconductor layer (see e.g., P-type silicon region 38 located in the upper portion of N-type silicon substrate 34, Para [0037], Figure 2), the first semiconductor area having a first surface that is coplanar with the first surface of the first semiconductor layer (see e.g., the silicon region 38 has a first surface coplanar with the first surface of the silicon substrate 34 as shown in Figure 2), the first semiconductor area having a second thickness along the first direction that is smaller than the first thickness (see e.g., the silicon region 38 has a second thickness along the first direction that is smaller than the first thickness of the silicon substrate 34 as shown in Figure 2) and a second width along the second direction that is smaller than the first width (see e.g., the silicon region 38 has a second width along the second direction that is smaller than the first width of the silicon substrate 34 as shown in Figure 2);
after forming the first semiconductor area of the second conductivity, forming a second semiconductor layer of the second conductivity type on the first surface of the first semiconductor area and the first surface of the first semiconductor layer (see e.g., forming a P-type epitaxial silicon layer 40 on the silicon substrate 34 and the silicon region 38, Para [0040], Figure 2), the second semiconductor layer having a third width along the second direction that is greater than the second width (see e.g., the epitaxial silicon layer 40 has a third width along the second direction that is greater than the second width of the silicon region 38 as shown in Figure 2);
after forming the second semiconductor layer of the second conductivity type, forming a second semiconductor area of the first conductivity type in the second semiconductor layer (see e.g., the upper portion of epitaxial silicon layer 40 includes a N-type region for example, 42a, Para [0041], Figure 2), the second semiconductor area having a fourth width that is smaller than the second width (see e.g., region 42a has a fourth width that is smaller than the second width of the silicon region 38 as shown in Figure 2), the second semiconductor area having a first surface that is coplanar with a first surface of the second semiconductor layer (see e.g., the region 42a has a first surface that is coplanar with a first surface of the epitaxial silicon layer 40 as shown in Figure 2) and a second surface that is between the first surface of the second semiconductor area and the first surface of the first semiconductor area (see e.g., the region 42a has a second surface that is between the first surface of region 42a and the first surface of region 38 as shown in Figure 2);
Arnaud does not explicitly teach
“after forming the second semiconductor area of the second conductivity type, treating an entirety of the first surface of the second semiconductor area and an entirety of the first surface of the second semiconductor layer with ….fluorine atoms …. implanted in the first surface of the second semiconductor area and the first surface of the second semiconductor layer”.
In a similar field of endeavor Ohashi teaches
after forming the second semiconductor area of the second conductivity type, treating an entirety of the first surface of the second semiconductor area and an entirety of the first surface of the second semiconductor layer with ….fluorine atoms …. implanted in the first surface of the second semiconductor area and the first surface of the second semiconductor layer (see e.g., the first interface region 40 having fluorine distribution formed over the upper surface of drift layer 14 and the p-type doped regions 20 and n-type doped regions 18, Para [0041], [0053], Figure 5).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Ohashi’s teachings of after forming the second semiconductor area of the second conductivity type, treating an entirety of the first surface of the second semiconductor area and an entirety of the first surface of the second semiconductor layer with ….fluorine atoms …. implanted in the first surface of the second semiconductor area and the first surface of the second semiconductor layer in the method of Arnaud so that fluorine may bond to the dangling bond of silicon in the top portion of the semiconductor layer and form the termination structure.
Arnaud does not explicitly teach
“treating…with a fluorinated-plasma process in which fluorine atoms are implanted ..”
In a similar field of endeavor Reiner teaches
treating…with a fluorinated-plasma process in which fluorine atoms are implanted.. (see e.g., the first lateral surface section 112 of the substrate 100 is fluorine treated by a fluorine plasma 116. The fluorine plasma 116, i.e., a plasma that at least partially includes fluorine molecules or atoms, is generated by an RF signal that causes particles in the fluorine injection gas mixture 126 to ionize and transform the fluorine injection gas mixture 126 into a plasma state. The fluorine injection gas mixture 126 may include CF.sub.4 (Tetrafluormethan), C.sub.2F.sub.6 (Hexafluorethan), C.sub.3F.sub.8 (Perfluorpropan), C.sub.4F.sub.6 (Perfluorbutadien), Paras [0035], [0037], [0039]- [0043], Figures 4-9);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Reiner’s teachings of treating…with a fluorinated-plasma process in which fluorine atoms are implanted in the method of Arnaud as it is one of the various methods available to provide the surface of the semiconductor layer with fluorine atoms.
Regarding claim 15, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 14 as mentioned above. Arnaud further teaches
comprising forming an electrically-insulating layer on the first surface of the second semiconductor layer and the first surface of the second semiconductor area”.
Arnaud discloses that the insulating layer includes openings indicating that the insulating layer could either be selectively deposited on the surface of the second semiconductor layer or deposited on both the surface of the second semiconductor layer and the surface of the second semiconductor region and later etched to expose for example, the n-type region 42 within the layer 40. It would be obvious to try any one of the combination. The rationale to support a conclusion that the claim would have been obvious is that “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103.” KSR, 550 U.S. at 421, 82 USPQ2d at 1397. MPEP 2143 (E).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement blanket deposit the insulating layer and then etch it to form openings as this is one of the most common practice in semiconductor devices.
Regarding claim 16, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 14 as mentioned above. Arnaud further teaches
wherein the second semiconductor layer is positioned centrally in relation to the first semiconductor layer along the first direction (see e.g., the region 42a is positioned centrally in relation to the silicon region 38 along the first direction as shown in Figure 2).
Regarding claim 17, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 15 as mentioned above. Arnaud further teaches
comprising etching through the electrically-insulating layer to expose the second semiconductor area.
Arnaud discloses that the insulating layer includes openings indicating that the insulating layer could either be selectively deposited on the surface of the second semiconductor layer or deposited on both the surface of the second semiconductor layer and the surface of the second semiconductor region and later etched to expose for example, the n-type region 42 within the layer 40. It would be obvious to try any one of the combination. The rationale to support a conclusion that the claim would have been obvious is that “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103.” KSR, 550 U.S. at 421, 82 USPQ2d at 1397. MPEP 2143 (E).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement blanket deposit the insulating layer and then etch it to form openings as this is one of the most common practice in semiconductor devices.
Regarding claim 18, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 14 as mentioned above. Arnaud further teaches
wherein the first conductivity type is an N conductivity type and the second conductivity type is a P conductivity type (see e.g., the substrate 34 and the region 42a have N-type conductivity that is, the first conductivity type and the region 38 and the epitaxial layer 40 have P-type conductivity that is, second conductivity type, Figure 2).
Regarding claim 19, Arnaud teaches a method for manufacturing a device (see e.g., electrostatic discharge (ESD) protection circuit, Figures 1 and 2), comprising:
Arnaud discloses the steps to form the ESD device in paragraph [0048], “The method further comprises steps of forming layer 40 by epitaxy, of forming regions 42 and 44 in layer 40, of forming insulating wells 32 between the different areas, of forming layer 50, and of forming conductive layers 52. The method also comprises the steps of doping the different regions and layers.”
Arnaud does not explicitly teach their sequence. However, it is reasonably understood that the layers would be formed sequentially.
First, the n-type substrate 34/36 and the p-type doped region 38, which is flush with its surface are formed. Only after this step can the p-type epitaxial layer 40 be deposited, with its upper portion doped with n-type dopants to form for example, region 42 and made flush with the surface. Subsequently, an insulating layer 50 may be formed over the structure.
forming a first semiconductor area in a semiconductor substrate (see e.g., silicon area 38 located in the upper portion of silicon substrate 34, Para [0037], Figure 2), the semiconductor substrate having a first conductivity type of a first dopant level (see e.g., the silicon substrate 34 is heavily doped with n-type dopants, Para [0036], Figure 2) and the first semiconductor area having a second conductivity type opposite the first conductivity type, the semiconductor area having a second dopant level (see e.g., silicon area 38 is heavily doped with p-type dopants, Para [0037], Figure 2);
after forming the first semiconductor area in the semiconductor substrate, forming, on and covering the semiconductor substrate and the first semiconductor area, a semiconductor layer having the second conductivity type at a third dopant level less than the second dopant level, the semiconductor layer having a first surface facing away from the first semiconductor area and the semiconductor substrate (see e.g., forming a p-type epitaxial silicon layer 40 on the silicon substrate 34 and the silicon region 38. The epitaxial layer 40 is lightly doped with p-type dopants, Para [0040], Figure 2);
after forming the semiconductor layer, forming a second semiconductor area in the semiconductor layer with a second surface flush with the first surface (see e.g., the upper portion of epitaxial silicon layer 40 includes a region for example, 42a. the upper surface of 42a is coplanar with the upper surface of layer 40 Para [0041], Figure 2), the second semiconductor area having the first conductivity type at the first dopant level (see e.g., region 42a is heavily doped with n-type dopants, Para [0041], Figure 2), the second semiconductor area being positioned centrally in relation to the first semiconductor area along a first direction (see e.g., the region 42a is positioned centrally in relation to the silicon region 38 along a first direction as shown in Figure 2) and having a first width along a second direction transverse to the first direction (see e.g., the region 42a has a first width along a second direction transverse to the first direction as shown in Figure 2);
after forming the second semiconductor area in the semiconductor layer, forming an electrically-insulating layer on the semiconductor layer; and (see e.g., forming the insulator layer 50 on the epitaxial silicon layer 40, Para [0043], Figure 2)
etching a gap in the electrically-insulating layer
Arnaud discloses that the insulating layer includes openings indicating that the insulating layer could either be selectively deposited on the surface of the second semiconductor layer or deposited on both the surface of the second semiconductor layer and the surface of the second semiconductor region and later etched to expose for example, the n-type region 42 within the layer 40. It would be obvious to try any one of the combination. The rationale to support a conclusion that the claim would have been obvious is that “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103.” KSR, 550 U.S. at 421, 82 USPQ2d at 1397. MPEP 2143 (E).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement blanket deposit the insulating layer and then etch it to form openings as this is one of the most common practice in semiconductor devices.
the gap being positioned centrally in relation to the first semiconductor area along the first direction (see e.g., the opening exposing region 42a in insulator 50 is positioned centrally in relation to the silicon region 38 along the first direction as shown in Figure 2) and having a second width along the second direction that is at least as wide as the first width (see e.g., the opening exposing region 42a in insulator 50 has a second width along the second direction that is at least as wide as the first width of region 42a as shown in Figure 2).
Arnaud does not explicitly teach
“treating an entirety of the first surface of the semiconductor layer and in a first an entirety of the second surface of the second semiconductor area with … fluorine atoms .. implanted in the second semiconductor area and the semiconductor layer”;
In a similar field of endeavor Ohashi teaches
treating an entirety of the first surface of the semiconductor layer and in a first an entirety of the second surface of the second semiconductor area with … fluorine atoms .. implanted in the second semiconductor area and the semiconductor layer (see e.g., the first interface region 40 having fluorine distribution formed over the upper surface of drift layer 14 and the p-type doped regions 20 and n-type doped regions 18, Para [0041], [0053], Figure 5).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Ohashi’s teachings of treating an entirety of the first surface of the semiconductor layer and in a first an entirety of the second surface of the second semiconductor area with … fluorine atoms .. implanted in the second semiconductor area and the semiconductor layer in the method of Arnaud so that fluorine may bond to the dangling bond of silicon in the top portion of the semiconductor layer and form the termination structure.
Arnaud does not explicitly teach
“treating….with a fluorinated-plasma during a fluorinated plasma treatment process in which fluorine atoms are implanted….”
In a similar field of endeavor Reiner teaches
treating….with a fluorinated-plasma during a fluorinated plasma treatment process in which fluorine atoms are implanted…. (see e.g., the first lateral surface section 112 of the semiconductor substrate 100 is fluorine treated by a fluorine plasma 116. The fluorine plasma 116, i.e., a plasma that at least partially includes fluorine molecules or atoms, is generated by an RF signal that causes particles in the fluorine injection gas mixture 126 to ionize and transform the fluorine injection gas mixture 126 into a plasma state. The fluorine injection gas mixture 126 may include CF.sub.4 (Tetrafluormethan), C.sub.2F.sub.6 (Hexafluorethan), C.sub.3F.sub.8 (Perfluorpropan), C.sub.4F.sub.6 (Perfluorbutadien), Paras [0035], [0037], [0039]- [0043], Figures 4-9);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Reiner’s teachings of treating….with a fluorinated-plasma during a fluorinated plasma treatment process in which fluorine atoms are implanted…. in the method of Arnaud as it is one of the various methods available to provide the surface of the semiconductor layer with fluorine atoms.
Regarding claim 20, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 19 as mentioned above. Arnaud further teaches
wherein a first side of the gap extends along a third direction that is transverse to both the first direction and the second direction (see e.g., a first side of the gap exposing the region 42a in the insulator 50 extends along a third direction that is transverse to both the first and second direction as shown in Figure 2).
Claims 2, 8 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Arnaud et al. (US 2019/0296004 A1; hereafter Arnaud) in view of Reiner et al. (US 2016/0260817 A1; hereafter Reiner) and further in view of Keena et al. (US 2009/0079022 A1; hereafter Keena).
Regarding claims 2, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud does not explicitly teach
“wherein the first conductivity type is an N conductivity type and the second conductivity type is a P conductivity type”.
In a similar field of endeavor Keena teaches
wherein the first conductivity type is an N conductivity type and the second conductivity type is a P conductivity type (see e.g., substrate 21 is formed with a P-type conductivity that is, second conductivity and the region 24 and the layer 27 both have N-type conductivity that is, first conductivity, Paras [0017], [0018], Figure 2).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Keena’s teachings of wherein the first conductivity type is an N conductivity type and the second conductivity type is a P conductivity type in the method of Arnaud as per device requirements.
Regarding claim 8, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud does not explicitly teach
“wherein the semiconductor layer has a doping level between
1
x
10
13
atoms/
c
m
3
and
1
x
10
15
atoms/
c
m
3
”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Keena teaches
wherein the semiconductor layer has a doping level between
1
x
10
13
atoms/
c
m
3
and
1
x
10
15
atoms/
c
m
3
(see e.g., layer 27 has a doping concentration between about 1.times.10.sup.13 and 1.times.10.sup.17 atoms/cm.sup.3., Para [0018], Figure 2).
Therefore, it would have been obvious to ne skilled in the art at the time the invention was effectively filed to implement Keena’s teachings of wherein the semiconductor layer has a doping level between
1
x
10
13
atoms/
c
m
3
and
1
x
10
15
atoms/
c
m
3
in the method of Arnaud in order to optimize device performance.
Regarding claim 21, Arnaud, as modified by Ohashi and Reiner, teaches the limitations of claim 1 as mentioned above. Arnaud further teaches
wherein:
the semiconductor substrate has a first dopant level (see e.g., the substrate 34 is heavily doped with n-type dopants, Figure 2);
the first semiconductor region has a second dopant level (see e.g., region 38 is heavily doped with p-type dopants, Figure 2);
the semiconductor layer has a third dopant level less than the second dopant level; and (see e.g., layer 40 is lightly doped with p-type dopants, Figure 2)
the second semiconductor region has the first dopant level (see e.g., region 42a is heavily doped with n-type dopants, Figure 2).
Arnaud does not explicitly teach
“the first conductivity type is a N-type;
the second conductivity type is a P-type”;
In a similar field of endeavor Keena teaches
the first conductivity type is a N-type (see e.g., region 24 and layer 27 both are doped with N-type dopants that is, have first conductivity type, Paras [0017] – [0020], Figure 2);
the second conductivity type is a P-type (see e.g., the substrate 21 is doped with p-type dopants that is, has the second conductivity type, Para [0017], Figure 2);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Keena’s teachings of the first conductivity type is a N-type; the second conductivity type is a P-type in the method of Arnaud as per device requirements.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210217746 A1
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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