DETAILED ACTION
Non-Final Rejection
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/30/2026 has been entered.
Response to Arguments
Applicant's arguments filed 03/30/2026 have been fully considered but they are not persuasive.
Regarding applicants arguments to claim 1, applicant states “Halteren does not teach or suggest that the electroacoustic transducers are mounted on flex-strip 106 to form an ASIC.”, examiner respectfully disagrees. Halteren teaches the integrated circuit 114, which may be an ASIC, provides the voltage and output signal amplification for the two electroacoustic transducers 102 & 104. No where in the applicants claims does the applicant claim mounting the transducer to form an ASIC, instead applicant claims an Application-Specific Integrated Circuit (ASIC) formed from a capacitive micromachined ultrasound transducer (CMUT) wafer that is bonded to a complementary metal-oxide semiconductor (CMOS) wafer. Halteren teaches the integrated circuit 114 (ASIC) is formed from an ultrasound transducer wafer (102, 104) that is bonded to a complementary metal-oxide semiconductor (CMOS) wafer (806, 906). Thus, Halteren, in view of Fish and Wodnicki, properly teaches the limitation as written. (See Paragraphs 10, 30, 29, 46-47, Claims 6, 8, 34, Figs.1B, 8-9 of Halteren)
Further regarding applicants arguments to claim 1, applicant states “Wodnicki does not teach or suggest that any input or output is redistributed from the bottom surface of a CMUT wafer to an upper surface of the CMUT wafer.”, examiner respectfully disagrees. Wodnicki teaches, as illustrated in figs.6A-6B and described in paragraphs 24, 72, 75, routing of several types of I/O lines into the array 90 of ASIC cells 92. Thus, Wodnicki properly teaches the input or output (I/O lines) is redistributed from the bottom surface of a CMUT wafer (bottom of figs.6A-6B) to an upper surface of the CMUT wafer (upper of figs.6A-6B).
Regarding applicants arguments to claim 7, applicant states “Halteren is silent as to how the amplifier is physically connected to the transducers, let alone if it is directly coupled or coupled using an interposer or flex circuits.”. No where in the discloser of Halteren does it teach the amplifier is coupled to the transducer with an interposer or flex circuit, instead Halteren teaches the amplifier (806) is directly coupled (connected) to the electroacoustic transducers (802,804) seemingly without the use of an interposer or flex circuit. Thus, the examiner believes, from examiners broadest reasonable interpretation of the claim language, that Halteren properly teaches the claim as written. (See Paragraphs 46-47, Figs.8-9 of Halteren) Furthermore, examiner notes claim 7 is rejected with the incorporation of the teachings of Fish as detailed below.
Regarding applicants arguments to claim 8, applicant states “Applicant objects to the use of "Design Choice." When the claimed features perform differently from the prior art, a finding of obvious design choice is precluded. In re Gal, 980 F.2d 717, 719 (Fed. Cir. 1992) (finding of obvious design choice precluded when claimed structure and the function it performs are different from the prior art). Here, the claimed features relate to the CMOS wafer comprising an ASIC which is responsible for transducing an acoustic signal into an electrical signal (see paragraph [0045] of the subject application). This is different from the CMOS of Halteren, which is an amplifier of electrical signals.” and “Additionally, the Office states a change of size is within the purview of one skilled in the art. Applicant respectfully disagrees. One skilled in the art would face technical problems in reducing a thickness of the CMUT wafer to be less than the thickness of the CMOS wafer. Those technical problems are overcome with the claimed ultrasound probe. As discussed in paragraph [0061] of the subject application, an advantage of the claimed ultrasound probe is that the CMUT wafer and CMOS wafer can be diced at the same time, which allows the CMUT wafer to be thinner than it would be in a conventional ultrasound probe where the CMUT wafer needs to be processed separately from the CMOS wafer which forms the ASIC.” Halteren teaches the integrated circuit 114, which may be an ASIC, provides the voltage and output signal amplification for the two electroacoustic transducers 102 & 104. Fish is introduced to teach the CMUT wafer as detailed below. No where in applicants discloser does applicant state an advantage of the claimed thickness as identified by paragraphs 45 and 61 of applicants discloser. It is unclear to the examiner what “technical problem” applicant is referring to/addressing when changing thickness of the respective wafers and why one of ordinary skill would not do so.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Halteren, Fish, Wodnicki and Yang are all in the same field of endeavor of ultrasound detection using transducers and sound receivers and thus it would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate teachings of Fish, Wodnicki and Yang respectively to in order to bring the ultrasound transducer element tile in a particular orientation as selected by the beam former and for the ultrasound transducer element tile to produce a part of the ultrasound beam to be formed in a desired direction and in order to avoid disruption in pitch among transducer cells and image different portions of a region under examination and in order to cause the ultrasound waveform to be sent and received from the transducer elements, and may also generate electrical signals from the received ultrasound energy and to construct images of the object therefrom using frames.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Halteren (US 20080192962 A1) in view of Fish (WO 2017182416 A1) and Wodnicki (US 20090182229 A1).
Regarding claim 1, Halteren teaches a device, comprising: an electroacoustic module (100, 800) comprising an Application-Specific Integrated Circuit (ASIC) (114) formed from a ultrasound transducer wafer (102, 104) that is bonded to a complementary metal-oxide semiconductor (CMOS) wafer (806, 906) (the one or more bias voltage generators and the amplifier are integrated on a single semiconductor substrate, such as a sub-micron CMOS integrated circuit). (Paragraphs 10, 30, 29, 46-47, Claims 6, 8, 34, Figs.1B, 8-9)
Halteren does not explicitly teach an ultrasound probe and a capacitive micromachined ultrasound transducer (CMUT) and dicing lanes of the CMOS wafer have been removed or precluded to extend one or more dimensions of dies of the ASIC and the electroacoustic module has a front side formed of an upper surface of the CMUT wafer, the upper surface of the CMUT wafer positioned vertically opposite a bottom surface of the CMUT wafer including: an active area with an array of CMUT cells and an input/output (I/O) region including input and output contacts of the ASIC that are redistributed from the bottom surface of the CMUT wafer to the upper surface of the CMUT wafer and wherein the I/O region is arranged adjacent to the active area, along a periphery or outer edge of the electroacoustic module, in a space created by the extended dimensions of the dies of the ASIC.
Fish teaches an ultrasound probe (10) and a capacitive micromachined ultrasound transducer (CMUT) (CMUT array 110) and dicing lanes of the CMOS wafer (disclosed components may be fabricated from CMOS compatible materials) (Fig.5) have been removed or precluded to extend one or more dimensions of dies of the ASIC (the ultrasound transducer element tile 100 may comprise a substrate 140 such as a silicon substrate on which an integrated circuit (IC) arrangement such as an application- specific integrated circuit (ASIC) is formed). (Page.8, lines 14-33, Page.9, lines 19-20, Page.18, lines 12-15, Page.13, lines 18-27, Figs.1, 5)
Fish also teaches the electroacoustic module has a front side (Fig.5) formed of an upper surface of the CMUT wafer (110), the upper surface of the CMUT wafer positioned vertically opposite a bottom surface of the CMUT wafer including: an active area with an array of CMUT cells (CMUT cells 100). (Abstract, Page.12, lines 17-21, Page.14, lines 3-17, Figs.1, 5)
Wodnicki teaches an input/output (I/O) region (I/O lines) including input and output contacts of the ASIC (I/O lines into the array 90 of ASIC cells 92) that are redistributed from the bottom surface of the CMUT wafer to the upper surface of the CMUT wafer (cMUT cells ) and wherein the I/O region is arranged adjacent to the active area (92), along a periphery or outer edge (allocated I/O regions have been positioned along the periphery of the ASICs) (Fig.6B, right hand side) of the electroacoustic module, in a space created by the extended dimensions of the dies of the ASIC. (Paragraphs 71-72, 75, 80, Figs.6B)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate an ultrasound probe and a capacitive micromachined ultrasound transducer (CMUT) and dicing lanes of the CMOS wafer have been removed or precluded to extend one or more dimensions of dies of the ASIC and the electroacoustic module has a front side formed of an upper surface of the CMUT wafer, the upper surface of the CMUT wafer positioned vertically opposite a bottom surface of the CMUT wafer including: an active area with an array of CMUT cells as taught by Fish in order to bring the ultrasound transducer element tile in a particular orientation as selected by the beam former and for the ultrasound transducer element tile to produce a part of the ultrasound beam to be formed in a desired direction and further modify Halteren to incorporate an input/output (I/O) region including input and output contacts of the ASIC that are redistributed from the bottom surface of the CMUT wafer to the upper surface of the CMUT wafer and wherein the I/O region is arranged adjacent to the active area, along a periphery or outer edge of the electroacoustic module, in a space created by the extended dimensions of the dies of the ASIC as taught by Wodnicki in order to avoid disruption in pitch among transducer cells and image different portions of a region under examination.
Regarding claim 3, Halteren teaches wherein the I/O regions are located on opposite sides of the active area, and wherein the I/O regions further includes CMUT bias contacts. (Paragraphs 10, 30, Figs.1A-1B)
Halteren does not explicitly teach wherein multiple electroacoustic module dies are arranged to form a tile and the I/O regions of the multiple electroacoustic module dies are located on opposite sides of the active areas of the multiple electroacoustic module dies.
Wodnicki teaches wherein multiple electroacoustic module dies are arranged to form a tile and the I/O regions of the multiple electroacoustic module dies are located on opposite sides of the active areas of the multiple electroacoustic module dies. (Fig.6B)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate wherein multiple electroacoustic module dies are arranged to form a tile and the I/O regions of the multiple electroacoustic module dies are located on opposite sides of the active areas of the multiple electroacoustic module dies as taught by Wodnicki in order to avoid disruption in pitch among transducer cells and image different portions of a region under examination.
Regarding claim 4, Halteren teaches wherein the I/O regions is configured to be coupled to interconnecting circuits extending away from the active area. (Paragraphs 10, 30, Figs.1A-1B)
Regarding claim 5, Halteren teaches wherein a clearance distance is provided between the active area and the I/O region, and wherein no CMUT cells or output contacts are positioned in the clearance distances. (Fig.1B)
Regarding claim 7, Halteren teaches wherein the wafer is directly coupled to the CMOS wafer without an interposer or flex circuits arranged therebetween. (Paragraphs 46-47, Figs.8-9)
Halteren does not explicitly teach the CMUT wafer
Fish teaches the CMUT wafer. (Page.8, lines 14-33, Page.9, lines 19-20, Figs.1, 5)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate the CMUT wafer as taught by Fish in order to bring the ultrasound transducer element tile in a particular orientation as selected by the beam former and for the ultrasound transducer element tile to produce a part of the ultrasound beam to be formed in a desired direction
Regarding claim 8, Halteren teaches wherein a thickness of the wafer is with respect to a thickness of the CMOS wafer. (Paragraphs 30, 33, 39) Halteren discloses the claimed invention except for a thickness of the wafer is less than a thickness of the CMOS wafer. It would have been an obvious matter of design choice to incorporate a thickness of the wafer is less than a thickness of the CMOS wafer, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Halteren does not explicitly teach the CMUT wafer
Fish teaches the CMUT wafer. (Page.8, lines 14-33, Page.9, lines 19-20, Figs.1, 5)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate the CMUT wafer as taught by Fish in order to bring the ultrasound transducer element tile in a particular orientation as selected by the beam former and for the ultrasound transducer element tile to produce a part of the ultrasound beam to be formed in a desired direction.
Claim(s) 2 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Halteren in view of Fish, Wodnicki and Yang (US 20220299634 A1).
Regarding claim 2, Halteren does not explicitly teach wherein the CMOS wafer is diced along no more than one direction to form ASIC dies, and wherein dimensions of the CMUT wafer along a plane of the CMUT wafer is equal to dimensions of the CMOS wafer, along a plane of the CMOS wafer.
Yang teaches wherein the CMOS wafer is diced along no more than one direction to form ASIC dies, and wherein dimensions of the CMUT wafer along a plane of the CMUT wafer is equal to dimensions of the CMOS wafer, along a plane of the CMOS wafer. (Paragraphs 91, 40-41, 35, Figs.3B-4)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate wherein the CMOS wafer is diced along no more than one direction to form ASIC dies, and wherein dimensions of the CMUT wafer along a plane of the CMUT wafer is equal to dimensions of the CMOS wafer, along a plane of the CMOS wafer in order to reduce the manufacturing cost since the transducers may be fabricated in high volume and at low cost.
Regarding claim 21, Halteren teaches output contacts positioned adjacent to the array of CMUTs, along a periphery of the respective tile and at a front side of the tile. (Paragraph 30, Figs.1A-1B)
Halteren does not explicitly teach wherein the electroacoustic module comprises a plurality of tiles, each tile comprising: an array of capacitive micromachined ultrasound transducers (CMUTs); an application-specific integrated circuit (ASIC) arranged below the array of CMUTs and electrically coupled to the array of CMUTs.
Yang teaches wherein the electroacoustic module comprises a plurality of tiles, each tile comprising: an array of capacitive micromachined ultrasound transducers (CMUTs) (302). (Paragraphs 48, 88, 78-79, Fig.3B)
Yang also teaches an application-specific integrated circuit (ASIC) (106) arranged below the array of CMUTs (302) and electrically coupled to the array of CMUTs. (Paragraphs 63, 88, Fig.3B)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate wherein the electroacoustic module comprises a plurality of tiles, each tile comprising: an array of capacitive micromachined ultrasound transducers (CMUTs); an application-specific integrated circuit (ASIC) arranged below the array of CMUTs and electrically coupled to the array of CMUTs in order to cause the ultrasound waveform to be sent and received from the transducer elements, and may also generate electrical signals from the received ultrasound energy and to construct images of the object therefrom using frames.
Regarding claim 22, Halteren teaches wherein the output contacts are arranged in the input/output (I/O) region adjacent to the array of CMUTs, and wherein a number of columns of the output contacts is not equal to a number of columns of ASIC pads of the ASIC in the I/O region. (Paragraphs 10, 30, Figs.1A-1B)
Regarding claim 23, Halteren does not explicitly teach wherein the ASIC is compatible for electrical coupling with more than one configuration of the array of CMUTs.
Yang teaches wherein the ASIC is compatible for electrical coupling with more than one configuration of the array of CMUTs. (Paragraphs 63, 88, Fig.3B)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate wherein the ASIC is compatible for electrical coupling with more than one configuration of the array of CMUTs in order to cause the ultrasound waveform to be sent and received from the transducer elements, and may also generate electrical signals from the received ultrasound energy and to construct images of the object therefrom using frames.
Allowable Subject Matter
Claim 24 is allowed.
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDALLAH ABULABAN whose telephone number is (571)272-4755. The examiner can normally be reached Monday - Friday 7:00am-3:00pm EST.
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/ABDALLAH ABULABAN/Primary Examiner, Art Unit 3645
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