Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The amendment filed 11/03/2025 has been entered. Claims 1-8 and 21-23 remain pending in the application.
Response to Arguments
Applicant' s arguments with respect to claim(s) 1 and all subsequent dependent claims have been considered but are moot in view of the references cited in the most current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Halteren (US 20080192962 A1) in view of Fish (WO 2017182416 A1) and Wodnicki (US 20090182229 A1).
Regarding claim 1, Halteren teaches a device, comprising: an electroacoustic module (100, 800) comprising an Application-Specific Integrated Circuit (ASIC) (114) formed from a ultrasound transducer wafer (102, 104) that is bonded to a complementary metal-oxide semiconductor (CMOS) wafer (806, 906) (the one or more bias voltage generators and the amplifier are integrated on a single semiconductor substrate, such as a sub-micron CMOS integrated circuit). (Paragraphs 10, 30, 29, 46-47, Claims 6, 8, 34, Figs.1B, 8-9)
Halteren does not explicitly teach an ultrasound probe and a capacitive micromachined ultrasound transducer (CMUT) and dicing lanes of the CMOS wafer have been removed or precluded to extend one or more dimensions of dies of the ASIC and the electroacoustic module has a front side formed of a surface of the CMUT wafer, the surface of the CMUT wafer including: an active area with an array of CMUT cells and an input/output (I/O) region including input and output contacts of the ASIC that are redistributed to the surface of the CMUT wafer; wherein the I/O region is arranged adjacent to the active area, along a periphery or outer edge of the electroacoustic module, in a space created by the extended dimensions of the dies of the ASIC
Fish teaches an ultrasound probe (10) and a capacitive micromachined ultrasound transducer (CMUT) (CMUT array 110) and dicing lanes of the CMOS wafer (disclosed components may be fabricated from CMOS compatible materials) (Fig.5) have been removed or precluded to extend one or more dimensions of dies of the ASIC (the ultrasound transducer element tile 100 may comprise a substrate 140 such as a silicon substrate on which an integrated circuit (IC) arrangement such as an application- specific integrated circuit (ASIC) is formed). (Page.8, lines 14-33, Page.9, lines 19-20, Page.18, lines 12-15, Page.13, lines 18-27, Figs.1, 5)
Fish also teaches the electroacoustic module has a front side (Fig.5) formed of a surface of the CMUT wafer (110), the surface of the CMUT wafer including: an active area with an array of CMUT cells (CMUT cells 100). (Abstract, Page.12, lines 17-21, Page.14, lines 3-17, Figs.1, 5)
Wodnicki teaches an input/output (I/O) region (I/O lines) including input and output contacts of the ASIC (I/O lines into the array 90 of ASIC cells 92) that are redistributed to the surface of the CMUT wafer (cMUT cells ); wherein the I/O region is arranged adjacent to the active area (92), along a periphery or outer edge (allocated I/O regions have been positioned along the periphery of the ASICs) (Fig.6B, right hand side) of the electroacoustic module, in a space created by the extended dimensions of the dies of the ASIC. (Paragraphs 71-72, 75, 80, Figs.6B)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate an ultrasound probe and a capacitive micromachined ultrasound transducer (CMUT) and dicing lanes of the CMOS wafer have been removed or precluded to extend one or more dimensions of dies of the ASIC and the electroacoustic module has a front side formed of a surface of the CMUT wafer, the surface of the CMUT wafer including: an active area with an array of CMUT cells as taught by Fish in order to bring the ultrasound transducer element tile in a particular orientation as selected by the beam former and for the ultrasound transducer element tile to produce a part of the ultrasound beam to be formed in a desired direction and further modify Halteren to incorporate an input/output (I/O) region including input and output contacts of the ASIC that are redistributed to the surface of the CMUT wafer; wherein the I/O region is arranged adjacent to the active area, along a periphery or outer edge of the electroacoustic module, in a space created by the extended dimensions of the dies of the ASIC as taught by Wodnicki in order to avoid disruption in pitch among transducer cells and image different portions of a region under examination.
Regarding claim 3, Halteren teaches wherein the I/O regions are located on opposite sides of the active area, and wherein the I/O regions further includes CMUT bias contacts. (Paragraphs 10, 30, Figs.1A-1B)
Halteren does not explicitly teach wherein multiple electroacoustic module dies are arranged to form a tile and the I/O regions of the multiple electroacoustic module dies are located on opposite sides of the active areas of the multiple electroacoustic module dies.
Wodnicki teaches wherein multiple electroacoustic module dies are arranged to form a tile and the I/O regions of the multiple electroacoustic module dies are located on opposite sides of the active areas of the multiple electroacoustic module dies. (Fig.6B)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate wherein multiple electroacoustic module dies are arranged to form a tile and the I/O regions of the multiple electroacoustic module dies are located on opposite sides of the active areas of the multiple electroacoustic module dies as taught by Wodnicki in order to avoid disruption in pitch among transducer cells and image different portions of a region under examination.
Regarding claim 4, Halteren teaches wherein the I/O regions is configured to be coupled to interconnecting circuits extending away from the active area. (Paragraphs 10, 30, Figs.1A-1B)
Regarding claim 5, Halteren teaches wherein a clearance distance is provided between the active area and the I/O region, and wherein no CMUT cells or output contacts are positioned in the clearance distances. (Fig.1B)
Regarding claim 7, Halteren teaches wherein the wafer is directly coupled to the CMOS wafer without an interposer or flex circuits arranged therebetween. (Paragraphs 46-47, Figs.8-9)
Halteren does not explicitly teach the CMUT wafer
Fish teaches the CMUT wafer. (Page.8, lines 14-33, Page.9, lines 19-20, Figs.1, 5)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate the CMUT wafer as taught by Fish in order to bring the ultrasound transducer element tile in a particular orientation as selected by the beam former and for the ultrasound transducer element tile to produce a part of the ultrasound beam to be formed in a desired direction
Regarding claim 8, Halteren teaches wherein a thickness of the wafer is with respect to a thickness of the CMOS wafer. (Paragraphs 30, 33, 39) Halteren discloses the claimed invention except for a thickness of the wafer is less than a thickness of the CMOS wafer. It would have been an obvious matter of design choice to incorporate a thickness of the wafer is less than a thickness of the CMOS wafer, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Halteren does not explicitly teach the CMUT wafer
Fish teaches the CMUT wafer. (Page.8, lines 14-33, Page.9, lines 19-20, Figs.1, 5)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate the CMUT wafer as taught by Fish in order to bring the ultrasound transducer element tile in a particular orientation as selected by the beam former and for the ultrasound transducer element tile to produce a part of the ultrasound beam to be formed in a desired direction.
Claim(s) 2 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Halteren in view of Fish, Wodnicki and Yang (US 20220299634 A1).
Regarding claim 2, Halteren does not explicitly teach wherein the CMOS wafer is diced along no more than one direction to form ASIC dies, and wherein dimensions of the CMUT wafer along a plane of the MEMS wafer is equal to dimensions of the CMOS wafer, along a plane of the CMOS wafer.
Yang teaches wherein the CMOS wafer is diced along no more than one direction to form ASIC dies, and wherein dimensions of the CMUT wafer along a plane of the MEMS wafer is equal to dimensions of the CMOS wafer, along a plane of the CMOS wafer. (Paragraphs 91, 40-41, 35, Figs.3B-4)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate wherein the CMOS wafer is diced along no more than one direction to form ASIC dies, and wherein dimensions of the CMUT wafer along a plane of the MEMS wafer is equal to dimensions of the CMOS wafer, along a plane of the CMOS wafer in order to reduce the manufacturing cost since the transducers may be fabricated in high volume and at low cost.
Regarding claim 21, Halteren teaches output contacts positioned adjacent to the array of CMUTs, along a periphery of the respective tile and at a front side of the tile. (Paragraph 30, Figs.1A-1B)
Halteren does not explicitly teach wherein the electroacoustic module comprises a plurality of tiles, each tile comprising: an array of capacitive micromachined ultrasound transducers (CMUTs); an application-specific integrated circuit (ASIC) arranged below the array of CMUTs and electrically coupled to the array of CMUTs.
Yang teaches wherein the electroacoustic module comprises a plurality of tiles, each tile comprising: an array of capacitive micromachined ultrasound transducers (CMUTs) (302). (Paragraphs 48, 88, 78-79, Fig.3B)
Yang also teaches an application-specific integrated circuit (ASIC) (106) arranged below the array of CMUTs (302) and electrically coupled to the array of CMUTs. (Paragraphs 63, 88, Fig.3B)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate wherein the electroacoustic module comprises a plurality of tiles, each tile comprising: an array of capacitive micromachined ultrasound transducers (CMUTs); an application-specific integrated circuit (ASIC) arranged below the array of CMUTs and electrically coupled to the array of CMUTs in order to cause the ultrasound waveform to be sent and received from the transducer elements, and may also generate electrical signals from the received ultrasound energy and to construct images of the object therefrom using frames.
Regarding claim 22, Halteren teaches wherein the output contacts are arranged in an input/output (I/O) region adjacent to the array of CMUTs, and wherein a number of columns of the output contacts is not equal to a number of columns of ASIC pads of the ASIC in the I/O region. (Paragraphs 10, 30, Figs.1A-1B)
Regarding claim 23, Halteren does not explicitly teach wherein the ASIC is compatible for electrical coupling with more than one configuration of the array of CMUTs.
Yang teaches wherein the ASIC is compatible for electrical coupling with more than one configuration of the array of CMUTs. (Paragraphs 63, 88, Fig.3B)
It would have been obvious to one having ordinary skill in the art before the effective filling date to have modified Halteren to incorporate wherein the ASIC is compatible for electrical coupling with more than one configuration of the array of CMUTs in order to cause the ultrasound waveform to be sent and received from the transducer elements, and may also generate electrical signals from the received ultrasound energy and to construct images of the object therefrom using frames.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDALLAH ABULABAN whose telephone number is (571)272-4755. The examiner can normally be reached Monday - Friday 7:00am-3:00pm EST.
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/ABDALLAH ABULABAN/Primary Examiner, Art Unit 3645