DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 18 March 2026 of Applicant’s amendments in which claims 1, 2, 4, 6, and 11 are amended, claims 3 and 5 are cancelled, and claims 21 and 22 are newly added. The Office withdraws the section 112(b) rejections identified in the Office Communication dated 5 January 2026 in view of the amendments.
Response to Arguments
Applicant’s arguments on pages 8 and 9 regarding the drawing objections are persuasive. Accordingly, the Office withdraws the drawing objections identified in the Office Communication dated 5 January 2026.
Applicant's arguments filed 18 March 2026 with respect to the art-based rejections have been fully considered but they are not persuasive.
Applicant argues in the last paragraph of page 9 through page 11 that Kinoshita does not teach the subject matter newly added to claim 1 whereby “the source pad forms a common source terminal … the drain pad forms a common drain terminal.” See, e.g., first paragraph of page 11. Amended claim 1 is rejected over the combined teachings of Takagi, Wang, and Kinoshita. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. MPEP 2145(IV). As this principle applies to the present circumstance, Takagi (not Kinoshita) is cited for teaching the source pad (6) forms a common source terminal … the drain pad (7) forms a common drain terminal. See, e.g., Takagi Fig. 1.
Applicant further argues in the last paragraph of page 9 through page 11 that Kinoshita does not teach the subject matter newly added to claim 1 whereby “an output capacitance of the GaN power transistor is N+1 times a capacitance CDS between the common drain terminal and the common source terminal.” See, e.g., first paragraph of page 11. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. MPEP 2145(IV). As this principle applies to the present circumstance, Takagi is cited for teaching a GaN power transistor comprising (N+1) individual same-size transistors (e.g., fingers) each having a drain-to-source capacitance of CDS electrically connected in parallel, which may alternatively be characterized as (N+1) capacitors of capacitance CDS electrically connected in parallel or (N+1) same-size portions of a single capacitor with each same-size portion having a capacitance CDS. Kinoshita teaches in the second paragraph of column 3 that capacitance is proportional to an area of consideration. Thus, for an instance in which an area of a second portion of the transistor is N times the area of a first portion of the transistor, the total capacitance for the total area (i.e., the sum of the areas for the first and second portions) would be (N+1) times the capacitance of the first portion of the transistor. Alternatively, this may be expressed as: (1) the total capacitance of (N+1) portions of a single capacitor each having a capacitance of CDS is given by the product (N+1) * CDS, (2) the total capacitance of (N+1) same-size capacitors each having a capacitance of CDS and connected in electrical parallel is given by the product (N+1) * CDS, or (3) the total drain-to-source capacitance of (N+1) same-size transistors each having a drain-to-source capacitance of CDS and connected in electrical parallel is given by the product (N+1) * CDS. Applicant discloses this same law of physics in paragraph [0115] of the original specification in relation to the capacitance of same-size transistors connected in electrical parallel by stating that (N+1) same-size transistors connected in electrical parallel have the same drain-to-source capacitance as (N+1) times the drain-to-source capacitance of a single one of the same-size transistors. Regardless of how the physical relationship is expressed, the total capacitance of (N+1) same-size capacitors/(capacitor portions)/transistors connected in electrical parallel is (N+1) times the capacitance of a single one of the same-size capacitors/(capacitor portions)/transistors. Kinoshita’s teachings (e.g., regarding the physics of electrically parallel capacitance) are implicit in the teachings of Takagi and Wang, just as they are in those of Applicant’s paragraph [0115]. As Kinoshita’s teaching applies to the circumstances of claim 1, an output capacitance of Takagi’s GaN power transistor is N+1 times a capacitance CDS between the common drain terminal and the common source terminal because the total capacitance CDS of the (N+1) electrically parallel same-size transistors/(capacitor portions) is (N+1) times the capacitance of a single one of the same-size transistors/(capacitor portions).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi (US20100237437A1) in view of Wang (US20080157222A1) and Kinoshita (US5677866A).
Regarding claim 1, Takagi teaches a Gallium Nitride (GaN) power transistor, comprising:
a source pad (6) {¶0027};
a drain pad (7) {¶0027};
a first gate pad (leftmost 5) {¶0027};
a second gate pad (2nd leftmost 5) {¶0027};
a plurality of unit cells (all groups of 2, 3, 4), wherein each unit cell (single group of 2, 3, 4), from the plurality of unit cells (all groups of 2, 3, 4), includes a source region (3), a drain region (4), and a gate region (2) {¶0027};
a first gate layer (layer interconnecting 2s with leftmost 5) contacting a gate region (2), of a first portion (portion corresponding to leftmost 5) of the plurality of unit cells (all groups of 2, 3, 4), with the first gate pad (leftmost 5) {¶0027}; and
a second gate layer (layer interconnecting 2s with 2nd leftmost 5) contacting a gate region (2), of a second portion (portion corresponding to 2nd leftmost 5) of the unit cells (all groups of 2, 3, 4), with the second gate pad (2nd leftmost 5) {¶0027};
the source pad (6) forms a common source terminal of the GaN power transistor for all unit cells (all groups of 2, 3, 4) {Fig. 1};
the drain pad (7) forms a common drain terminal of the GaN power transistor for all unit cells (all groups of 2, 3, 4) {Fig. 1};
the first gate pad (leftmost 5) forms a first gate terminal of the GaN power transistor for the first portion (portion corresponding to leftmost 5) of the plurality of unit cells (all groups of 2, 3, 4) {Fig. 1};
the second gate pad (2nd leftmost 5) forms a second gate terminal of the GaN power transistor for the second portion (portion corresponding to 2nd leftmost 5) of the plurality of unit cells (all groups of 2, 3, 4) {Fig. 1}.
Takagi does not teach:
a source metallization layer contacting the source regions, of the plurality of unit cells, with the source pad;
a drain metallization layer contacting the drain regions, of the plurality of unit cells, with the drain pad;
the first and second gate layers are metal.
In an analogous art, Wang teaches in Figs. 3 and 4 and paragraph [0019] a source metallization layer (metallization layer interconnecting Ws and S31-S37) contacting source regions (S31-S37), of a plurality of unit cells (e.g., cells corresponding to S31-S37 and D35-D38), with a source pad (Ws); a drain metallization layer (metallization layer interconnecting WD2 and D35-D38) contacting drain regions (D35-D38), of the plurality of unit cells (e.g., cells corresponding to S31-S37 and D35-D38), with a drain pad (WD2); and first and second gate layers (gate layers interconnecting gate fingers with corresponding gate pads) are metal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takagi’s GaN power transistor based on the teachings of Wang – such that a source metallization layer contacts the source regions, of the plurality of unit cells, with the source pad; a drain metallization layer contacts the drain regions, of the plurality of unit cells, with the drain pad; and the first and second gate layers are metal – so parasitic capacitance can be efficiently reduced. Wang ¶0019. Moreover, all the claimed elements (e.g., source/drain regions, pads, metallization layers) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Wang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Takagi does not teach expressly wherein an output capacitance of the GaN power transistor is N+1 times a capacitance CDS between the common drain terminal and the common source terminal.
In an analogous art, Kinoshita teaches in the second paragraph of column 3 that capacitance is proportional to an area of consideration. Thus, for an instance in which an area of a second portion of the transistor is N times the area of a first portion of the transistor, the total capacitance for the total area (i.e., the sum of the areas for the first and second portions) would be (N+1) times the capacitance of the first portion of the transistor. Alternatively, this may be expressed as: (1) the total capacitance of (N+1) portions of a single capacitor each having a capacitance of CDS is given by the product (N+1) * CDS, (2) the total capacitance of (N+1) same-size capacitors each having a capacitance of CDS and connected in electrical parallel is given by the product (N+1) * CDS, or (3) the total drain-to-source capacitance of (N+1) same-size transistors each having a drain-to-source capacitance of CDS and connected in electrical parallel is given by the product (N+1) * CDS. Applicant discloses this same law of physics in paragraph [0115] of the original specification in relation to the capacitance of same-size transistors connected in electrical parallel by stating that (N+1) same-size transistors connected in electrical parallel have the same drain-to-source capacitance as (N+1) times the drain-to-source capacitance of a single one of the same-size transistors. Regardless of how the physical relationship is expressed, the total capacitance of (N+1) same-size capacitors/(capacitor portions)/transistors connected in electrical parallel is (N+1) times the capacitance of a single one of the same-size capacitors/(capacitor portions)/transistors. Kinoshita’s teachings (e.g., regarding the physics of electrically parallel capacitance) are implicit in the teachings of Takagi and Wang, just as they are in those of Applicant’s paragraph [0115].
As Kinoshita’s teaching applies to the circumstances of claim 1, an output capacitance of Takagi’s GaN power transistor is N+1 times a capacitance CDS between the common drain terminal and the common source terminal because the total capacitance CDS of the (N+1) electrically parallel same-size transistors/(capacitor portions) is (N+1) times the capacitance of a single one of the same-size transistors/(capacitor portions).
Regarding claim 2, Takagi as modified by Wang and Kinoshita teaches the GaN power transistor according to claim 1, and Takagi further teaches wherein a ratio of a first area of the first portion (portion corresponding to leftmost 5) of the unit cells (all groups of 2, 3, 4) to a second area of the second portion (portion corresponding to 2nd leftmost 5) of the unit cells (all groups of 2, 3, 4) is N (implicit).
Regarding claim 17, Takagi as modified by Wang and Kinoshita teaches the GaN power transistor according to claim 1, but Takagi does not teach wherein
the source metallization layer comprises at least one crossing with the drain metallization layer in order to connect the source regions, of the plurality of unit cells, with the source pad; and
the drain metallization layer comprises at least one crossing with the source metallization layer in order to connect the drain regions of the plurality of unit cells with the drain pad.
Wang teaches in Fig. 3 and paragraph [0019] a source metallization layer (metallization layer interconnecting Ws and S31-S37) comprises at least one crossing with a drain metallization layer (metallization layer interconnecting WD2 and D35-D38) in order to connect source regions (S31-S37), of the plurality of unit cells (e.g., cells corresponding to S31-S37 and D35-D38), with a source pad (Ws); and the drain metallization layer (metallization layer interconnecting WD2 and D35-D38) comprises at least one crossing with the source metallization layer (metallization layer interconnecting Ws and S31-S37) in order to connect drain regions (D35-D38) of the plurality of unit cells (e.g., cells corresponding to S31-S37 and D35-D38) with a drain pad (WD2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takagi’s GaN power transistor as modified by Wang and Kinoshita based on the further teachings of Wang, as identified above, so parasitic capacitance can be efficiently reduced. Wang ¶0019. Moreover, all the claimed elements (e.g., source/drain regions, pads, metallization layers) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Wang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 19, Takagi as modified by Wang and Kinoshita teaches the GaN power transistor according to claim 17, and Takagi further teaches wherein the source pad (6) and the drain pad (7) are arranged outside of an active area (area of 2, 3, 4) of the GaN power transistor formed by the plurality of unit cells (all groups of 2, 3, 4) {Fig. 1; ¶0027}.
Regarding claim 20, Takagi as modified by Wang and Kinoshita teaches the GaN power transistor according to claim 19, but Takagi does not teach
wherein the source metallization layer is arranged side by side with the drain metallization layer in order to connect the source regions of the plurality of unit cells with the source pad; and
wherein the drain metallization layer is arranged side by side with the source metallization layer in order to connect the drain regions of the plurality of unit cells with the drain pad.
Wang teaches in Fig. 3 and paragraph [0019]:
wherein the source metallization layer (metallization layer interconnecting Ws and S31-S37) is arranged side by side with the drain metallization layer (metallization layer interconnecting WD2 and D35-D38) in order to connect the source regions (S31-S37) of the plurality of unit cells (e.g., cells corresponding to S31-S37 and D35-D38) with the source pad (Ws); and
wherein the drain metallization layer (metallization layer interconnecting WD2 and D35-D38) is arranged side by side with the source metallization layer (metallization layer interconnecting Ws and S31-S37) in order to connect the drain regions (D35-D38) of the plurality of unit cells (e.g., cells corresponding to S31-S37 and D35-D38) with the drain pad (WD2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takagi’s GaN power transistor as modified by Wang based on the further teachings of Wang, as identified above, so parasitic capacitance can be efficiently reduced. Wang ¶0019. Moreover, all the claimed elements (e.g., source/drain regions, pads, metallization layers) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Wang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 4, 6, 7, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi in view of Wang and Kinoshita as applied to claim 1 above, and further in view of Amirtharajah et al. (Rajeevan Amirtharajah, Jeff Parkhurst; EEC 118 Lecture #2: MOSFET Structure and Basic Operation; 2011).
Regarding claim 4, Takagi as modified by Wang and Kinoshita teaches the GaN power transistor according to claim 1, but Takagi does not teach
wherein an input capacitance N*CGS between the second gate terminal and the source terminal is N times larger than an input capacitance CGS between the first gate terminal and the source terminal; and
wherein an input capacitance N*CGD between the second gate terminal and the drain terminal is N times larger than an input capacitance CGD between the first gate terminal and the drain terminal.
In an analogous art, Amirtharajah teaches on pages 32-34 that both of input capacitances CGS and CGD are proportional to the area of a transistor channel under a gate. Because Takagi’s second transistor channel area under a second gate (e.g., 2nd leftmost gate) is N (e.g., ~1) times the size of Takagi’s first transistor channel area under a first gate (e.g., leftmost gate), it follows from Amirtharajah’s teaching that each of the input capacitances CGS and CGD for Takagi’s second transistor are N times greater than that of Takagi’s first transistor. And because Amirtharajah’s teachings relate to the implicit characteristics of a MOSFET, it follows the above-identified relationship is implicit.
Regarding claim 6, Takagi as modified by Wang and Kinoshita teaches the GaN power transistor according to claim 1, and Takagi further teaches wherein input capacitances of the GaN power transistor are modified during operation by selecting one or both of the first (leftmost 5) and second (2nd leftmost 5) gate terminals {see both First and Second Examiner’s Notes, below}.
First Examiner’s Note: Takagi teaches in Fig. 1 that each of the first gate pad (e.g., leftmost 5) and the second gate pad (e.g., 2nd leftmost gate) are separate terminals. Thus, each is selectable separately or in combination with the other. For instance, Takagi teaches in Fig. 2 a wire connection to one or more of the first gate pad terminals. Moreover, because the claim recites “one” and “both” in the alternative (i.e., disjunctive; Markush Group), only one of the first and second gate terminals need be selectable (though Takagi teaches both are selectable). Furthermore, the input capacitances of the GaN power transistor are implicitly determined in accordance with which of the one or more gates is operational, as taught by Amirtharajah and discussed with respect to claim 4 (which discussion in incorporated here by reference).
Second Examiner’s Note: The recitation “are modified during operation by selecting” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 7, Takagi as modified by Wang, Kinoshita, and Amirtharajah teaches the GaN power transistor according to claim 6, and but Takagi does not expressly teach wherein
a first device capacitance configuration: (N+1)* CGS, (N+1)* CGD, (N+1)*CDS is set by enabling the first and second gate terminals;
a second device capacitance configuration: CGS, CGD, (N+1)* CDS is set by enabling the first gate terminal and disabling the second gate terminal; and
a third device capacitance configuration: N* CGS, N* CGD, (N+1)* CDS is set by disabling the first gate terminal and enabling the second gate terminal.
Kinoshita teaches in the second paragraph of column 3 that capacitance is proportional to an area of consideration. Thus, for an instance in which an area of a second portion of the transistor is N times the area of a first portion of the transistor, the total capacitance for the total area (i.e., the sum of the areas for the first and second portions) would be (N+1) times the capacitance of the first portion of the transistor. Alternatively, this may be expressed as: (1) the total capacitance of (N+1) portions of a single capacitor each having a capacitance of CDS is given by the product (N+1) * CDS, (2) the total capacitance of (N+1) same-size capacitors each having a capacitance of CDS and connected in electrical parallel is given by the product (N+1) * CDS, or (3) the total drain-to-source capacitance of (N+1) same-size transistors each having a drain-to-source capacitance of CDS and connected in electrical parallel is given by the product (N+1) * CDS. Applicant discloses this same law of physics in paragraph [0115] of the original specification in relation to the capacitance of same-size transistors connected in electrical parallel by stating that (N+1) same-size transistors connected in electrical parallel have the same drain-to-source capacitance as (N+1) times the drain-to-source capacitance of a single one of the same-size transistors. Regardless of how the physical relationship is expressed, the total capacitance of (N+1) same-size capacitors/(capacitor portions)/transistors connected in electrical parallel is (N+1) times the capacitance of a single one of the same-size capacitors/(capacitor portions)/transistors. Kinoshita’s teachings (e.g., regarding the physics of electrically parallel capacitance) are implicit in the teachings of Takagi and Wang, just as they are in those of Applicant’s paragraph [0115].
As Kinoshita’s teaching applies to the circumstances of claim 7, the capacitance for CGS/CGD is: (1) CGS/CGD when the first gate corresponding to the first portion is solely enabled, (2) N * (CGS/CGD) when the second gate corresponding to the second portion is solely enabled, and (3) (N+1) * (CGS/CGD) when both the first gate corresponding to the first portion and the second gate corresponding to the second portion are enabled. (N+1) * CDS exists for all three circumstances because Takagi’s drain and source are common to both the first and second portions (e.g., first and second gates), as discussed with respect to claim 5 (which discussion is incorporated here by reference). Kinoshita’s teachings are implicit in the combination taught by Takagi, Wang, Kinoshita, and Amirtharajah.
Regarding claim 21, Takagi as modified by Wang, Kinoshita, and Amirtharajah teaches the GaN power transistor according to claim 6, and but Takagi does not expressly teach wherein by selecting one or both of the first and second gate terminals, the following configuration of device capacitances can be obtained:
VG1 ON, VGN ON → (n+1)*CGS, (n+1)* CGD, (n+1)* CDS,
VG1 ON, VGN OFF → CGS, CGD, (n+1)* CDS, and
VG1 OFF, VGN ON → n*CGS, n* CGD, (n+1)* CDS.
Kinoshita teaches in the second paragraph of column 3 that capacitance is proportional to an area of consideration. Thus, for an instance in which an area of a second portion of the transistor is N times the area of a first portion of the transistor, the total capacitance for the total area (i.e., the sum of the areas for the first and second portions) would be (N+1) times the capacitance of the first portion of the transistor. Alternatively, this may be expressed as: (1) the total capacitance of (N+1) portions of a single capacitor each having a capacitance of CDS is given by the product (N+1) * CDS, (2) the total capacitance of (N+1) same-size capacitors each having a capacitance of CDS and connected in electrical parallel is given by the product (N+1) * CDS, or (3) the total drain-to-source capacitance of (N+1) same-size transistors each having a drain-to-source capacitance of CDS and connected in electrical parallel is given by the product (N+1) * CDS. Applicant discloses this same law of physics in paragraph [0115] of the original specification in relation to the capacitance of same-size transistors connected in electrical parallel by stating that (N+1) same-size transistors connected in electrical parallel have the same drain-to-source capacitance as (N+1) times the drain-to-source capacitance of a single one of the same-size transistors. Regardless of how the physical relationship is expressed, the total capacitance of (N+1) same-size capacitors/(capacitor portions)/transistors connected in electrical parallel is (N+1) times the capacitance of a single one of the same-size capacitors/(capacitor portions)/transistors. Kinoshita’s teachings (e.g., regarding the physics of electrically parallel capacitance) are implicit in the teachings of Takagi and Wang, just as they are in those of Applicant’s paragraph [0115].
As Kinoshita’s teaching applies to the circumstances of claim 21, the capacitance for CGS/CGD is: (1) CGS/CGD when VG1 corresponding to the first portion is solely enabled, (2) N * (CGS/CGD) when VGN corresponding to the second portion is solely enabled, and (3) (N+1) * (CGS/CGD) when both VG1 corresponding to the first portion and VGN corresponding to the second portion are enabled. (N+1) * CDS exists for all three circumstances because Takagi’s drain and source are common to both the first and second portions (e.g., first and second gates). Kinoshita’s teachings are implicit in the combination taught by Takagi, Wang, Kinoshita, and Amirtharajah.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi in view of Wang and Kinoshita as applied to claim 1 above, and further in view of Yang (US20220157979A1).
Regarding claim 15, Takagi as modified by Wang and Kinoshita teaches the GaN power transistor according to claim 1, but Takagi does not teach wherein each unit cell comprises:
a buffer layer;
a barrier layer deposited on the buffer layer; and
a p-type doped GaN layer deposited on top of the barrier layer,
wherein the gate region of the unit cell is formed on top of the p-type doped GaN layer, and the source region and the drain region of the unit cell are formed laterally to the barrier layer.
In an analogous art, Yang teaches in Fig. 1 and paragraph [0026] a unit cell includes a buffer layer (104); a barrier layer (108) deposited on the buffer layer (104); and a p-type doped GaN layer (110) deposited on top of the barrier layer (108), wherein a gate region (120) of a unit cell is formed on top of the p-type doped GaN layer (110), and a source region (122) and a drain region (124) of the unit cell are formed laterally to the barrier layer (108). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takagi’s GaN power transistor as modified by Wang and Kinoshita based on the additional teachings of Yang – such that each unit cell comprises: a buffer layer; a barrier layer deposited on the buffer layer; and a p-type doped GaN layer deposited on top of the barrier layer, wherein the gate region of the unit cell is formed on top of the p-type doped GaN layer, and the source region and the drain region of the unit cell are formed laterally to the barrier layer – so that a portion of the two-dimensional electron gas region … is cut off. Yang ¶0026. Moreover, all the claimed elements (e.g., buffer layer, barrier layer, p-type GaN layer, gate region, source region, drain region) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 16 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi in view of Wang and Kinoshita (US5677866A) as applied to claim 1 above, and further in view of Negoro et al. (US20160049347A1), Ouchi et al. (US20230215922A1), and Yeh et al. (US20180151751A1).
Regarding claim 16, Takagi as modified by Wang and Kinoshita teaches the GaN power transistor according to claim 1, but Takagi does not teach wherein each unit cell comprises:
a buffer layer;
a barrier layer deposited on the buffer layer; and
a passivation layer deposited on top of the barrier layer,
wherein the gate region of the unit cell is formed on top of the passivation layer, and the source region and the drain region of the unit cell are formed laterally to the barrier layer.
In an analogous art, Negoro teaches in Fig. 1 and paragraph [0131] a unit cell includes a buffer layer (102); a barrier layer (104) deposited on the buffer layer (102); and a passivation layer (109, silicon nitride) deposited on top of the barrier layer (104), and a source region (105) and a drain region (106) of the unit cell {Fig. 1} are formed laterally to the barrier layer (104). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takagi’s GaN power transistor as modified by Wang and Kinoshita based on the teachings of Negoro – such that each unit cell comprises: a buffer layer; a barrier layer deposited on the buffer layer; and a passivation layer deposited on top of the barrier layer – so a semiconductor device having a smaller amount of leakage current can be obtained. Negoro ¶0058. Moreover, all the claimed elements (e.g., buffer layer, barrier layer, passivation layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Negoro) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. See, e.g., Ouchi ¶0007 for teaching that a layer of silicon nitride is a passivation layer.
In an analogous art, Yeh teaches in Fig. 3 and paragraph [0029] a gate region (222) of a unit cell is formed on top of a passivation layer (212/214). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takagi’s GaN power transistor as modified by Wang, Kinoshita, Negoro, and Ouchi based on the teachings of Yeh – such that the gate region of the unit cell is formed on top of the passivation layer – because all the claimed elements (e.g., buffer layer, barrier layer, passivation layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yeh) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 22, Takagi as modified by Wang, Kinoshita, Negoro, Ouchi, and Yeh teaches the GaN power transistor according to claim 16, but Takagi does not teach wherein the buffer layer comprises a GaN layer or an Aluminum Gallium Nitride (AlGaN) layer, and the barrier layer comprises an AlGaN layer.
Negoro teaches in Fig. 1 and paragraph [0122, 0129] a buffer layer (102) comprises a GaN layer or an Aluminum Gallium Nitride (AlGaN) layer, and a barrier layer (104) comprises an AlGaN layer. The motivation for this modification is identified with respect to intermediate claim 16. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi in view of Wang and Kinoshita as applied to claim 17 above, and further in view of Takemae et al. (US20120091986A1).
Regarding claim 18, Takagi as modified by Wang and Kinoshita teaches the GaN power transistor according to claim 17, but Takagi does not teach wherein the source pad and the drain pad are arranged on top of an active area of the GaN power transistor formed by the plurality of unit cells.
In an analogous art, Takemae teaches in Figs. 1A-1D and paragraphs [0033], [0035], [0038], and [0043] a source pad (25; Fig. 1D) and a drain pad (15; Fig. 1B) are arranged on top of an active area (3) of a GaN power transistor (3) formed by a plurality of unit cells (8, 9, 10; ¶0035). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takagi’s GaN power transistor as modified by Wang and Kinoshita based on the teachings of Takemae – such that the source pad and the drain pad are arranged on top of an active area of the GaN power transistor formed by the plurality of unit cells – to reduce the parasitic inductance and resistance, thereby improving the conversion efficiency. Takemae ¶0047. Moreover, all the claimed elements (e.g., source pad, drain pad, active area, cells) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Takemae) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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