DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawing Objections
Examiner withdraws the drawing objection based upon the submission of new figures and corresponding specification.
Claim Rejections - 35 USC § 112(b)
Examiner withdraws the 35 USC § 112(b) based upon the amendments to claim 13.
Claim Rejections - 35 USC § 112(d)
Examiner withdraws the 35 USC § 112(d) rejection based upon the amendments to claim 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kiani, Ahmed, “Analysis of metal oxide thin film transistors with high-k dielectrics and source/drain contact metals”, A Dissertation submitted to the University of Cambridge for the Degree of Doctor of Philosophy, June 2013 (“Kiani”), in view of Kato et al. (US 2011/0114941 A1) (“Kato”), in view of Murray et al. (US 2022/0246767 A1) (“Murray”).
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Regarding claim 13, Kiani teaches at least in figure 5.1 above:
a substrate (n-Si) serving as a gate electrode (N-Si serves as the claimed gate electrode);
a gate insulating film (Gate dielectric) formed on the substrate (n-Si);
Kiani does not teach:
a metal layer formed on the gate insulating film;
a metal oxide layer formed on the metal layer and covering an entirety of a surface of the metal layer;
a metal oxide semiconductor layer formed so as to cover an entirety of a surface of the metal oxide layer; and
a source/drain electrode formed on the metal oxide semiconductor layer,
wherein an oxygen depletion layer disposed in an area of the metal oxide semiconductor layer adjacent to the metal oxide layer.
Kato teaches at least in figure 1B:
a metal layer (405) formed on the gate insulating film (404);
a metal oxide layer (406) formed on the metal layer (405) and covering an entirety of a surface of the metal layer (406 covers the entirety of 405);
a metal oxide semiconductor layer (407) formed so as to cover a surface of the metal oxide layer (406); and
a source/drain electrode (408a-b) formed on the metal oxide semiconductor layer (407),
wherein an oxygen depletion layer is disposed in an area of the metal oxide semiconductor layer adjacent to the metal oxide layer (Per ¶¶ 0067-68, oxygen depletion layer is result of having the metal oxide semiconductor layer in contact with the metal oxide layer, and the oxygen migrating from the oxide semiconductor layer to the metal oxide layer under a temperature of 100 to 1000C. It is understood that this migration of oxygen can happen at any time the temperature of the device is between the above ranges. In ¶ 0103 Kato teaches a heat treatment after forming oxide insulating film 409. This heat treatment is performed at 200 to 400C. Therefore, based upon Applicant’s disclosure the oxygen in the oxide semiconductor layer will migrate to the metal oxide layer and create an oxygen depletion layer. Therefore, the prior art obviously teaches the oxygen depletion layer as it performs a heat treatment above the required temperature ranges necessary to form the oxygen depletion layer.).
It would have been obvious to one of ordinary skill in the art to combine Kato with Kiani as this would allow one to create a nonvolatile TFT memory device. Kato ¶ 0004.
The prior art does not teach:
a metal oxide semiconductor layer formed so as to cover an entirety of a surface of the metal oxide layer.
This is because the prior art shows the metal oxide semiconductor layer as mainly being formed between the source drain contacts.
Murray teaches at least in figure 24B:
a metal oxide semiconductor layer (20) formed so as to cover an entirety of a surface of the metal oxide layer (10).
It would have been obvious that the metal oxide semiconductor layer could be equal in length to the metal oxide layer. This is because it is an obvious variant and design choice on how one wants to form the oxide semiconductor layer and its integration with the source and drain.
Regarding claim 14, Kiani teaches at least in figure 5.1 above:
wherein the metal oxide semiconductor layer is obtained by crystallizing the amorphous metal oxide semiconductor layer under the heat-treatment (this is a product-by-process limitation. Kato teaches this limitation in ¶ 0079).
Allowable Subject Matter
Claims 1-6 are allowed.
The following is an examiner’s statement of reasons for allowance: See below.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Regarding claim 1, Kiani teaches at least in figure 5.1 above:
a first step of forming a gate insulating film (Gate dielectric) on a substrate (n-Si),
wherein the substrate (n-Si) serves as a gate electrode (n-Si acts as ;
forming an metal oxide semiconductor layer (IGZO)
a fifth step of depositing a source/drain electrode (source/drain) layer on the metal oxide semiconductor layer (a-IGZO)
Kiani does not teach:
a second step of forming a metal layer on the gate insulating film;
a third step of forming an amorphous metal oxide semiconductor layer so as to cover an entirety of a surface of the metal layer to obtain a structure including the metal layer and the amorphous metal oxide semiconductor layer formed thereon;
a fourth step of heat-treating the structure; and
a fifth step of depositing a source/drain electrode layer on the heat-treated structure,
wherein during the fourth step,
a metal oxide layer is formed between the amorphous metal oxide semiconductor layer and the metal layer,
the amorphous metal oxide semiconductor layer is crystallized, and
an oxygen depletion area is formed in an area of the amorphous metal semiconductor layer adjacent to the metal layer or the metal oxide layer.
Kato teaches
a second step of forming a metal layer (405; ¶ 0064, where 405 can be AL) on the gate insulating film (404);
a third step of forming an amorphous metal oxide semiconductor layer (407) so as to cover an entirety of a surface of the metal layer (405) to obtain a structure (405/407) including the metal layer (405) and the amorphous metal oxide semiconductor layer (407) formed thereon;
a fourth step of heat-treating the structure (¶ 0079); and
a fifth step of depositing a source/drain electrode layer (408a-b) on the heat-treated structure (405/407),
wherein during the fourth step (detailed below),
the amorphous metal oxide semiconductor layer is crystallized (¶ 0079), and
an oxygen depletion area is formed in an area of the amorphous metal semiconductor layer adjacent to the metal layer or the metal oxide layer (¶ 0088).
The prior art does not teach:
wherein during the fourth step,
a metal oxide layer is formed between the amorphous metal oxide semiconductor layer and the metal layer.
This is because the prior art does not teach the metal layer is oxidized during the fourth step.
Response to Arguments
Applicant's arguments filed June 1, 2026 have been fully considered but they are not persuasive.
Applicant asserts the oxygen depletion layer is required by the claims to be formed within the metal oxide semiconductor layer. This is incorrect. The claims require “an oxygen depletion layer is disposed in an area of the metal oxide semiconductor layer adjacent to the metal oxide layer.” (emphasis added). The limitation “in an area of” does not require it to be formed in a layer, or somewhat near. Further, the claims do not require a compositional change of the metal oxide semiconductor layer. Additionally, Applicant argues the metal oxide layer does not cover an entirety of the surface of the metal layer. The prior art teaches the metal oxide layer 406 does cover the entirety of the surface of the metal layer 405.
In response to Applicant’s argument that Examiner improperly uses Applicant’s disclosure against them, it is Examiner’s position that Examiner is simply uses Applicant’s disclosure to intrinsically understand the meaning of the claimed terms.
For all the above reasons, Applicant’s arguments are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VINCENT WALL/Primary Examiner, Art Unit 2898
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