DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-8, 10-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US 20190172838 A1; hereinafter Jo) in view of Chandrashekar et al. (US 20130302980 A1; hereinafter Chandrashekar), and further in view of Fukumaki et al. (US 20230064038 A1; hereinafter Fukumaki).
Regarding claim 1, FIG. 5A of Jo teaches a non-volatile memory device (e.g. FIG. 5A) comprising: a substrate (PS ¶ [0025]) including a first area (area of PS below VS) and a second area (area of PS below TPLG and PPLG); a first mold structure (ST) on the substrate (PS ¶ [0049]), the mold structure (ST) including a plurality of gate electrodes (CGE) and a plurality of mold insulating films (ILD) that are alternately stacked on top of each other and stacked in a stepwise manner (¶ [0050]); an interlayer insulating film (150) covering the mold structure (ST ¶ [0071]); a channel structure (VS) on the first area of the substrate (area of PS below VS ¶ [0046]), the channel structure (VS) extending through the first mold structure (ST) and connected to the plurality of gate electrodes (CGE ¶ [0053],[0061]); and a through-contact (PPLG) on the second area of the substrate (area of PS below TPLG and PPLG) and extending through the first interlayer insulating film (150 ¶ [0075]).
Jo does not teach wherein the through-contact includes a first portion in a first trench and a second portion in a second trench, the second trench being on the first trench, the first portion includes, a liner film along a sidewall and a bottom surface of the first trench, and a filling film on the liner film, the filling film is a multi-grain conductive material, and the second portion is a single grain conductive material.
FIG. 4B of Chandrashekar teaches a through-contact (403, 404, 461, 463) extending through a substrate (not labelled ¶ [0084],[0042], substrate may include dielectric material deposited thereon); wherein the through-contact (403, 404, 461, 463) includes a first portion (403, 461, 463) in a first trench (first trench occupied by 403, 461, 463 according to 470) and a second portion (404) in a second trench (second trench formed according to 462), the second trench being on the first trench, the first portion (403, 461, 463) includes, a liner film (461, 463) along a sidewall and a bottom surface of the first trench (sidewall of first trench occupied by 403, 461, 463 according to 470), and a filling film (403) on the liner film (461, 463), the filling film (403) is a multi-grain conductive material (see FIG. 4B), and the second portion (404) is a single grain conductive material (¶ [0092]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device taught by Jo with the through-contact taught by Chandrashekar for the purpose of improving electrical characteristics of the through-contact (¶ [0086]).
Jo as modified does not teach a second mold structure on the first mold structure, the second mold structure including the plurality of gate electrodes and the plurality of mold insulating films that are alternately stacked on top of each other and stacked in a stepwise manner; a second interlayer insulating film on the first interlayer insulating film, the second interlayer insulating film covering the second mold structure; the channel structure extending through the second mold structure; the through-contact extending through the second interlayer insulating film; the first trench being in the first interlayer insulating film and the second trench being in the second interlayer insulating film.
FIGS. 1-4 of Fukumaki teaches a non-volatile memory device (MR ¶ [0023]-[0024]) comprising: a substrate (10) including a first area (1) and a second area (2 ¶ [0025]-[0026]); a first mold structure (100aL) on the substrate (10), and a second mold structure (100aU) on the first mold structure (100aL), the first mold structure (100aL) and the second mold structure (100aU) each including a plurality of gate electrodes (70) and a plurality of mold insulating films (72) that are alternately stacked on top of each other and stacked in a stepwise manner (¶ [0027],[0034]-[0035]); a first interlayer insulating film (42 on 100aL) covering the first mold structure (100aL ¶ [0044]); a second interlayer insulating film (42 on 100aU) on the first interlayer insulating film (42 on 100aL), the second interlayer insulating film (42 on 100aU) covering the second mold structure (100aU ¶ [0044]); a channel structure (CL1) on the first area of the substrate (1 ¶ [0047]), the channel structure (CL1) extending through the first mold structure (100aL) and the second mold structure (100aU) and connected to the plurality of gate electrodes (70, see FIG. 4).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device taught by Jo with the first and second mold structures taught by Fukumaki for the purpose of expanding the memory storage of the device.
Thus, Jo in view of Chandrashekar and Fukumaki teaches the through-contact (PPLG of Jo; 403, 404, 461, 463 of Chandrashekar) extending through the first interlayer insulating film (42 on 100aL of Fukumaki) and the second interlayer insulating film (42 on 100aU of Fukumaki), the first trench (first trench occupied by 403, 461, 463 according to 470 of Chandrashekar) being in the first interlayer insulating film (42 on 100aL of Fukumaki) and the second trench (second trench formed according to 462 of Chandrashekar) being in the second interlayer insulating film (42 on 100aU of Fukumaki). The shape and extent of the through-contact being similar to 63 of Fukumaki.
Regarding claim 2, Jo as modified teaches the non-volatile memory device of claim 1, and FIG. 4B of Chandrashekar further teaches wherein the first trench (first trench occupied by 403, 461, 463 according to 470) and the second trench (second trench formed according to 462) are positionally offset relative to each other (offset in a height-wise direction, i.e. the first trench is not at the same height as the second trench) when viewed in plan view. The Examiner notes that FIG. 4B of Chandrashekar shows the above recited limitations in a cross-sectional view. Thus, the above recited limitations are also taught in a plan view.
Regarding claim 4, Jo as modified teaches the non-volatile memory device of claim 1, and FIG. 4B of Chandrashekar further teaches wherein the filling film (403) includes a first filling portion (first portion of 403) on one sidewall of the first trench and a second filling portion (second portion of 403 opposite to first portion of 403) on an opposite sidewall of the first trench, and a boundary line (boundary line between first portion and second portion of 403) is at a second boundary (boundary between first portion and second portion of 403) between the first area filling portion (first portion of 403) and the second area filling portion (second portion of 403, see Examiner annotated FIG. 4B below).
PNG
media_image1.png
706
889
media_image1.png
Greyscale
Regarding claim 5, Jo as modified teaches the non-volatile memory device of claim 1, and FIG. 4B of Chandrashekar further teaches wherein the liner film (461, 463) includes a first sub-liner film (463), and a second sub-liner film (461) on the first sub-liner film (463), the first sub-liner film (463) includes at least one of TiN, WN, WCN, or TSN (e.g. TiN or WN ¶ [0086]).
Jo as modified does not teach the second sub-liner film includes boron (B).
FIG. 13B of Chandrashekar teaches a method of forming the filling film (e.g. “tungsten fill” ¶ [0124]) comprising forming a first sub-liner film (e.g. tungsten film), and a second sub-liner film (e.g. boron film) on the first sub-liner film (tungsten film ¶ [0124] “conformal boron deposition may occur prior to or after initial tungsten deposition in the feature”); wherein the second sub-liner film (boron film) is partially converted to tungsten, leaving a portion of the second sub-liner film (boron film ¶ [0126] “boron is partially converted to tungsten… leaving a boron-tungsten bilayer”) and subsequently forming the filling film (¶ [0127] “feature fill”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device taught by Jo with the method of forming the tungsten fill taught by Chandrashekar for the purpose of tailoring the tungsten feature fill (¶ [0127]).
Regarding claim 6, Jo as modified teaches the non-volatile memory device of claim 1, and FIG. 4 of Chandrashekar further teaches wherein the second portion (404) is a single film (¶ [0092]).
Regarding claim 7, Jo as modified teaches the non-volatile memory device of claim 1.
Jo as modified does not teach wherein the channel structure includes a first channel and a second channel on the first channel.
FIGS. 1-4 of Fukumaki teach a non-volatile memory device (e.g. FIG. 3) comprising: a substrate (10 ¶ [0021]); a mold structure (100) on the substrate (10 ¶ [0025]), the mold structure (100) including a plurality of gate electrodes (70) and a plurality of mold insulating films (72) that are alternately stacked on top of each other and stacked in a stepwise manner (¶ [0030]); an interlayer insulating film (42) covering the mold structure (100 ¶ [0044]); a channel structure (CL1) extending through the mold structure (100) and connected to the plurality of gate electrodes (70 ¶ [0025]); and wherein the channel structure (CL1) includes a first channel (LCL1 ¶ [0035]) and a second channel (UCL1) on the first channel (LCL1 ¶ [0036]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the non-volatile memory device taught by Jo with the channel structure taught by Fukumaki for the purpose of increasing the memory capacity of the device.
Regarding claim 8, Jo as modified teaches the non-volatile memory device of claim 7.
Jo as modified does not explicitly teach wherein the first channel overlaps the first trench in a direction parallel to a top surface of the substrate, and the second channel overlaps the second trench in the direction parallel to the top surface of the substrate.
However, Jo in view of Chandrashekar and Fukumaki teaches a non-volatile memory device (e.g. FIG. 5A of Jo and FIG. 4 of Fukumaki) comprising a lower group (100aL of Fukumaki, first instance of ST according to Jo) and an upper group (100aU of Fukumaki ¶ [0034], second instance of ST according to Jo) of mold structures (Fukumaki ¶ [0035]-[0036], Jo ¶ [0049]), a lower channel structure (LCL1 of Fukumaki ¶ [0035], first instance of VS according to Jo) and an upper channel structure (UCL1 of Fukumaki ¶ [0036], second instance of VS according to Jo) on the lower channel structure. Jo in view of Fukumaki teaches a first instance of the mold structure ST and a second instance of the mold structure ST on the first instance of ST, a first instance of the channel structures VS and a second instance of the channel structures VS on the first instance of VS as outlined above. In addition, Jo teaches a through-contact PPLG extending through an interlayer dielectric covering the mold structure, wherein the channel structure VS overlaps the through-contact PPLG in a direction parallel to a top surface of the substrate. An additional second mold structure ST and plurality of second channel structures VS result from modifying Jo with Fukumaki. The through-contact PPLG of Jo is either extended or a secondary through-contact PPLG is added on the first through-contact PPLG.
In either case, modifying the through-contact PPLG of Jo with the through-contact 401 of Chandrashekar results in the first channel structures VS of Jo in view of Fukumaki overlaping the first trench (first trench occupied by 403, 461, 463 according to 470 of Chandrashekar) in a direction parallel to a top surface of the substrate (10 of Jo) and the second channel structures VS of Jo in view of Fukumaki overlapping the second trench (second trench formed according to 462 of Chandrashekar) in the direction parallel to the top surface of the substrate (10 of Jo).
Regarding claim 10, FIG. 5A of Jo teaches a non-volatile memory device (e.g. FIG. 5A) comprising: a substrate (PS ¶ [0025]) including a first area (area of PS below VS) and a second area (area of PS below TPLG and PPLG); a mold structure (ST) on the substrate (PS ¶ [0049]), the mold structure (ST) including a plurality of gate electrodes (CGE) and a plurality of mold insulating films (ILD) that are alternately stacked on top of each other and stacked in a stepwise manner (¶ [0050]); an interlayer insulating film (150) covering the mold structure (ST ¶ [0071]); a channel structure (VS) on the first area of the substrate (area of PS below VS ¶ [0046]), the channel structure (VS) extending through the mold structure (ST) and connected to the plurality of gate electrodes (CGE ¶ [0053],[0061]); and a through-contact (PPLG) on the second area of the substrate (area of PS below TPLG and PPLG) and extending through the interlayer insulating film (150 ¶ [0075]).
Jo does not teach wherein the through-contact includes, a first portion in a first trench and being multiple layers; and a second portion in a second trench and being a single layer, the second trench is on the first trench, the first portion includes, a liner film along a sidewall and a bottom surface of the first trench, and a filling film on the liner film, the filling film includes a first filling portion on one sidewall of the first trench, and a second filling portion on an opposite sidewall of the first trench, and a boundary line is at a boundary between the first filling portion and the second filing portion.
FIG. 4B of Chandrashekar teaches a through-contact (403, 404, 461, 463) extending through a substrate (not labelled ¶ [0084],[0042], substrate may include dielectric material deposited thereon); wherein the through-contact (403, 404, 461, 463) includes a first portion (403, 461, 463) in a first trench and being multiple layers (first trench occupied by 403, 461, 463 according to 470) and a second portion (404) in a second trench (second trench formed according to 462) and being a single layer (404), the second trench is on the first trench, the first portion (403, 461, 463) includes, a liner film (461, 463) along a sidewall and a bottom surface of the first trench (sidewall of first trench occupied by 403, 461, 463 according to 470), and a filling film (403) on the liner film (461, 463), the filling film (403) includes a first filling portion (first portion of 403) on one sidewall of the first trench (one sidewall of first trench occupied by 403, 461, 463 according to 470), and a second filling portion (second portion of 403) on an opposite sidewall of the first trench (another sidewall of first trench occupied by 403, 461, 463 according to 470), a boundary line (boundary line between first portion and second portion of 403) is at a first boundary (boundary between first portion and second portion of 403) between the first filling portion (first portion of 403) and the second filling portion (second portion of 403, see Examiner annotated FIG. 4B below).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device taught by Jo with the through-contact taught by Chandrashekar for the purpose of improving electrical characteristics of the through-contact (¶ [0086]).
PNG
media_image1.png
706
889
media_image1.png
Greyscale
Jo as modified does not teach a second mold structure on the first mold structure, the second mold structure including the plurality of gate electrodes and the plurality of mold insulating films that are alternately stacked on top of each other and stacked in a stepwise manner; a second interlayer insulating film on the first interlayer insulating film, the second interlayer insulating film covering the second mold structure; the channel structure extending through the second mold structure; the through-contact extending through the second interlayer insulating film; the first trench being in the first interlayer insulating film and the second trench being in the second interlayer insulating film.
FIGS. 1-4 of Fukumaki teaches a non-volatile memory device (MR ¶ [0023]-[0024]) comprising: a substrate (10) including a first area (1) and a second area (2 ¶ [0025]-[0026]); a first mold structure (100aL) on the substrate (10), and a second mold structure (100aU) on the first mold structure (100aL), the first mold structure (100aL) and the second mold structure (100aU) each including a plurality of gate electrodes (70) and a plurality of mold insulating films (72) that are alternately stacked on top of each other and stacked in a stepwise manner (¶ [0027],[0034]-[0035]); a first interlayer insulating film (42 on 100aL) covering the first mold structure (100aL ¶ [0044]); a second interlayer insulating film (42 on 100aU) on the first interlayer insulating film (42 on 100aL), the second interlayer insulating film (42 on 100aU) covering the second mold structure (100aU ¶ [0044]); a channel structure (CL1) on the first area of the substrate (1 ¶ [0047]), the channel structure (CL1) extending through the first mold structure (100aL) and the second mold structure (100aU) and connected to the plurality of gate electrodes (70, see FIG. 4).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device taught by Jo with the first and second mold structures taught by Fukumaki for the purpose of expanding the memory storage of the device.
Thus, Jo in view of Chandrashekar and Fukumaki teaches the through-contact (PPLG of Jo; 403, 404, 461, 463 of Chandrashekar) extending through the first interlayer insulating film (42 on 100aL of Fukumaki) and the second interlayer insulating film (42 on 100aU of Fukumaki), the first trench (first trench occupied by 403, 461, 463 according to 470 of Chandrashekar) being in the first interlayer insulating film (42 on 100aL of Fukumaki) and the second trench (second trench formed according to 462 of Chandrashekar) being in the second interlayer insulating film (42 on 100aU of Fukumaki). The shape and extent of the through-contact being similar to 63 of Fukumaki.
Regarding claim 11, Jo as modified teaches the non-volatile memory device of claim 10, and Chandrashekar further teaches wherein the filling film (403) is a multi-grain conductive material (see FIG. 4B), wherein the second portion (404) is a single grain conductive material (¶ [0092]).
Regarding claim 12, Jo as modified teaches the non-volatile memory device of claim 10, and FIG. 4B of Chandrashekar further teaches wherein the first trench (first trench occupied by 403, 461, 463 according to 470) and the second trench (second trench formed according to 462) are positionally offset relative to each other (offset in a height-wise direction, i.e. the first trench is not at the same height as the second trench).
Regarding claim 14, Jo as modified teaches the non-volatile memory device of claim 10, and FIG. 4B of Chandrashekar further teaches wherein the liner film (461, 463) includes a first sub-liner film (463), and a second sub-liner film (461) on the first sub-liner film (463), the first sub-liner film (463) includes at least one of TiN, WN, WCN, or TSN (e.g. TiN or WN ¶ [0086]),
Jo as modified does not teach the second sub-liner film includes boron (B).
FIG. 13B of Chandrashekar teaches a method of forming the filling film (e.g. “tungsten fill” ¶ [0124]) comprising forming a first sub-liner film (e.g. tungsten film), and a second sub-liner film (e.g. boron film) on the first sub-liner film (tungsten film ¶ [0124] “conformal boron deposition may occur prior to or after initial tungsten deposition in the feature”); wherein the second sub-liner film (boron film) is partially converted to tungsten, leaving a portion of the second sub-liner film (boron film ¶ [0126] “boron is partially converted to tungsten… leaving a boron-tungsten bilayer”) and subsequently forming the filling film (¶ [0127] “feature fill”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device taught by Jo with the method of forming the tungsten fill taught by Chandrashekar for the purpose of tailoring the tungsten feature fill (¶ [0127]).
Regarding claim 15, Jo as modified teaches the non-volatile memory device of claim 10.
Jo as modified does not teach wherein the channel structure includes a first channel and a second channel on the first channel.
FIGS. 1-4 of Fukumaki teach a non-volatile memory device (e.g. FIG. 3) comprising: a substrate (10 ¶ [0021]); a mold structure (100) on the substrate (10 ¶ [0025]), the mold structure (100) including a plurality of gate electrodes (70) and a plurality of mold insulating films (72) that are alternately stacked on top of each other and stacked in a stepwise manner (¶ [0030]); an interlayer insulating film (42) covering the mold structure (100 ¶ [0044]); a channel structure (CL1) extending through the mold structure (100) and connected to the plurality of gate electrodes (70 ¶ [0025]); and wherein the channel structure (CL1) includes a first channel (LCL1 ¶ [0035]) and a second channel (UCL1) on the first channel (LCL1 ¶ [0036]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the non-volatile memory device taught by Jo with the channel structure taught by Fukumaki for the purpose of increasing the memory capacity of the device.
Regarding claim 16, Jo as modified teaches the non-volatile memory device of claim 15.
Jo as modified does not explicitly teach wherein the first channel overlaps the first trench in a direction parallel to a top surface of the substrate, and the second channel overlaps the second trench in the direction parallel to the top surface of the substrate.
However, Jo in view of Chandrashekar and Fukumaki teaches a non-volatile memory device (e.g. FIG. 5A of Jo and FIG. 4 of Fukumaki) comprising a lower group (100aL of Fukumaki, first instance of ST according to Jo) and an upper group (100aU of Fukumaki ¶ [0034], second instance of ST according to Jo) of mold structures (Fukumaki ¶ [0035]-[0036], Jo ¶ [0049]), a lower channel structure (LCL1 of Fukumaki ¶ [0035], first instance of VS according to Jo) and an upper channel structure (UCL1 of Fukumaki ¶ [0036], second instance of VS according to Jo) on the lower channel structure. Jo in view of Fukumaki teaches a first instance of the mold structure ST and a second instance of the mold structure ST on the first instance of ST, a first instance of the channel structures VS and a second instance of the channel structures VS on the first instance of VS as outlined above. In addition, Jo teaches a through-contact PPLG extending through an interlayer dielectric covering the mold structure, wherein the channel structure VS overlaps the through-contact PPLG in a direction parallel to a top surface of the substrate. An additional second mold structure ST and plurality of second channel structures VS result from modifying Jo with Fukumaki. The through-contact PPLG of Jo is either extended or a secondary through-contact PPLG is added on the first through-contact PPLG.
In either case, modifying the through-contact PPLG of Jo with the through-contact 401 of Chandrashekar results in the first channel structures VS of Jo in view of Fukumaki overlapping the first trench (first trench occupied by 403, 461, 463 according to 470 of Chandrashekar) in a direction parallel to a top surface of the substrate (10 of Jo) and the second channel structures VS of Jo in view of Fukumaki overlapping the second trench (second trench formed according to 462 of Chandrashekar) in the direction parallel to the top surface of the substrate (10 of Jo).
Claims 3, 9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jo in view of Chandrashekar and Fukumaki, and further in view of Han et al. (US 20150137259 A1; hereinafter Han).
Regarding claim 3, Jo as modified teaches the non-volatile memory device of claim 1.
Jo as modified does not teach wherein a first width of the first trench gradually increases and then decreases as the first trench extends away from the substrate, and a second width of the second trench gradually increases and then decreases as the second trench extends away from the substrate.
FIGS. 1-2 of Han teach a through-contact (130) extending through an interlayer insulating film (120) on a substrate (101 ¶ [0038]), the through-contact (130) comprising a first portion (132) in a first trench (trench occupied by 132) and a second portion (134) in a second trench (trench occupied by 134 ¶ [0038]), the second trench (trench occupied by 134) being on the first trench (trench occupied by 132, see FIG. 1); and wherein a first width of the first trench (width of trench occupied by 132) gradually increases (W2 to W3) and then decreases (W3 to W1) as the first trench (trench occupied by 132) extends away from the substrate (101 ¶ [0046]), and a second width of the second trench (width of trench occupied by 134) gradually increases (tip L to width at D2) and then decreases (width at D2 to width of upper surface opposite to tip L) as the second trench (trench occupied by 134) extends away from the substrate (101 ¶ [0047]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the non-volatile memory device taught by Jo with the through-contact taught by Han for the purpose of preventing formation of a void or seam in the bowing region (¶ [0068]), reducing a defect rate, and thus, reducing connection resistivity and improving reliability (¶ [0139]).
Regarding claim 9, Jo as modified teaches the non-volatile memory device of claim 1.
Jo as modified does not teach wherein the through-contact includes a tip portion at a boundary between the first portion and the second portion, and the tip portion is convex toward the substrate.
FIGS. 1-2 of Han teach a through-contact (130) extending through an interlayer insulating film (120) on a substrate (101 ¶ [0038]), the through-contact (130) comprising a first portion (132) in a first trench (trench occupied by 132) and a second portion (134) in a second trench (trench occupied by 134 ¶ [0038]), the second trench (trench occupied by 134) being on the first trench (trench occupied by 132, see FIG. 1); and wherein the through-contact (130) includes a tip portion (tip L) at a boundary between the first portion (132) and the second portion (134), and the tip portion (tip L) is convex toward the substrate (101 ¶ [0047]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the non-volatile memory device taught by Jo with the through-contact taught by Han for the purpose of preventing formation of a void or seam in the bowing region (¶ [0068]), reducing a defect rate, and thus, reducing connection resistivity and improving reliability (¶ [0139]).
Regarding claim 13, Jo as modified teaches the non-volatile memory device of claim 10.
Jo as modified does not teach wherein a first width of the first trench gradually increases and then decreases as the first trench extends away from the substrate, and a second width of the second trench gradually increases and then decreases as the second trench extends away from the substrate.
FIGS. 1-2 of Han teach a through-contact (130) extending through an interlayer insulating film (120) on a substrate (101 ¶ [0038]), the through-contact (130) comprising a first portion (132) in a first trench (trench occupied by 132) and a second portion (134) in a second trench (trench occupied by 134 ¶ [0038]), the second trench (trench occupied by 134) being on the first trench (trench occupied by 132, see FIG. 1); and wherein a first width of the first trench (width of trench occupied by 132) gradually increases (W2 to W3) and then decreases (W3 to W1) as the first trench (trench occupied by 132) extends away from the substrate (101 ¶ [0046]), and a second width of the second trench (width of trench occupied by 134) gradually increases (tip L to width at D2) and then decreases (width at D2 to width of upper surface opposite to tip L) as the second trench (trench occupied by 134) extends away from the substrate (101 ¶ [0047]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the non-volatile memory device taught by Jo with the through-contact taught by Han for the purpose of preventing formation of a void or seam in the bowing region (¶ [0068]), reducing a defect rate, and thus, reducing connection resistivity and improving reliability (¶ [0139]).
Allowable Subject Matter
Claims 17 and 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 17 recites a method for manufacturing a non-volatile memory device, the method comprising: providing a substrate including a first area and a second area; forming a mold structure on the substrate, the mold structure including a plurality of gate electrodes and a plurality of mold insulating films that are stacked in a stepwise manner and are alternately stacked on top of each other; forming an interlayer insulating film to cover the mold structure; forming a channel structure on the first area of the substrate to extend through the mold structure and to be connected to the plurality of gate electrodes; forming a trench on the second area of the substate substrate to extend through the interlayer insulating film, the trench including a first trench and a second trench disposed on the first trench; forming a pre-liner film along a sidewall and a trench bottom surface of the trench; forming an inhibiting layer on a second portion of the pre-liner film, which is disposed on a second sidewall of the second trench, such that the inhibiting layer is not formed on a first portion of the pre-liner film disposed on a first sidewall of the first trench; and forming a through-contact in the trench, wherein the through-contact includes a first portion disposed in the first trench and a second portion disposed in the second trench, wherein the first portion includes, includes a liner film disposed along the sidewall and a first bottom surface of the first trench; trench, and a filling film disposed on the liner film, wherein the filling film is made of a multi-grain conductive material, wherein the second portion is made of a single grain conductive material. material, and wherein the method further comprises forming the filling film in the first trench, and removing the inhibiting layer after forming the filling film.
FIGS. 5A, 16-23 of Jo teach a method for manufacturing a non-volatile memory device (e.g. FIGS. 5A, 16-23), the method comprising: providing a substrate (PS ¶ [0025]) including a first area (area of PS below VS) and a second area (area of PS below TPLG and PPLG); forming a mold structure (ST) on the substrate (PS ¶ [0049]), the mold structure (ST) including a plurality of gate electrodes (CGE) and a plurality of mold insulating films (ILD) and are alternately stacked on top of each other and stacked in a stepwise manner (¶ [0050]); forming an interlayer insulating film (150) covering the mold structure (ST ¶ [0071]); forming a channel structure (VS) on the first area of the substrate (area of PS below VS ¶ [0046]) to extend through the mold structure (ST) and to be connected to the plurality of gate electrodes (CGE ¶ [0053],[0061]); and forming a trench (CH2) on the second area of the substrate (area of PS below TPLG and PPLG) to extend through the interlayer insulating film (150 ¶ [0075]).
FIG. 4B of Chandrashekar teaches forming a trench (401) including a first trench (first trench occupied by 403, 461, 463 according to 470) and a second trench (second trench formed according to 462) disposed on the first trench (first trench occupied by 403, 461, 463 according to 470); and forming a through-contact (403, 404, 461, 463) in the trench (401), wherein the through-contact (403, 404, 461, 463) includes a first portion (403, 461, 463) disposed in the first trench (first trench occupied by 403, 461, 463 according to 470) and a second portion (404) disposed in the second trench (second trench formed according to 462), wherein the first portion (403, 461, 463) includes a liner film (461, 463) disposed along the sidewall and a bottom surface of the first trench (sidewall and bottom surface of first trench occupied by 403, 461, 463 according to 470); and a filling film (403) disposed on the liner film (461, 463), wherein the filling film (403) is made of a multi-grain conductive material (see FIG. 4B), wherein the second portion (404) is made of a single grain conductive material (¶ [0092]).
FIGS. 1-4F of Han teach a method for manufacturing a through-contact (e.g. FIGS. 1-4F ¶ [0026]), the method comprising forming a trench (H1) to extend through an interlayer insulating film (120 ¶ [0053]), the trench including a first trench (space occupied by 132 ¶ [0056]) and a second trench (space occupied by 134) disposed on the first trench (132 ¶ [0066]); forming a pre-liner film (132a-132b) along a sidewall and a bottom surface of the trench (sidewall and bottom surface of H1 ¶ [0056]); forming an inhibiting layer (132c) on a portion of the pre-liner film (132a-132b), which is disposed on a sidewall of the second trench (sidewall of 132 shown in FIG. 1), such that the inhibiting layer (132c) is not formed on a portion of the pre-liner film (132a-132b) disposed on a sidewall of the first trench (sidewall of H1 ¶ [0059]-[0060], see FIG. 4C).
However, the prior art fails to teach or reasonably suggest “wherein the method further comprises forming the filling film in the first trench, and removing the inhibiting layer after forming the filling film” together with all the limitations of claim 17 as claimed. Claims 19-20 are allowable insofar as they depend upon and require all the limitations of claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights