Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/23/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
Applicant’s amendments to the specification have overcome the Examiner’s objections to the specification. Therefore, the objections to the specification are withdrawn.
Claim Objections
Applicant’s amendments to the claims have over the Examiner’s claim objections. Therefore, the claim objections are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10-13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al 1 drawn to FIG. 22 of US 20200091186 A1 in view of Yang et al 2 drawn to FIG. 21 of US 20200091186 A1 and in further view of Kwon et al US 20230328986 A1 . Yang et al 1, Yang et al 2, and Kwon et al will be referenced to as Yang 1, Yang 2, and Kwon respectively henceforth.
Regarding Claim 1,
Yang 1 teaches:
“A memory device, comprising (FIG. 21):
source-level material layers comprising, from bottom to top, a lower source-level semiconductor layer (well impurity region 10W, [0086] , FIG. 22), a source contact layer (first source conductive pattern SCP1, [0084, 0086], FIG. 22), and an upper source-level semiconductor layer (second source conductive pattern SCP2, [0084, 0086], FIG. 22: SCP2 is made of semiconductor material.);
an alternating stack (block structure BLK, [0047], FIG. 22) of insulating layers (interlayered insulating layers 51, [0051], FIG. 22) and electrically conductive layers (cell gate electrodes CGE1, CGE2, [0047], FIG. 22) located over the source-level material layers (FIG. 22);
a memory opening vertically extending through the alternating stack, the upper source-level semiconductor layer, and the source contact layer ([0011-0013], [0024], FIG. 10A, FIG. 11A, annotated FIG. 22 #1: FIG. 10A shows a process step in which a memory opening is made. The memory opening is filled in FIG. 11A. The memory fill structure of FIG. 11A is the same as the one in annotated FIG. 22 #1.);
a memory opening fill structure located in the memory opening and comprising a memory film (blocking insulating pattern 61, charge storing pattern 63, tunnel insulating pattern 65, [0054] FIG. 22) and a vertical semiconductor layer having a surface segment that contacts the source contact layer (vertical semiconductor pattern VS, [0054], FIG. 22: VS contacts SCP1.);”
Yang 1 doesn’t substantially teach:
“and a lateral isolation trench fill structure including an insulating material portion having a stepped outer sidewall that contacts the alternating stack, wherein the stepped outer sidewall comprises an upper sidewall segment that vertically extends through a first subset of the insulating layers and the electrically conductive layers within the alternating stack, a lower sidewall segment that contacts a second subset of the insulating layers and the electrically conductive layers within the alternating stack, and a horizontally-extending surface segment that is adjoined to the upper sidewall segment and to the lower sidewall segment.”
However, Yang 2 teaches:
“and a lateral isolation trench fill structure (source contact plugs CSPLG, insulating spacer 17, [0073], FIG. 21) including an insulating material portion having a stepped outer sidewall that contacts the alternating stack (insulating spacer 17, [0073], FIG. 21), wherein the stepped outer sidewall comprises an upper sidewall segment (annotated FIG. 21 #1) that vertically extends through a first subset of the insulating layers and the electrically conductive layers within the alternating stack (second stack structure ST2, [0047], FIG. 21), a lower sidewall segment (annotated FIG. 21 #1) that contacts a second subset of the insulating layers and the electrically conductive layers within the alternating stack (first stack structure ST1, [0047], FIG. 21), and a horizontally-extending surface segment that is adjoined to the upper sidewall segment and to the lower sidewall segment (annotated FIG. 21 #1),”
Neither Yang 1 nor Yang 2 teaches:
“wherein a periphery of an interface between the lower source-level semiconductor layer and the source contact layer is located at the lower sidewall segment of the lateral isolation trench fill structure.”
However, Kwon teaches:
“wherein a periphery of an interface between the lower source-level semiconductor layer and the source contact layer is located at the lower sidewall segment of the lateral isolation trench fill structure (Kwon: plate layer 101, conductive layer 102, [0028], [0030], [0032]annotated FIG. 7A#1: The periphery of an interface between 101 and 102 is an interface between a conductive source structure and a doped semiconductor layer.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Yang 1 is modifiable in view of Yang 2 and Kwon.
This is because Yang teaches that FIG. 22 may have the same or similar features as the figures before it, such as FIG. 21 with the exception of the differences shown in FIG. 22 (Yang 1: [0086]). One of ordinary skill in the art would consider the stepped structure of the insulating spacer of FIG. 21 to be a feature which is compatible with FIG. 22 and would therefore consider the combination.
Further, this is because Yang 1/Yang 2 teaches a source contact plug surrounded by a dielectric sidewall contacting a source contact. Yang 1/Yang 2 doesn’t substantively teach a dielectric sidewall which extends into a doped semiconductor layer having an interface with a source contact. Kwon teaches a source contact plug surrounded by a dielectric sidewall contacting a source contact. Kwon further teaches a dielectric sidewall which extends into a doped semiconductor layer having an interface with the source contact. Because both Yang 1/Yang 2 and Kwon have a source contact plug surrounded by a dielectric sidewall contacting the source contact, one of ordinary skill in the art would have deemed it obvious to substitute the dielectric sidewall surrounding a source contact plug of Yang 1/Yang 2 for a dielectric sidewall surrounding a source contact plug which extends into a doped semiconductor layer having an interface with a source contact of Kwon for the predictable result of a source contact plug which is electrically isolated from neighboring conductive structures.
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Annotated FIG. 22 #1
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680
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Annotated FIG. 7A #1
Regarding Claim 2,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 1, wherein the lateral isolation trench fill structure vertically extends through the upper source-level semiconductor layer and the source contact layer (Yang 1: FIG. 22: CSPLG extends through 10W and SCP1 and SCP2.).”
Regarding Claim 3,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 2, wherein the lateral isolation trench fill structure contacts a recessed surface of the lower source-level semiconductor layer (Yang 1: annotated FIG. 22 #2).”
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Annotated FIG. 22 #2
Regarding Claim 4,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 1, wherein the insulating material portion contacts a horizontal surface segment of a bottommost insulating layer within the first subset (Yang 2: FIG. 21: 17 contacts a horizontal surface of the bottommost 51.). ”
Regarding Claim 5,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 1, wherein the insulating material portion contacts each of the insulating layers within the alternating stack and each of the electrically conductive layers within the alternating stack (Yang 2: FIG. 21). ”
Regarding Claim 10,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 1, wherein:
the stepped outer sidewall laterally extends straight along a first horizontal direction (Yang 2: annotated FIG. 21 #1); and
a contact area between the source contact via structure and the recessed surface of the lower source-level semiconductor layer laterally extends along the first horizontal direction (Yang 1: annotated FIG. 22 #2: CSPLG has a length along 10W. This is one width of the contact area.) and has a uniform width along a second horizontal direction that is perpendicular to the first horizontal direction (Yang 1: FIG. 3: The CSPLG has a uniform width along directions D1 and D2. A second width of the contact area lies along D1.).”
Regarding Claim 11,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 1, wherein the memory opening fill structure comprises a stepped surface that comprises (Yang 1: FIG. 22):
an upper surface segment that contacts the first subset of the insulating layers and the electrically conductive layers within the alternating stack (Yang 1: annotated FIG. 22 #3);
a lower surface segment that contacts the second subset of the insulating layers and the electrically conductive layers within the alternating stack (Yang 1: annotated FIG. 22 #3); and
an annular surface segment that is adjoined to the upper surface segment and to the lower surface segment (Yang 1/ Yang 2: [0021], [0022], [0082], FIGs. 19-21: one of ordinary skill in the art would recognize that FIG. 19-21 are combinable from [0082]. Further, FIG. 20 shows that the annular surface segment from annotated FIG. 22 #3 is annular.).”
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Annotated FIG. 22 #3
Regarding Claim 12,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 11, wherein the annular surface segment is located in a horizontal plane including the horizontally-extending surface segment (Yang 2: FIG. 21). ”
Regarding Claim 13,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 11, wherein the annular surface segment contacts an annular bottom surface segment of a bottommost insulating layer within the first subset (Yang 2: FIG. 21): the bottommost surface segment of a bottommost insulating layer must be annular as this surface segment is shared with the annular surface segment.”
Regarding Claim 21,
Yang 1/Yang2/Kwon teaches:
“The memory device of Claim 1, wherein a horizontal plane extends through the interface between the lower source-level semiconductor layer and the source contact layer (Kwon: annotated FIG, 7A #1), and through the lower sidewall segment of the lateral isolation trench fill structure (Kwon: annotated FIG, 7A #1).”
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yang 1/Yang 2/Kwon as applied to claims 1-5 and 10-13 and 21 above, and further in view of Hopkins et al US 20200119038 A1. Hopkins et al will be referenced to as Hopkins henceforth.
Regarding Claim 6,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 1, wherein:
the lower sidewall segment has a first average taper angle relative to a vertical direction (Yang 2: FIG. 21);”
Yang 1/Yang 2/Kwon doesn’t substantially teach:
“the upper sidewall segment is vertical or has a second average taper angle relative to the vertical direction that is less than the first average taper angle.”
However, Hopkins teaches:
“the upper sidewall segment is vertical or has a second average taper angle relative to the vertical direction that is less than the first average taper angle (Hopkins: [0007],[0015])”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Yang 1/Yang 2/Kwon is modifiable in view of Hopkins.
This is because Hopkins teaches that ideally openings made into an alternating stack have vertical walls so that a sufficient amount of material is exposed at the bottom of the stack. However, etching these openings inherently results in tapered sidewalls. The inclusion of shoulder and undercut portions however accommodate the formation of materials within the opening. Therefore, one of ordinary skill in the art would reduce the second taper angle relative to the first to maintain good exposure of material at the bottom of the stack while also accommodating the formation of materials within the opening by including shoulder and undercut portions.
Claims 7, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang 1/Yang 2/Kwon as applied to claims 1-5, 10-13 and 21 above, and further in view of Kanakamedala et al US 9824966 B1. Kanakamedala et al will be referenced to as Kanakamedala henceforth.
Regarding Claim 7,
Yang 1/Yang 2/Kwon teaches:
“The memory device of Claim 1,”
Yang 1/Yang 2/Kwon doesn’t substantially teach:
“wherein the insulating material portion comprises an insulating spacer that vertically extends from a top surface of the lateral isolation trench fill structure to a recessed surface of the lower source-level semiconductor layer.”
However, Kanakamedala teaches:
“wherein the insulating material portion comprises an insulating spacer that vertically extends from a top surface of the lateral isolation trench fill structure to a recessed surface of the lower source-level semiconductor layer (Kanakamedala: insulating spacer, col 20 lines 8-20, FIG. 20: 74 is in contact with layer 10D.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Yang 1/Yang 2 is modifiable in view of Kanakamedala.
This is because Yang 1/Yang 2 teaches an insulating spacer that vertically extends from a top surface of a lateral isolation trench fill structure to a semiconductor layer. Yang 1/Yang 2 doesn’t substantively teach an insulating spacer that vertically extends to a recess of a lower semiconductor layer. Kanakamedala teaches an insulating spacer that vertically extends from a top surface of a lateral isolation trench fill structure to a semiconductor layer. Kanakamedala further teaches an insulating spacer that vertically extends to a recess of a lower semiconductor layer. Because both Yang 1/Yang 2 and Kanakamedala have an insulating spacer that vertically extends from a top surface of a lateral isolation trench fill structure to a semiconductor layer, one of ordinary skill in the art would have deemed it obvious to substitute the insulating spacer that vertically extends from a top surface of a lateral isolation trench fill structure to a semiconductor layer of Yang 1/Yang 2 for an insulating spacer that vertically extends from a top surface a lateral isolation trench fill structure to a recess of a lower semiconductor layer of Kanakamedala for the predictable result of causing indirect electron flow from a source contact to neighboring semiconductor regions.
Regarding Claim 8,
Yang 1/Yang 2/Kwon /Kanakamedala teaches:
“The memory device of Claim 7, wherein the lateral isolation trench fill structure further comprises a source contact via structure in contact with a recessed surface of the lower source-level semiconductor layer (Yang 1: FIG. 22: CSPLG is in contact with 10W.).”
Regarding Claim 9,
Yang 1/Yang 2/Kwon /Kanakamedala teaches:
“The memory device of Claim 7, wherein the insulating spacer further comprises a straight inner sidewall that is free of any step and vertically extends at least from a horizontal plane including a topmost surface of the alternating stack and at least to a horizontal plane including a top surface of the upper source-level semiconductor layer (Yang 1/Yang 2: FIGs. 21-22: The interior sidewall of 17 extends from the top of the stack to layer 10. Therefore, were FIG. 21 and FIG. 22 be combined, 17 would extend from the top of the stack to SCP1 which is below SCP2.). ”
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yang 1/Yang 2/Kwon as applied to claims 1-5, 10-13 and 21 above, and further in view of Lee et al US 9627405 B1. Lee et al will be referenced to as Lee henceforth.
Regarding Claim 14,
Yang 1/Yang 2 teaches:
“The memory device of Claim 1, wherein:
the vertical semiconductor layer comprises a channel portion having a doping of a first conductivity type (Yang 1: [0051]: VS may include a doped silicon layer.).”
Yang 1/Yang 2 doesn’t substantially teach:
“and a source extension region having a doping of a second conductivity type that is an opposite of the first conductivity type;”
However, Lee teaches:
“and a source extension region having a doping of a second conductivity type that is an opposite of the first conductivity type (Yang 1/Lee: Lee: first doped region A1, col 7 lines 60-67, col 8 lines 1-9, FIG. 2A: A1 is n-type. A2 is p-type; Yang 1: [0084], FIG. 22: SCP1 may be n-doped);”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Yang 1/Yang 2/Kwon is modifiable in view of Lee.
This is because doping a first part of a channel with p-type dopants helps to increase the threshold voltage of a first part of a channel. One of ordinary skill in the art would recognize that increasing the threshold voltage of a channel is advantageous because low threshold voltages result in noise signals being recorded as false positives causing errors in stored data.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yang 1/Yang 2/Kwon /Lee as applied to claim 14 above, and further in view of Hsu et al US 20190027227 A1. Hsu et al will be referenced to as Hsu henceforth.
Regarding Claim 15,
Yang 1/Yang 2/Kwon/Lee teaches:
“The memory device of Claim 14, wherein:
the second subset of the electrically conductive layers comprises bottom source- select-level electrically conductive layers (Yang 1: ground selection gate electrode GGE, [0048], FIG. 22); word lines (Yang 1: [0048], FIG. 22: CGE2 may be a word line.) and drain-select-level electrically conductive layers (Yang 1: String selection gate electrode SGE, [0048]: SGE may be provided at two or more different levels ) located over the bottom source-select-level electrically conductive layers (Yang 1: FIG. 22); and
the p-n junction is located in horizontal plane between a bottommost surface of the second subset and a topmost surface of the second subset (Yang 1/Lee: Lee: FIG. 2A: A p-n junction is formed between two semiconductor regions of different dopant conductivities. The p-n junction is formed inside the source-side channel region at a same height level as the bottommost ILD. Therefore, one of ordinary skill in the art combining Yang 1 and Lee would place the p-n junction of Lee in the second stack which is nearest to the source region.).”
Yang 1/Yang 2/Lee doesn’t substantially teach:
“the first subset of the electrically conductive layers comprises additional source- select-level electrically conductive layers (Hsu: control signal ISG0, [0041], FIG. 5B: A lower stack of word lines, 509b, is coupled to control signal ISG1. The control signals select the gates.)”
However, Hsu teaches:
“the first subset of the electrically conductive layers comprises additional source- select-level electrically conductive layers (Hsu: control signal ISG0, [0041], FIG. 5B: A lower stack of word lines, 509b, is coupled to control signal ISG1. The control signals select the gates.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Yang 1/Yang 2/Kwon /Lee is modifiable in view of Hsu.
This is because one of ordinary skill in the art would want to include control signals in each stack to reduce program-disturb. Program-disturb is a drawback in which unselected word lines are boosted with a medium high voltage which boosts the channel which program inhibits a memory cell. This drawback is exacerbated by high density 3D NAND arrays. Program-disturb is reduced by selectively enabling and disabling the one or more internal select gates to isolate string segments. Therefore, one of ordinary skill in the art could reduce program-disturb by introducing several control signals. (Hsu: Abstract, [0007-0009]).
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 103 rejections.
The Examiner notes that Applicant states that , “a horizontal plane that extends through the interface between the lower source-level semiconductor layer l0W and the source contact layer SCP1 is located above the lower sidewall segment of the lateral isolation trench fill structure 17”. However, as shown in Applicant’s annotated figure, a horizontal plane that extends through the interface between the lower source-level semiconductor layer l0W and the source contact layer SCP1 is located below the lower sidewall segment of the lateral isolation trench fill structure 17.
Nonetheless, Applicant’s arguments, with respect to the rejection(s) of the claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kwon.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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