Prosecution Insights
Last updated: July 17, 2026
Application No. 18/349,578

STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS

Non-Final OA §102§103
Filed
Jul 10, 2023
Priority
Nov 29, 2022 — provisional 63/385,328
Examiner
YUSHINA, GALINA G
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
861 granted / 1085 resolved
+11.4% vs TC avg
Strong +17% interview lift
Without
With
+16.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
36 currently pending
Career history
1115
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
72.3%
+32.3% vs TC avg
§102
5.8%
-34.2% vs TC avg
§112
19.5%
-20.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1085 resolved cases

Office Action

§102 §103
CTNF 18/349,578 CTNF 85886 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Acknowledgement of RCE Filing and Status of Claims 07-42-04 AIA A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/01/26 has been entered. The amendment filed on 05/01/26 has been entered. Applicant did not amend earlier examined device Claims 1-14 chosen without traverse in the Response to Restriction Requirements filed 01/16/26, but provided a new IDS. Claims 1-14 are examined on merits herein. Information Disclosure Statement 06-52 AIA The information disclosure statement (IDS) submitted on 05/01/26 was filed after the mailing date of the Notice Allowance on 04/15/26 . The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 t hat form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-3 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (US 2024/0107760) . In re Claim 1, Wang teaches a memory device (Abstract), comprising (Fig. 5): an alternating stack of insulating layers 503 (paragraph 0066) and composite layers 502, 505 (paragraphs 0066, 0071), wherein each of the composite layers comprises an electrically conductive layer 502 and a dielectric material plate 505; memory openings 710 (the number is shown in Fig. 7A, paragraph 0087) vertically extending through the alternating stack; memory opening fill structures – each fill structure identified as a channel structure 714 in the method of manufacturing shown in Figs. 7A-7O - and disposed under channel contacts 506 in Fig. 5 (paragraph 0069), the channel structure includes a memory layer and a channel layer (paragraphs 0015, 0088) located in the memory openings 710, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements – as a stack of portions of a memory layer, where each portion is chosen at a location of a corresponding level of electrically conductive layer 502 - and a vertical semiconductor channel (paragraph 0088); and a plurality (as Figs. 2-4 show) of integrated line-and-via structures 106, 206 (paragraphs 0054, 0065), wherein each of the plurality of integrated line-and-via structures 106, 206 comprises: a conductive plate portion 206 (shown as 743 in a step of manufacturing of Fig. 7O, paragraph 0118) that contacts the electrically conductive layer 502 of a respective one of the composite layers 502, 505 (paragraph 0070; the composite layers 502, 505 correspond to conductive layers 732 and dielectric plates 708 in a method of manufacturing shown in Figs. 7A-7P); and a conductive via portion 106 (Fig. 5, paragraph 0054) that is adjoined to a top surface of the conductive plate portion 206 and vertically extends through a respective overlying subset of the insulating layers 503 and a subset of the dielectric material plates 505 of the composite layers 505, 502. In re Claim 2 , Wang teaches the memory device of Claim 1 as cited above, wherein (Fig. 5; see also Figs. 2-3): the plurality of integrated line-and-via structures 106, 206 are located in a contact region 103 (paragraph 0056); the memory opening fill structures are located in a memory array region; and the memory array region includes the electrically conductive layers of the composite layers and does not include the dielectric material plates of the composite layers. In re Claim 3 , Wang teaches the memory device of Claim 2 as cited above, wherein (Fig. 5 and Annotated Fig. 5): Annotated Fig. 5 PNG media_image1.png 386 696 media_image1.png Greyscale each of the dielectric material plates 505 comprises a combination of a proximal dielectric material plate 505p – in the direction of the memory array - and a distal dielectric material plate 505d (as in Annotated fig. 5) – in the direction to region 105 of 103; the proximal dielectric material plate 505p is more proximal to the memory array region 101 than the distal dielectric material plate 505d is to the memory array region 101; and the conductive plate portion 206 also contacts the proximal dielectric material plate 505p and the distal dielectric material plate 505d of the respective one of the composite layers 502, 505. In re Claim 14 , Wang teaches the memory device of Claim 1 as cited above, wherein (Fig. 5) there are no dielectric barrier structures located between the electrically conductive layers 502 and the dielectric material plates 505; see an addition, a method of the device manufacturing in Figs. 7A through 7P not teaching any dielectric barrier between the electrically conductive layers and dielectric material plates . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Wang . In re Claim 4 , Wang teaches the memory device of Claim 3, wherein (Fig. 1 and Fig. 3) the alternating stack comprises a pair of first lengthwise sidewalls - of slit structures 108 (paragraph 0055) - that laterally extend along a first horizontal direction X; each of the proximal dielectric material plates 505p (of Fig. 5) and the distal dielectric material plates 505d, obviously, comprise a respective straight vertical sidewall (when being similar to dispositions of sidewalls of dielectric and conductive layers of the stack in Fig. 3, and it would have been obvious to create them in the above-described manner, for the manufacturing simplicity) that is parallel to the first horizontal direction X; and the straight vertical sidewalls of the proximal dielectric material plates and the distal dielectric material plates are laterally spaced from a respective proximal one of the pair of first lengthwise sidewalls by a uniform lateral spacing – as is obvious from Figs. 1 and 3. In re Claim 5 , Wang teaches the memory device of Claim 4 as cited above and further teaches (Figs. 1 and 5) that the memory device further comprising first backside trench fill structures – as spacers and insulating material filling the trenches 108 (paragraph 0068) - and comprising a respective insulating material portion contacting a respective first lengthwise sidewall of the pair of first lengthwise sidewalls . 07-21-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Kim et al. (US 2021/0265389) . In re Claim 6 , Wang teaches the memory device of Claim 4 as cited above, wherein (Fig. 1): the alternating stack comprises a pair of second lengthwise sidewalls of a slit 109 (paragraph 0055) that laterally extend along the first horizontal direction X and located midway between the pair of first lengthwise sidewalls of slits 108; and the proximal dielectric material plates – within region 107, as is shown in Figs. 1 and 5 - comprise vertically-straight surface segments (it would have been obvious creating all dielectric material plates in a rectangular shape with vertically straight sidewalls, similar to conductive and insulating layers of the memory structure as shown in Figs. 1 and 3, for the manufacturing simplicity) - that are equidistant - from a vertically-extending edge of one of the pair of second lengthwise sidewalls of 109. Wang does not teach that the proximal dielectric material plates have laterally-concave surface segments. Kim teaches (Fig. 6B, paragraphs 0127-0128) dielectric plates 120, 122 comprised vertically-straight and laterally concave edge segments. Wang and Kim teach analogous arts directed to dielectric plates, and one of ordinary skill in the art before the effective data of filing the application would have had a reasonable expectation of success in modifying the Wang structure in view of the Kim structure, since they are from the same field of endeavor and Kim created a successfully operated device. It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the vertically-straight surface segments of the proximal dielectric material plates with laterally-concave surfaces (per Kim), if such shape is preferred for the manufacturer. In accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant . 07-21-aia AIA Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Liu et al. (US 2019/0096841) . In re Claim 13 , Wang teaches the memory device of Claim 1 as cited above and wherein (Figs. 1-2, 5): the plurality of integrated line-and-via structures 106, 206 is arranged in a row with a uniform pitch along a first horizontal direction X; and the conductive via portions 106 of the plurality of integrated line-and-via structures has a square or rectangular shape and is extended in the first and second horizontal directions, the second horizontal direction being perpendicular to the first horizontal direction. Wang does not teach that the conductive via portions are elongated along a second horizontal direction that is perpendicular to the first horizontal direction. Liu teaches a via (Fig. 2, paragraph 0028) that has an elongated shape in a second direction II-II that is orthogonal to a first direction I-I. Wang and Liu teach analogous arts directed to vias, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Wang device in view of the Liu device, since they are from the same field of endeavor, and the Liu’ via successfully functioning. It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Wang device by creating conductive via portions of the plurality of integrated line-and-via structures such that they would have an elongated shape in the second direction, orthogonal to the first direction, if such shape is preferred for the manufacturer. However, n accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant. Allowable Subject Matter Claims 7, 10, and 12 contain allowable subject matter, while Claims 8-9 depends on Claim 7, and Claim 11 depends on Claim 10. Accordingly, Claims 7-12 are objected by the current Office Action. Reason for Identification Allowable Subject Matter Re Claim 7: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 7 as: “each of the conductive plate portions comprises: a first vertically-straight and laterally convex surface segment contacting a vertically-straight and laterally concave surface of a respective proximal dielectric material plate; and a second vertically-straight and laterally convex surface segment contacting a vertically-straight and laterally concave surface of a respective distal dielectric material plate”: Wang teaches that each of his conductive plates has one vertically straight segment that is in contact with an electrical conductive layer of an alternative stack, and, although Wang does not explicitly teach that the second surface segment contacts a dielectric material plate, this assumption could be viewed as obvious, as well as shapes of these surfaces in view of Kim’s Fig. 6B (as shown for Claim 6). However, this precludes having two contacts of any conductive plate with dielectric plates in the manner described by Claim 7. Other prior arts of record do not cure the above deficiency. Re Claim 10: For the same reason as explained for Claim 7, the prior arts of record do not teach such limitation of Claim 10 as: “the conductive plate portion contacts the electrically conductive layer at two vertically-straight and laterally-straight interfaces” –although Kim teaches the shape of the interfaces, Wang teaches that his conductive plate portions contact the electrically conductive layer at two interfaces – he teaches such contact only at one interface. Re Claim 12: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 12 as: “the uniform pitch is greater than a width of each of the distal dielectric material plates along a second horizontal direction that is perpendicular to the first horizontal direction”, in combination with other limitations of Claim 12 and in combination with all limitations of Claims 1 and 3, on which Claim 12 depends. The prior arts of record include the prior arts cited by the current and earlier Office Actions. Conclusion Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible). Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center - for more information about Patent Center and visit https://www.uspto.gov/patents/docx - for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800, United States Patent and Trademark Office E-mail: galina.yushina@USPTO.gov Phone: 571-270-7440 Date: 06/10/26 Application/Control Number: 18/349,578 Page 2 Art Unit: 2811
Read full office action

Prosecution Timeline

Jul 10, 2023
Application Filed
Feb 06, 2026
Examiner Interview (Telephonic)
Mar 23, 2026
Request for Continued Examination
Mar 26, 2026
Response after Non-Final Action
May 01, 2026
Request for Continued Examination
May 05, 2026
Response after Non-Final Action
Jun 17, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685230
SEMICONDUCTOR DEVICE
2y 10m to grant Granted Jul 14, 2026
Patent 12677439
SEMICONDUCTOR DEVICES WITH SELECTIVELY DOPED GATE ELECTRODE STRUCTURE
3y 2m to grant Granted Jul 07, 2026
Patent 12666653
METAL OXIDE THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE
3y 3m to grant Granted Jun 23, 2026
Patent 12666954
SEMICONDUCTOR DEVICE INCLUDING VARIABLE RESISTANCE PATTERN AND ELECTRONIC SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE
3y 1m to grant Granted Jun 23, 2026
Patent 12660190
INTERVENING POLYSILICON MATERIALS THAT ARE THICKER AT DISTAL EDGES THAN AT PILLARS DEFINING MEMORY CELLS AND RELATED APPARATUSES, SYSTEMS, AND METHODS
3y 9m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+16.8%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1085 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month