DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 9 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2021/0305276; 03/2020 in view of Zhang; US 2020/0194454 A1; 07/2019
Claim 1: Kim ( ‘276 ) discloses a semiconductor memory device ( Fig. 15; [0113] Fig. 15 is a sectional view taken along the line I-I′ of FIG. 3 to illustrate a semiconductor memory device according to an embodiment of the inventive concept ), comprising: a first stacked structure ( Fig. 15: first electrode structure ST1 ) including a plurality of first electrode patterns ( Fig. 15: first electrodes EL1 ) and a plurality of first interlayer insulating layers ( Fig. 15: first insulating layers IL1 ) that are alternately stacked on each other ( as shown in Fig. 15 ); a first vertical structure ( [0117] Each of the vertical channel structures VS may include a first vertical extended portion penetrating the first electrode structure ST1 ) extending through the first stacked structure ( Fig. 15: ST1 ) in a vertical direction ( as shown in the Fig. 15 ); a second stacked structure ( Fig. 15: ST2 ) including a plurality of second electrode patterns ( Fig. 15: second electrodes EL2 ) and a plurality of second interlayer insulating layers ( Fig. 15: second insulating layers IL2 ) that are alternately stacked on each other ( as shown in Fig. 15 ) over the first stacked structure ( Fig. 15: ST2 is stacked on ST1 ); a second vertical structure ( [0117] a second vertical extended portion penetrating the second electrode structure ST2 ) extending through the second stacked structure in the vertical direction ( as shown in Fig. 15 ), an insulating layer ( Fig. 15: IL2 ) disposed between the first stacked structure ( Fig. 15: ST1 ) and the second stacked structure ( Fig. 15: ST2 ); and a coupling structure passing through the insulating layer ( Fig. 15: EXP1 ) and connecting the first vertical structure ( Fig.15: VS in the ST1 region ) and the second vertical structure ( Fig. 15: VS in the ST2 region ), wherein each of the first vertical structure ( Fig. 15: VS in the ST1 region ), the coupling structure ( Fig. 15: EXP1 ), and the second vertical structure ( Fig. 15: VS in the ST2 region ) includes an impurity ( [0047] the vertical semiconductor pattern SP may be formed of or include a doped semiconductor material ).
Kim ( ‘276 ) does not appear to disclose a concentration of the impurity of the coupling structure varies depending on proximity to one of the first vertical structure and the second vertical structure.
However, Zhang teaches a concentration of the impurity of the coupling structure ( [0044] The pad #158 may be, for example polycrystalline silicon including n-type impurities ) varies depending on proximity to one of the first vertical structure ( [0050] the n-type impurities included in the semiconductor layer #110 may be partially diffused into the channel #154 ) and the second vertical structure ( as discussed above ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Kim ( ‘276 ) to implement a concentration of the impurity of the coupling structure varies depending on proximity to one of the first vertical structure and the second vertical structure because of the physics of dopant diffusion and segregation effects during high-temperature manufacturing processes.
Claim 2: Kim ( ‘276 ) and Zhang disclose the semiconductor memory device of claim 1 ( as discussed above ).
Kim ( ‘276 ) teaches the first vertical structure ( Fig. 15: vertical channel structure VS in the ST1 region ) includes a first core layer ( Fig. 15: gap-fill insulating pattern VI in the ST1 region ) and a first channel layer ( Fig. 15: vertical semiconductor pattern SP in the ST1 region ), the first core layer ( Fig. 15: VI in the ST1 region ) extending in the vertical direction ( as shown in Fig. 15 ), the first channel layer ( Fig. 15: SP in the ST1 region ) surrounding a sidewall ( [0044] The vertical semiconductor pattern SP may be provided on (e.g., to cover) an outer surface of the gap-fill insulating pattern VI and may be extended from the lower semiconductor layer LSL to the conductive pad PAD in the third direction D3 ) of the first core layer ( Fig. 15: VI in the ST1 region ) and including the impurity ( [0105] impurities in the polysilicon material may be diffused into the channel region ), wherein the second vertical structure ( Fig. 15: VS in the ST2 region ) includes a second core layer ( Fig. 15: VI in the ST2 region ) and a second channel layer ( Fig. 15: SP in the ST2 region ), the second core layer ( Fig. 15: VI in the ST2 region ) extending in the vertical direction ( as shown in Fig. 15 ), the second channel layer ( Fig. 15: SP in the ST2 region ) surrounding a sidewall ( as discussed above ) of the second core layer ( Fig. 15: VI in the ST2 region ) and including the impurity ( [0047] the vertical semiconductor pattern SP may be formed of or include a doped semiconductor material ), wherein the coupling structure ( Fig. 15: EXP1 ) includes a third core layer ( Fig. 15 VI in the EXP1 region ) and a coupling channel layer ( Fig. 15: SP in the EXP1 region ), the third core layer extending in the vertical direction ( as shown in Fig. 15 ), the coupling channel layer ( Fig. 15 SP in the EXP1 region ) surrounding a sidewall of the third core layer ( as shown in Fig. 15 ) and including the impurity ( [0105] impurities in the polysilicon material may be diffused into the channel region ), and wherein the coupling channel layer ( Fig. 15: EXP1 ) is disposed between the first channel layer ( Fig. 15 SP in the ST1 region ) and the second channel layer ( Fig. 15 SP in the ST2 region ).
Claim 3: Kim (‘276) and Zhang disclose the semiconductor memory device of claim 2 ( as discussed above ).
Kim ( ‘276 ) discloses a lower part of the coupling channel layer ( Fig. 15: lower part of SP in the EXP1 region ) contacts an upper part of the first channel layer ( Fig. 15: upper part of SP in the ST1 region ), and an upper part of the coupling channel layer ( Fig. 15: upper part of SP in the EXP1 region ) contacts a lower part of the second channel layer ( Fig. 15: lower part of SP in the ST2 region ).
Claim 9: Kim ( ‘276 ) and Zhang disclose the semiconductor memory device of claim 2 ( as discussed above).
Kim ( ‘276 ) teaches a thickness of the coupling channel layer ( Fig. 15: SP in the EXP1 region ) in a horizontal direction is greater than a thickness of each of the first channel layer ( Fig. 15: SP in the ST1 region ) and the second channel layer ( Fig. 15: SP in the ST2 region ) in the horizontal direction ( [0117] A diameter of the vertical channel structure VS may be abruptly increased at the first expanding portion EXP1 ).
Claims 4 and 7 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2021/0305276; 03/2020 in view of Zhang; US 2020/0194454 A1; 07/2019 as it relates to claim 2 and further in view of Kim et al.; US 2023/0145117 A1; 11/2022
Claim 4: Kim (‘276) and Zhang disclose the semiconductor memory device of claim 3 ( as discussed above ).
Neither Kim ( ‘276 ) nor Zhang appear to disclose a lower part of the first vertical structure is coupled to a source line and an upper part of the second vertical structure is coupled to a bit line, wherein the first vertical structure and the plurality of first electrode patterns are defined as a first cell portion including a plurality of first memory cells, the plurality of first electrode patterns surrounding a sidewall of the first vertical structure at different levels, and wherein the second vertical structure and the plurality of second electrode patterns are defined as a second cell portion including a plurality of second memory cells, the plurality of second electrode patterns surrounding a sidewall of the second vertical structure at different levels.
However, Kim ( ‘117 ) teaches a lower part of the first vertical structure ( Fig. 13: ST1 ) is coupled to a source line ( Fig. 13: CSL ) and an upper part of the second vertical structure ( Fig. 13: ST2 ) is coupled to a bit line ( Fig. 13: BL ), wherein the first vertical structure ( Fig. 13: ST1 ) and the plurality of first electrode patterns ( [0036] The gate electrode layers of the memory block may be connected with a string selection line SSL ) are defined as a first cell portion ( Fig. 2: BLK1 ) including a plurality of first memory cells ( Fig. 4: ST1 ), the plurality of first electrode patterns ( Fig. 4: GST ) surrounding a sidewall ( as shown in Fig. 11 ) of the first vertical structure at different levels ( as shown in Fig. 13 ), and wherein the second vertical structure ( Fig. 4: ST2 ) and the plurality of second electrode patterns ( Fig. 4: SST ) are defined as a second cell portion including a plurality of second memory cells ( Fig. 4: ST2 ), the plurality of second electrode patterns ( Fig. 4: SST ) surrounding a sidewall ( as shown in Fig. 11 ) of the second vertical structure at different levels ( levels shown in Fig. 10 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim (‘117) with Kim (‘276) and Zhang to implement a lower part of the first vertical structure is coupled to a source line and an upper part of the second vertical structure is coupled to a bit line, wherein the first vertical structure and the plurality of first electrode patterns are defined as a first cell portion including a plurality of first memory cells, the plurality of first electrode patterns surrounding a sidewall of the first vertical structure at different levels, and wherein the second vertical structure and the plurality of second electrode patterns are defined as a second cell portion including a plurality of second memory cells, the plurality of second electrode patterns surrounding a sidewall of the second vertical structure at different levels because this defines a U-shaped or pope-shaped vertical NAND string architecture.
Claim 7: Kim (‘276), Zhang, and Kim (‘117) disclose the semiconductor memory device of claim 4 ( as discussed above ).
Neither Kim(‘276) nor Zhang appear to disclose the plurality of first memory cells and the plurality of second memory cells are sequentially programmed in order from a memory cell adjacent to the bit line to a memory cell adjacent to the source line during a program operation.
However, Kim(‘117) teaches the plurality of first memory cells ( Fig. 7: ST1 ) and the plurality of second memory cells ( Fig. 7: ST2 ) are sequentially programmed ( as shown in Fig. 7 ) in order from a memory cell adjacent to the bit line to a memory cell adjacent to the source line during a program operation ( [0072] a top to bottom (T2B) program operation, in which programming is sequentially performed from the uppermost word line towards the bottom, may be performed ) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim(‘117) with Kim (‘276) and Zhang to implement the plurality of first memory cells and the plurality of second memory cells are sequentially programmed in order from a memory cell adjacent to the bit line to a memory cell adjacent to the source line during a program operation because this manages punch-through effects and optimizes specific voltage biasing conditions.
Claim 5 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 20210305276; 03/2020 in view of Zhang; US 2020/0194454 A1; 07/2019 and Kim et al.; US 2023/0145117 A1; 11/2022 as is relates to claim 4 above and further in view of Linnen et al.; US 10,943,662 B1; 12/2019
Claim 5: Kim (‘276), Zhang, and Kim (‘117) disclose the semiconductor memory device of claim 4 ( as discussed above ).
Neither Kim (‘276) nor Zhang nor Kim (‘117) appear to disclose the plurality of first memory cells and the plurality of second memory cells are sequentially programmed in order from a memory cell adjacent to the source line to a memory cell adjacent to the bit line during a program operation.
However, Linnen teaches the plurality of first memory cells ( Fig. 3: Block 0 ) and the plurality of second memory cells ( Fig. 3: Block 1 ) are sequentially programmed ( Fig. 9A ) in order from a memory cell adjacent to the source line to a memory cell adjacent to the bit line during a program operation ( Col. 3 lines 28-32 During a programming operation, the memory cells are programmed according to a word line programming order. For example, the programming may start at the word line at the source side of the block and proceed to the word line at the drain end of the block ) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Linnen with Kim (‘276 ), Zhang, and Kim (‘117) to implement the plurality of first memory cells and the plurality of second memory cells are sequentially programmed in order from a memory cell adjacent to the source line to a memory cell adjacent to the bit line during a program operation because this approach manages and mitigates a significant reliability challenge known as program interference.
Claim 6 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 20210305276; 03/2020 in view of Zhang; US 2020/0194454 A1; 07/2019, Kim et al.; US 2023/0145117 A1; 11/2022, and Linnen et al.; US 10,943,662 B1; 12/2019 as it relates to claim 5 above and further in view of Lee; US 2012/0299005 A1; 12/2011
Claim 6: Kim (‘276), Zhang, Kim(‘117), and Linnen disclose the semiconductor memory device of claim 5 ( as discussed above ).
Neither Kim (‘276) nor Zhang nor Kim(‘117) nor Linnen appear to disclose the concentration of the impurity of the coupling channel layer is the highest in a region that is in contact with the first channel layer and becomes lower in a direction toward the second channel layer.
However, Lee (‘005) teaches the concentration of the impurity of the coupling channel layer ( [0037] an initial first impurity doped region #202 is formed by doping the upper portion of the second channel #200 with a first impurity ) is the highest in a region that is in contact with the first channel layer ( [0038] the bottom surface of the initial first impurity doped region #202 is shown to be a little lower than the upper surface of the second conductive layer #170 ) and becomes lower in a direction toward the second channel layer ( [0043] the second impurity doped region #204 has a lower bandgap energy than the final first impurity doped region #202’ ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee (‘005) with Kim(‘276), Zhang, Kim (‘117) and Linnen to implement the concentration of the impurity of the coupling channel layer is the highest in a region that is in contact with the first channel layer and becomes lower in a direction toward the second channel layer because the non-uniform doping profile optimizes device performance, manages short-channel effects and ensures reliable operation.
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 20210305276; 03/2020, Zhang; US 2020/0194454 A1; 07/2019 and Kim et al.; US 2023/0145117 A1; 11/2022 as it relates to claim 7 and further in view of Lee et al.; US 2012/0168852 A1; 01/2012
Claim 8: Kim (‘276), Zhang, Kim (‘117) disclose the semiconductor memory device of claim 7 ( as discussed above ).
Neither Kim (‘276) nor Zhang nor Kim (‘117) appear to disclose the concentration of the impurity of the coupling channel layer is the highest in a region that is in contact with the second channel layer and becomes lower in a direction toward the first channel layer.
However, Lee (‘852) teaches the concentration of the impurity ( [ 0043] the first impurity layers #114aabout.114f may be formed at the boundary between the channel and drain region #112f of the string selection transistor ) of the coupling channel layer is the highest in a region that is in contact with the second channel layer ( [0044] the regions to which the second impurity layers #116a and #116f are additionally provided are configured with a higher impurity concentration relative to the regions of the first impurity layers ) and becomes lower in a direction toward the first channel layer ( as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee (‘852) with Kim (‘276), Zhang, and Kim (‘117) to implement the concentration of the impurity of the coupling channel layer is the highest in a region that is in contact with the second channel layer and becomes lower in a direction toward the first channel layer because the concentration of the impurity of the coupling channel layer is the highest in a region that is in contact with the second channel layer and becomes lower in a direction toward the first channel layer because reverse graded doping profiles address suppression of short-channel effects and balancing drive current and SCEs.
Response to Amendments / Arguments
Applicant’s arguments, see pages 9 - 14 of remarks, filed 03/17/2026, with respect to the rejection of claim 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim (‘276).
Applicant’s arguments, see pages 1, filed 03/17/2026, with respect to the rejection of claim 2 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim (‘276).
Applicant’s arguments, see pages 1, filed 03/17/2026, with respect to the rejection of claim 9 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim (‘276).
Applicant’s arguments, see pages 1, filed 03/17/2026, with respect to the rejection of claim 3-8 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim (‘276).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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