DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant's arguments filed 06/22/2026 with respect to the rejection of claims 1-9, 11-13 and 23 under 35 U.S.C. 102 and 103 have been fully considered but they are not persuasive. The argument that Kimura does not teach wherein a “second filling material fills only a boundary area between adjacent ones of the plurality of upper substrates” is not persuasive because this limitation does appear to be taught by Kimura. Figures 3 and 4 of Kimura depict a plurality of upper substrates (81/82/83) which are surrounded by a second filling material (70) between adjacent ones of the upper substrates (81/82/83). The arguments against the combination of Kimura in view of Eom are not persuasive because the combination does not propose replacing the second filling material of Kimura (70) with the filling material of Eom (Fig.6 400 of Eom). Instead, page 7 of the rejection mailed on 04/08/2026 proposes lowering the height of the light blocking layer taught by Kimura (85) in a similar manner taught by Eom (500 of Eom) to include filling material (70) both above and below (shown in Fig.6 of Eom). The rejection makes no mention of substituting components taught by Kimura with components taught by Eom. Reference numerals from Kimura should have originally been used to clarify this stance. Accordingly, the rejection of record is amended in accordance with Applicant’s amendments and upheld.
Applicant's arguments filed 06/22/2026 with respect to the rejection of claims 14-15 and 18-22 under 35 U.S.C. 102 and 103 have been fully considered but they are not persuasive. The broadest reasonable interpretation of Kimura reads upon claim 14 as amended, so the rejection is upheld.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 14-15 and 18-21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kimura et al. (US-20250221133-A1 – hereinafter Kimura).
Regarding claim 14, Kimura teaches a tiling display device (Fig.4; ¶0096) comprising:
a lower substrate (Fig.4 40; ¶0065);
a thin-film transistor (¶0065) disposed over the lower substrate (40);
connection electrodes (Fig.4 41 and 42; ¶0066) disposed over the lower substrate (40) and electrically connected to the thin-film transistor (¶0065);
a plurality of upper substrates (Fig.3 81/82/83; ¶0086) each including a first surface (bottom surface of 81/82/83) and a second surface (top surface of 81/82/83) opposite to the first surface (bottom surface of 81/82/83), wherein light-emitting elements (Fig.3 110/120/130; ¶0080) are disposed over the first surface (bottom surface of 81/82/83) of each of the upper substrates (81/82/83), and each of the plurality of upper substrates (81/82/83) being formed of a transparent material (81/82/83 are formed of a transparent material as depicted by light L1-3 passing through in Fig.4);
a planarization layer (Fig.4 51 and 60; ¶0067 and ¶0081) disposed on each of the plurality of upper substrates (81/82/83) and surrounding a corresponding one of the light-emitting elements (110/120/130);
a first contact hole (Fig.4 a first hole is the space within 51 occupied by 111) defined in the planarization layer (51 and 60) and disposed on a first side (left side) of the corresponding one of the light-emitting elements (110/120/130);
a second contact hole (Fig.4 a second hole is the space within 51 occupied by 112) defined in the planarization layer (51 and 60) and disposed on a second side (right side) of the corresponding one of the light-emitting elements (110/120/130) opposite the first side (left side);
a first electrode (Fig.4 111; ¶0066) disposed on an exposed surface of the first contact hole (space within 51 occupied by 111);
a second electrode (Fig.4 112; ¶0066) disposed on an exposed surface of the second contact hole (space within 51 occupied by 112); and
a plurality of conductive adhesive members (Fig.4 53; ¶0080), respectively disposed between the plurality of upper substrates (81/82/83) and the lower substrate (40) to electrically connect the first electrode (111) and the second electrode (112) to the connection electrodes (41 and 42) of the lower substrate (40), wherein the plurality of upper substrates (81/82/83) are arranged in a matrix form in a first direction and a second direction perpendicular to the first direction, and are spaced apart from each other (Fig.2; ¶0064).
Regarding claim 15, Kimura teaches the tiling display device of claim 14, wherein the plurality of conductive adhesive members (53) respectively bond the plurality of upper substrates (81/82/83) and the lower substrate (40).
Regarding claim 16, Kimura teaches the tiling display device of claim 14, further comprising connection members (Fig.4 41/42; ¶0066) disposed on the lower substrate (40), which electrically connects the light-emitting elements (110) and the thin-film transistor (which is inside 40; ¶0065) to each other.
Regarding claim 17, Kimura teaches the tiling display device of claim 16, wherein the connection members (41/42) are connection electrodes, connection wires or connection patterns (¶0066).
Regarding claim 18, Kimura teaches the tiling display device of claim 14, further comprising a first filling material (Fig.4 50; ¶0067) filled between the lower substrate (40) and each of the plurality of upper substrates (81/82/83).
Regarding claim 19, Kimura teaches the tiling display device of claim 18, further comprising a second filling material (Fig.3 70; ¶0083) filled between adjacent two upper substrates (81/82/83) among the plurality of upper substrates (81/82/83).
Regarding claim 20, Kimura teaches the tiling display device of claim 18, wherein the first filling material (50) includes a resin with relatively high viscosity and low flowability (¶0067).
Regarding claim 21, Kimura teaches the tiling display device of claim 19, wherein the second filling material (70) includes a resin with relatively high viscosity and low flowability (¶0010).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-7, 9, 11 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Eom (US-20210242376-A1).
Regarding claim 1, Kimura teaches a tiling display device (Fig.4; ¶0096) comprising:
a lower substrate (Fig.4 40; ¶0065);
a thin-film transistor (¶0065) disposed over the lower substrate (40);
a plurality of upper substrates (Fig.3 81/82/83; ¶0086) each including a first surface (bottom surface of 81/82/83) and a second surface (top surface of 81/82/83) opposite to the first surface (bottom surface of 81/82/83), wherein light-emitting elements (Fig.3 110/120/130; ¶0080) are disposed over the first surface (bottom surface of 81/82/83) of each of the upper substrates (81/82/83), and wherein the plurality of upper substrates (81/82/83) are spaced apart from each other and are disposed on the lower substrate (40), and the plurality of upper substrates (81/82/83) each being formed of a transparent material (81/82/83 are formed of a transparent material as depicted by light L1-3 passing through in Fig.4);
conductive adhesive members (Fig.4 53; ¶0080) respectively disposed between the lower substrate (40) and the plurality of upper substrates (81/82/83);
a first filling material (Fig.4 50; ¶0067) filling a space between the lower substrate (40) and each of the plurality of upper substrates (81/82/83), wherein the first filling material (50) covers the conductive adhesive members (53), and is filled between the lower substrate (40) and each of the plurality of upper substrates (81/82/83);
a second filling material (Fig.3 70; ¶0083) filling only a boundary area between adjacent ones of the plurality of upper substrates (81/82/83); and
a light blocking pattern (Fig.4 85; ¶0100).
Kimura does not teach wherein the light-blocking pattern is disposed between the first filling material and the second filling material.
Eom teaches an LED package (Fig.6 1000; ¶0063 of Eom) having a light blocking layer (Fig.6 500; ¶0062 of Eom) with a first (Fig.6 420; ¶0062 of Eom) and second (Fig.6 410; ¶0062 of Eom) filling material, the first (420 of Eom) and second (410 of Eom) filling materials having comparable resin properties.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to lower the height of the light blocking layer (85 of Kimura) to include filling material (70 of Kimura) above the light blocking layer (85 of Kimura) as taught by Eom (Fig.6 and 500 of Eom) to arrive at the claimed invention. These modifications are obvious because they are a matter of design choice and do not patentably distinguish the claimed invention over claim 1 or the cited references.
Regarding claim 2, the combination of Kimura in view of Eom from claim 1 teaches the tiling display device of claim 1, wherein the lower substrate (40 of Kimura) is composed of a single sheet substrate, and wherein the upper substrates (81/82/83 of Kimura) are disposed on the lower substrate (40 of Kimura) and are arranged in a matrix form and are spaced apart from each other (see Fig.2 ¶0064 of Kimura).
Regarding claim 3, the combination of Kimura in view of Eom from claim 1 teaches the tiling display device of claim 1, wherein the first filling material includes a resin with relatively high viscosity and low flowability (¶0067 of Kimura).
Regarding claim 4, the combination of Kimura in view of Eom from claim 1 teaches the tiling display device of claim 1, wherein a vertical height of an uppermost face of the first filling material (50 of Kimura) is lower than a vertical height of the first surface (bottom surface) of the upper substrate (81/82/83 of Kimura).
Regarding claim 5, the combination of Kimura in view of Eom from claim 1 teaches the tiling display device of claim 1, wherein each of the upper substrates includes glass or plastic (color conversion layers are well-known to have a resin base, which is a plastic material).
Regarding claim 6, the combination of Kimura in view of Eom from claim 1 teaches the tiling display device of claim 1.
The combination does not teach wherein the second filling material has a second refractive index and a second light transmittance respectively equal to a first refractive index and a first light transmittance of each of the plurality of upper substrates.
Eom teaches an LED package (Fig.6 1000; ¶0063 of Eom) having a light blocking layer (Fig.6 500; ¶0062 of Eom) with a first (Fig.6 300; ¶0063 of Eom) and second (Fig.6 400; ¶0062 of Eom) filling material having comparable resin properties.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the second filling material of Kimura (70 of Kimura) with the second filling material of Eom (400 of Eom) to arrive at the claimed invention. These modifications are obvious because they are a matter of design choice and do not patentably distinguish the claimed invention over claim 1 or the cited references.
Regarding claim 7, the combination of Kimura in view of Eom from claim 6 teaches the tiling display device of claim 6.
The combination does not explicitly teach wherein the second refractive index is in a range of 1.45 to 2.0, and wherein the second light transmittance in a visible light region is 90% or greater.
However, it would have been obvious to form the refractive index and light transmittance within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 9, the combination of Kimura in view of Eom from claim 1 teaches the tiling display device of claim 1, wherein the light-blocking pattern (85 of Kimura) is disposed between adjacent ones of the upper substrates (81/82/83 of Kimura).
Regarding claim 11, the combination of Kimura in view of Eom from claim 10 teaches the tiling display device of claim 9, wherein each of the upper substrates (81/82/83 of Kimura) includes a first surface (bottom surface) on which the light-emitting element (110 of Kimura) is disposed and a second surface (top surface) opposite to the first surface (bottom surface), and
wherein a vertical height of an uppermost face of the light-blocking pattern (500 of Eom) is lower than a vertical height of the first surface (bottom surface) of the upper substrate (81/82/83 of Kimura).
Regarding claim 22, Kimura teaches the tiling display device of claim 18.
Kimura does not teach wherein the first filling material has a first refractive index and a first light transmittance, and the second filling material has a second refractive index equal to the first refractive index and a second light transmittance equal to the first light transmittance.
Eom teaches an LED package (Fig.6 1000; ¶0063 of Eom) having a light blocking layer (Fig.6 500; ¶0062 of Eom) with a first (Fig.6 300; ¶0063 of Eom) and second (Fig.6 400; ¶0062 of Eom) filling material having comparable resin properties.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the second filling material of Kimura (70 of Kimura) with the second filling material of Eom (400 of Eom) to arrive at the claimed invention. These modifications are obvious because they are a matter of design choice and do not patentably distinguish the claimed invention over claim 1 or the cited references.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Eom, and further in view of Han et al. (US-20230279292-A1 – hereinafter Han).
Regarding claim 8, the combination of Kimura in view of Eom from claim 6 teaches the tiling display device of claim 6.
The combination does not teach wherein the second filling material includes perhydropolysilazane resin.
Han teaches an encapsulant that can comprise perhydropolysilazane resin (¶0097 of Han).
It would be obvious to include perhydropolysilazane in the second filling material because it is a known option one of ordinary skill could use when fabricating the device taught by Kimura in view of Eom.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Eom, and further in view of Armitage (US-20230420627-A1 – hereinafter Armitage).
Regarding claim 12, the combination of Kimura in view of Eom from claim 1 teaches the tiling display device of claim 1.
The combination does not explicitly teach wherein the light-emitting element includes:
a first semiconductor layer;
an active layer disposed on one side of one surface of the first semiconductor layer;
a second semiconductor layer disposed on the active layer;
a reflective layer disposed on the second semiconductor layer;
a first electrode connected to the first semiconductor layer; and
a second electrode connected to the reflective layer.
Armitage teaches an LED having a first semiconductor layer (Fig.6 204b; ¶0075 of Armitage);
an active layer (Fig.6 206b; ¶0074 of Armitage) disposed on one side of one surface of the first semiconductor layer (204b of Armitage);
a second semiconductor layer (Fig.6 208b; ¶0077 of Armitage) disposed on the active layer (206b of Armitage);
a reflective layer (Fig.6 218; ¶0086 of Armitage) disposed on the second semiconductor layer (208b of Armitage);
a first electrode (Fig.6 214; ¶0088 of Armitage) connected to the first semiconductor layer (204b of Armitage); and
a second electrode connected to the reflective layer (218 is an electrode and a reflective layer).
It would have been obvious to one of ordinary skill to implement the LED design of Armitage to the structure taught by Kimura to arrive at the claimed invention. This modification is obvious because the design is well known in the art as a suitable LED for the device taught by Kimura.
Regarding claim 13, the combination of Kimura in view of Eom, and further in view of Armitage from claim 12 teaches the tiling display device of claim 12, wherein the reflective layer (218 of Armitage) is in contact with an entirety of one surface of the second semiconductor layer (208b of Armitage).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Eom, and further in view of Stolz et al. (US-20240314904-A1 – hereinafter Stolz).
Regarding claim 23, the combination of Kimura in view of Eom from claim 1 teaches the tiling display device of claim 1, wherein each of the plurality of upper substrates (81/82/83) includes a plurality of sub-pixels (each upper substrate defines an individual sub-pixel of pixel structure Fig.3 100),
each of the plurality of sub-pixels includes a light-emitting element (110/120/130).
Kimura does not teach the display device including a redundant light-emitting element corresponding to the light-emitting element, and
the redundant light-emitting element (ED1b) is provided for a repair process.
Stolz teaches a sub-pixel circuit (Fig.2; ¶0047 of Stolz) having an LED (Fig.2 D31; ¶0047 of Stolz) and a redundant LED (Fig.2 D33; ¶0047 of Stolz) for use in a repair process (¶0047 of Stolz).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the redundant LED of Stolz (D33 of Stolz) to the sub-pixels taught by Kimura (Fig.3 of Kimura) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of having the redundant LED (D33 of Stolz) available for operation should the primary LED (110/120/130 of Kimura) fail (¶0047 of Stolz).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
