DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 2 in the reply filed on 3/9/2026 is acknowledged. The traversal is on the grounds that the protruded spacer of FIG. 6 is present in the other embodiments but not illustrated, so the feature is not mutually exclusive, and that there would be no serious burden to examine all of the claims (Applicant’s Remarks pages 11-12). This is not found persuasive because when discussing the embodiments of FIGS. 18 and 19 in applicant’s specification, the spacer structures described in relation to the FIG. 6 embodiment were not in any way mentioned, not even as “included but not illustrated”. Additionally, a serious burden was demonstrated in the restriction requirement, and the restriction requirement is maintained.
The requirement is still deemed proper and is therefore made FINAL.
Claims 14-15 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 3/9/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “a first size of a second light emitting area defined in the second light emitting element is greater than a size of a third light emitting area defined in the third light emitting element, and the first size of the second light emitting area is greater than a size of a copy light emitting area defined in the copy light emitting element” (e.g. claim 5) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20210210584 A1 (Youn et al hereinafter Youn) in view of US 20210202617 A1 (Cho) and US 20210020718 A1 (Nishioka et al hereinafter Nishioka).
Regarding claim 1, Youn discloses an electronic device comprising: a display panel (the display panel of FIG. 15 ¶ [0220-0226], which includes the structure of FIG. 11 ¶ [0226, 0192-0203]) comprising a first area (FIG. 15, third display area DA3 ¶ [0221]) comprising a transmission area (FIG. 15, transmitting unit TA’ ¶ [0223]) and an element area (FIG. 15, auxiliary pixel Pa ¶ [0223]), a second area (FIG. 15, first display area DA1 [excluding an inner portion which includes light emitting units 200/300 which are connected to dummy light emitting units 200’/300’] is spaced apart from area DA3 ¶ [0221]) spaced apart from the first area, and an intermediate area (FIG. 15, second display area DA2 and the inner portion of area DA1 which includes units 200/300 which are connected to dummy units 200’/300’ ¶ [0221]) disposed between the first area and the second area, the display panel comprising: a base layer (FIG. 10A, substrate 100 ¶ [0078]; FIG. 10A’s structure is included in FIG. 11 ¶ [0194]);
a circuit layer (FIGS. 10A and 16, layers 111, 117, and circuit elements within and between those layers form a circuit layer; FIG. 16 illustrates a cross section of DA3 shown in FIG. 15 ¶ [0227]) disposed on the base layer, the circuit layer comprising: a first pixel circuit (FIG. 16, auxiliary TFT” is part of a first pixel circuit in DA3 ¶ [0228]) disposed in the first area and comprising a first driving transistor (FIG. 16, auxiliary TFT” is a transistor that drives auxiliary OLED’ ¶ [0228]), a second pixel circuit (FIG. 15, unlabeled pixels unconnected to dummy pixels and having pixel circuits are shown in area DA1, e.g. pixel circuit PC2 of FIG. 6 ¶ [0138, 0221]) disposed in the second area and comprising a second driving transistor (FIG. 6, pixel circuit PC2 includes a driving transistor, as regardless of which pixel circuit structure taught in FIGS. 4A and 4B is used in a given embodiment, both have driving TFT T1 to drive the pixel ¶ [0081 ,0088]), and a third pixel circuit (FIGS. 10A and 15, TFT1 at edge of DA1 is in the intermediate area) disposed in the intermediate area and comprising a third driving transistor (FIG. 10A, TFT1 is a driving transistor ¶ [0081, 0137]);
an element layer (FIG. 10A, layer 119 and elements disposed around it are above the circuit layer) disposed on the circuit layer, the element layer comprising: a first light emitting element (FIG. 16, auxiliary OLED’ is electrically connected to auxiliary TFT” ¶ [0228]) electrically connected to the first pixel circuit, a second light emitting element (FIG. 15, unlabeled pixels unconnected to dummy pixels and having light emitting elements are shown in area DA1, e.g. pixel circuit PC2 of FIG. 6 ¶ [0138, 0221], and electrically connected to an OLED, regardless of whether the pixel circuit structure of FIG. 4A or FIG. 4B is employed ¶ [0081, 0086]) electrically connected to the second pixel circuit, a third light emitting element (FIG. 10A, first light emitting unit 300 is electrically connected to TFT1 ¶ [0189]) electrically connected to the third pixel circuit, and a copy light emitting element (FIG. 10A, first dummy light emitting unit 300’ is electrically connected to TFT1 ¶ [0187]) electrically connected to the third pixel circuit.
Youn did not explicitly show an encapsulation layer disposed on the element layer in the embodiment under consideration, nor was it explicitly taught that a W/L ratio of the third driving transistor is greater than a W/L ratio of the second driving transistor, where the W denotes a channel width, and the L denotes a channel length.
Regarding the limitation “an encapsulation layer disposed on the element layer”, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to include such an encapsulation layer in view of the embodiment of FIG. 14 of Youn, which shows an encapsulation layer (FIG. 14, thin film encapsulation 600 ¶ [0215-0216]) disposed on the element layer. Youn also teaches that the encapsulation protects the OLED from damage due to moisture or oxygen exposure (¶ [0216]), so a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to include an encapsulation layer disposed on the element layer as is demonstrated in the embodiment of FIG. 14 of Youn, in order to protect the OLED against external contaminants.
Youn does not explicitly teach that a W/L ratio of the third driving transistor is greater than a W/L ratio of the second driving transistor, where the W denotes a channel width, and the L denotes a channel length, such a parameter not being of particular importance to the disclosure of their invention.
However, Cho discloses a display device wherein channel regions (FIGS. 2A-2B, semiconductor layers 102a and 102b) of transistors in different regions (FIG. 1, regions A and B) of the device have different W/L ratios (¶ [0103]). Nishioka further discloses a display device and teaches that the W/L ratio of channel regions of transistors affects the amount of current that can flow through them (¶ [0050]). The W/L ratio of the driving transistors’ channels is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the W/L ratios of the channels of the third driving transistor and the second driving transistor, since Nishioka has demonstrated that the W/L ratio is a result-effective variable which influences the amount of current that flows through the channels, and since Cho has demonstrated that different transistors in different regions of a display device may have varied W/L ratios for their channel regions. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a configuration wherein a W/L ratio of the third driving transistor is greater than a W/L ratio of the second driving transistor, in order to achieve desirable current flow characteristics in the driving transistors of the respective regions (MPEP 2144.05).
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 2, Youn in view of Cho and Nishioka discloses the limitations of claim 1 as detailed above. Additionally, in view of the routine optimization of the W/L ratios of the channel regions of the various driving transistors in the device discussed regarding claim 1, a person of ordinary skill in the art before the effective filing date of the claimed invention to further arrive at a configuration wherein a W/L ratio of the first driving transistor is greater than the W/L ratio of the third driving transistor, in order to achieve desirable current flow characteristics in the driving transistors (MPEP 2144.05).
Regarding claim 3, Youn in view of Cho and Nishioka discloses the limitations of claim 1 as detailed above, and Youn further discloses that the copy light emitting element comprises a pixel electrode that is integral with a pixel electrode of the third light emitting element (as can be seen in FIG. 10A, first pixel electrode 310 is formed integrally both in first light emitting element 300 and dummy light emitting element 300’ ¶ [0189]).
Regarding claim 4, Youn in view of Cho and Nishioka discloses the limitations of claim 1 as detailed above. Youn in view of Cho and Nishioka as currently considered did not explicitly state that a size of a first light emitting area defined in the first light emitting element is greater than a size of a second light emitting area defined in the second light emitting element. However, Cho further discloses that a size of a first light emitting area defined in the first light emitting element (Cho FIG. 9A, the area of first light emitting part E1 in region A ¶ [0101-0102]) is greater than a size of a second light emitting area defined in the second light emitting element (Cho FIG. 9B, the area of second light emitting part E2 in region B, which may be ¼ of the area of first light emitting part E1 ¶ [0101-0102]). Cho also teaches that in different regions of the display device (specifically a camera-region and non-camera region ¶ [0058-0059]), the pixels are arranged at different resolutions, and also teaches that this configuration allows the first region with lower pixel density to have higher light transmission (¶ [0061]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn in view of Cho such that a size of a first light emitting area defined in the first light emitting element is greater than a size of a second light emitting area defined in the second light emitting element, in order to provide increased light transmission in the transmission region of Youn.
Regarding claim 6, Youn in view of Cho and Nishioka discloses the limitations of claim 1 as detailed above, and Youn further discloses that the intermediate area comprises a first sub-intermediate area (FIG. 15, area DA2 surrounds first/transmission area DA3) surrounding the first area and a second sub-intermediate area (FIG. 15, the inner portion of area DA1 which includes units 200/300 which are connected to dummy units 200’/300’ ¶ [0221], which surrounds area DA2) surrounding the first sub-intermediate area, the copy light emitting element is disposed in the first sub-intermediate area (FIG. 15, dummy light emitting units 300’ and 200’ are in area DA2), and the third light emitting element is disposed in the second sub-intermediate area (FIG. 15, units 200/300 which are connected to dummy units 200’/300’ are in the inner portion of area DA1, considered the second sub-intermediate area).
Regarding claim 8, Youn in view of Cho and Nishioka discloses the limitations of claim 1 as detailed above, and Youn further discloses a plurality of first pixels (FIG. 15, auxiliary pixels Pa are first color pixels in the element area ¶ [0223]; the pixels emit colored light through their respective OLEDs ¶ [0081]) disposed in the element area and comprising first color pixels, a plurality of second pixels (FIG. 15, the pixels in area DA1 that are unlabeled and not connected to dummy pixels in area DA2 are second color pixels, i.e. the pixel shown in FIG. 9 having circuit PC2 and emission unit 200 ¶ [0132]) disposed in the second area and comprising second color pixels, and a plurality of third pixels (FIG. 15, light emitting units 200 and 300 that connect to dummy light emitting units 200’ and 300’ and the dummy light emitting units 200’ and 300’ form third color pixels in the intermediate area portion of area DA1) disposed in the intermediate area and comprising third color pixels, each of the plurality of first pixels comprises the first pixel circuit and the first light emitting element (FIGS. 15-16, auxiliary pixels Pa include auxiliary TFT” and auxiliary OLED’ ¶ [0228]), each of the plurality of second pixels comprises the second pixel circuit and the second light emitting element (FIG. 15, the pixels in area DA1 that are unlabeled and not connected to dummy pixels in area DA2 include pixel circuit PC2 and emitting element 200 as can be seen in FIG. 9 ¶ [0132]), each of the plurality of third pixels comprises the third pixel circuit, the third light emitting element, and the copy light emitting element (FIGS. 10A and 15, third pixels include light emitting unit 300, dummy light emitting unit 300’, and transistor TFT1 included in a third pixel circuit).
Youn did not explicitly teach that a pixel density of the plurality of first pixels is smaller than a pixel density of the plurality of second pixels, a comparison of pixel densities not being a parameter emphasized in their disclosure. However, Cho taught that in different regions of the display device (specifically a camera-region and non-camera region ¶ [0058-0059]), the pixels are arranged at different resolutions, and have different pixel densities such that a pixel density of the plurality of first pixels (pixels in the first region A ¶ [0059]) is smaller than a pixel density of the plurality of second pixels (pixels in the second region B ¶ [0059]), and also teaches that this configuration allows the first region with lower pixel density to have higher light transmission (¶ [0061]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn in view of Cho such that a pixel density of the plurality of first pixels is smaller than a pixel density of the plurality of second pixels, in order to provide increased light transmission in the transmission region of Youn.
Regarding claim 9, Youn in view of Cho and Nishioka discloses the limitations of claim 8 as detailed above, and Youn further discloses that a number of the second color pixels disposed in a reference area among the plurality of second pixels is X times of a number of the first color pixels disposed in the reference area among the plurality of first pixels, where X is a natural number equal to or greater than 2 (annotated FIG. 15 below, a reference area may be drawn up near the border of area DA3 wherein at least twice as many second color pixels are present compared to the number of first color pixels).
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Regarding claim 10, Youn in view of Cho and Nishioka discloses the limitations of claim 9 as detailed above, and Youn further discloses that a sum of sizes of light emitting areas included in each of the third color pixels is greater than a size of a light emitting area included in each of the second color pixels (FIG. 15, since the third color pixels include both the emissive areas of 200/300 and 200’/300’, they have larger emissive areas than the unlabeled second color pixels in area DA1; see also MPEP 2125 I), and the first color pixels, the second color pixels, and the third color pixels are configured to emit lights having a same color (the pixels may emit red, green, blue, or white light ¶ [0081, 0165]; the plurality of pixels emit light of those same colors).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of Cho and Nishioka as applied to claim 1 above, and further in view of US patent publication US 20210193745 A1 (Zhang et al hereinafter Zhang).
Youn in view of Cho and Nishioka discloses the limitations of claim 1 as detailed above, but they do not explicitly disclose that a first size of a second light emitting area defined in the second light emitting element is greater than a size of a third light emitting area defined in the third light emitting element, and the first size of the second light emitting area is greater than a size of a copy light emitting area defined in the copy light emitting element. Youn FIG. 15 does appear to show that light emitting areas (e.g. 200 and 300) may have different sizes, but does not describe such differences in detail.
However, Zhang discloses a display device (the device of FIG. 3 ¶ [0027]), wherein sizes of light emitting areas of respective light emitting elements (FIG. 3, openings 111, 112, and 113 for red, green, and blue emitters respectively ¶ [0053]) may have different areas to adjust based on luminous brightness for each color emitter so that the display uniformity of the display panel is improved (¶ [0056]). Youn also mentioned that red, green, and blue light emitting areas may be present in their device (¶ [0081]).
Youn, Cho, Nishioka, and Zhang all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Implementing the teaching of Zhang, a person of ordinary skill in the art before the effective filing date of the claimed invention would therefore have found it obvious modify the device of Youn in view of Cho and Nishioka further in view of Zhang such that a first size of a second light emitting area defined in the second light emitting element (e.g. an emitting element of a color suitable for having a large emissive area, present in the DA1 second area portion of the device of Youn FIG. 15) is greater than a size of a third light emitting area defined in the third light emitting element (e.g. an emitting element of a color suitable for having a comparatively smaller emissive area, present in the edge of the DA1 intermediate area portion of the device of Youn FIG. 15), and the first size of the second light emitting area is greater than a size of a copy light emitting area defined in the copy light emitting element (e.g. an emitting element of a color suitable for having a comparatively smaller emissive area, present in the DA2 intermediate area portion of the device of Youn FIG. 15), to balance the luminous brightness for each color emitter so that the display uniformity of the display panel is improved, as was taught by Zhang.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of Cho and Nishioka as applied to claim 1 above, and further in view of US patent publication US 20140077163 A1 (Hack et al hereinafter Hack).
Youn in view of Cho and Nishioka discloses the limitations of claim 1 as detailed above, and Youn further discloses an intermediate pixel which comprises the third pixel circuit, the third light emitting element, and the copy light emitting element (FIGS. 10A and 15, first light emitting unit 300, first dummy light emitting unit 300’, and the pixel circuit in area DA1 that controls them define an intermediate pixel ¶ [0187-0189]). Youn also discloses a data driver (FIG. 3, data driver 1200 ¶ [0079]), but does not explicitly characterize it as a driving chip mounted on the display panel, the driving chip that stores a coordinate of an intermediate pixel and a brightness compensation value with respect to the intermediate pixel.
However, Hack teaches that in a display device (Title, Abstract, ¶ [0039-0040]), a compensation driver may be included in an external driver chip to improve display uniformity, and at the same time allow the sub-pixel area to remain relatively small while still obtaining the benefit of the driver (¶ [0040]); such functionality allows the driving chip to store a coordinate of an intermediate pixel and a brightness compensation value with respect to the intermediate pixel.
Youn, Cho, Nishioka, and Hack all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn in view of Cho and Nishioka further in view of Hack such that the data driver of Youn is implemented as a driving chip mounted on the display panel, the driving chip that stores a coordinate of an intermediate pixel and a brightness compensation value with respect to the intermediate pixel, in order to improve display uniformity, and at the same time allow the sub-pixel area to remain relatively small while still obtaining the benefit of the driver as taught by Hack.
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of Cho and Nishioka as applied to claim 1 above, and further in view of US patent publication US 20250374762 A1 (Cui et al hereinafter Cui).
Regarding claim 11, Youn in view of Cho and Nishioka discloses the limitations of claim 1 as detailed above, , but as currently considered they do not further disclose a first pixel unit disposed in the first area, an adjacent pixel unit disposed in the first area and disposed closest to the intermediate area, and a second pixel unit disposed in the second area and comprising a second-first sub-pixel unit and a second-second sub-pixel unit, the first pixel unit comprises a first red pixel, a first green pixel, and a first blue pixel, the second-first sub-pixel unit comprises a second red pixel and a second-first green pixel, and the second-second sub-pixel unit comprises a second-second green pixel and a second blue pixel, a particular layout of pixel and sub-pixel units having specific colors emitted not being a feature emphasized in the disclosure of Youn.
However, Cui discloses a display device (the device of FIG. 17 ¶ [0025]) which includes a first pixel unit (FIG. 17, a set of RGB sub-pixels along the left side of pixel removal region 332 ¶ [0133-0135]; sub-pixels are labeled according to the first-letter abbreviation per ¶ [0053]) disposed in a first area (FIG. 17, pixel removal region 332 ¶ [0132]), an adjacent pixel unit (FIG. 17, a set of RGB sub-pixels along the right side of pixel removal region 332 at the border of full pixel density region 334 ¶ [0133-0135]) disposed in the first area and disposed closest to an intermediate area (FIG. 17, an area in full pixel density region 334 directly bordering pixel removal region 332), and a second pixel unit (FIG. 17, a set of RGGB sub-pixels in full pixel density region 334, e.g. along the right end of region 334) disposed in a second area and comprising a second-first sub-pixel unit (FIG. 17, a red and green sub-pixel in an RGGB set e.g. along the right end of region 334) and a second-second sub-pixel unit (FIG. 17, a blue and green sub-pixel in the RGGB set along the right end of region 334), the first pixel unit comprises a first red pixel (FIG. 17, a red sub-pixel R along the left side of pixel removal region 332), a first green pixel (FIG. 17, a green sub-pixel G along the left side of pixel removal region 332), and a first blue pixel (FIG. 17, a blue sub-pixel B along the left side of pixel removal region 332), the second-first sub-pixel unit comprises a second red pixel (FIG. 17, the top rightmost red sub-pixel R) and a second-first green pixel (FIG. 17, the top rightmost green sub-pixel G), and the second-second sub-pixel unit comprises a second-second green pixel (FIG. 17, green sub-pixel G directly under the top rightmost green sub-pixel G) and a second blue pixel (FIG. 17, the top rightmost blue sub-pixel B). Cui also teaches that removing pixels from the pixel removal area allows light to transmit through, forming a transmission area, and by removing 50% of the red and blue sub-pixels and 75% of the green sub-pixels relative to the full pixel density region (¶ [0132]), the transmittance in the display area is improved by having fewer pixel elements present (¶ [0006]).
Youn, Cho, Nishioka, and Cui all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn in view of Cho and Nishioka further in view of Cui such that the device includes a first pixel unit disposed in the first area, an adjacent pixel unit disposed in the first area and disposed closest to the intermediate area, and a second pixel unit disposed in the second area and comprising a second-first sub-pixel unit and a second-second sub-pixel unit, the first pixel unit comprises a first red pixel, a first green pixel, and a first blue pixel, the second-first sub-pixel unit comprises a second red pixel and a second-first green pixel, and the second-second sub-pixel unit comprises a second-second green pixel and a second blue pixel, in order to improve the transmittance in the display area by having fewer pixel elements present.
Regarding claim 18, Youn in view of Cho, Nishioka, and Cui disclose the limitations of claim 11 as detailed above, and Youn further discloses that the circuit layer further comprises: a plurality of conductive layers (Youn FIG. 16, auxiliary storage capacitor Cst” has a plurality of conductive layers ¶ [0228]), a plurality of inorganic layers (FIG. 16, first gate insulating layer 111 and second gate insulating layer 113 are inorganic layers ¶ [0115, 0149]), and a plurality of organic layers (FIG. 16, segments of planarization layer 117 distributed through the device are a plurality of organic layers ¶ [0160]), the plurality of organic layers comprise a common organic layer (FIG. 16, the portion of planarization layer 117 near OLED’ and TA’) commonly disposed in the transmission area and the element area (annotated FIG. 16 below, the portion of planarization layer 117 is located in both the transmission and element areas), and a first thickness of the common organic layer in the transmission area is smaller than a second thickness of the common organic layer in the element area (annotated FIG. 16 below, the thickness of layer 117 in the transmission area is less than the thickness of layer 117 in the element area).
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Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of Cho, Nishioka, and Cui as applied to claim 11 above, and further in view of US patent publication US 20250017067 A1 (Hochman).
Regarding claim 12, Youn in view of Cho, Nishioka, and Cui disclose the limitations of claim 11 as detailed above, but as currently considered they do not further disclose that the adjacent pixel unit comprises an adjacent red pixel, an adjacent green pixel, and an adjacent blue pixel, wherein a width of a first red light emitting area defined in the first red pixel in a first direction is smaller than a width of a second red light emitting area defined in the adjacent red pixel in the first direction, a width of a first green light emitting area defined in the first green pixel in the first direction is smaller than a width of a second green light emitting area defined in the adjacent green pixel in the first direction, and a width of a first blue light emitting area defined in the first blue pixel in the first direction is smaller than a width of a second blue light emitting area defined in the adjacent blue pixel in the first direction.
However, Hochman discloses a display device (the device of FIG. 2 ¶ [0031]) wherein an adjacent pixel unit (FIG. 2, the upper left set of RGB sub-pixels) comprises an adjacent red pixel (FIG. 2, upper left red LED 110 ¶ [0031]), an adjacent green pixel (FIG. 2, upper left green LED 112 ¶ [0031]), and an adjacent blue pixel (FIG. 2, upper left blue LED 114 ¶ [0031]), wherein a width of a first red light emitting area (FIG. 2 illustrates an emitter structure of upper right red LED 110 having a narrow horizontal width) defined in the first red pixel in a first direction (FIG. 2, a horizontal direction) is smaller than a width of a second red light emitting area defined in the adjacent red pixel (FIG. 2, upper left red LED 110 has a wider horizontal width) in the first direction, a width of a first green light emitting area (FIG. 2 illustrates an emitter structure of upper right green LED 112 having a narrow horizontal width) defined in the first green pixel in the first direction is smaller than a width of a second green light emitting area defined in the adjacent green pixel (FIG. 2, upper left green LED 112 has a wider horizontal width) in the first direction, and a width of a first blue light emitting area (FIG. 2 illustrates an emitter structure of upper right blue LED 114 having a narrow horizontal width) defined in the first blue pixel in the first direction is smaller than a width of a second blue light emitting area defined in the adjacent blue pixel (FIG. 2, upper left blue LED 114 has a wider horizontal width) in the first direction. Hochman also teaches that the configuration of light emitting areas may distribute non-uniform color characteristics in less perceptible patterns when arranged in the orientation of FIG. 2 (¶ [0031]).
Youn, Cho, Nishioka, Cui, and Hochman all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn in view of Cho, Nishioka, and Cui further in view of Hochman such that the RGB subpixels of Youn in view of Cho, Nishioka, and Cui in the transmission area DA3 of Youn FIG. 15 are provided in the configuration shown in FIG. 2 of Hochman, such that the adjacent pixel unit comprises an adjacent red pixel, an adjacent green pixel, and an adjacent blue pixel, wherein a width of a first red light emitting area defined in the first red pixel in a first direction is smaller than a width of a second red light emitting area defined in the adjacent red pixel in the first direction, a width of a first green light emitting area defined in the first green pixel in the first direction is smaller than a width of a second green light emitting area defined in the adjacent green pixel in the first direction, and a width of a first blue light emitting area defined in the first blue pixel in the first direction is smaller than a width of a second blue light emitting area defined in the adjacent blue pixel in the first direction, in order to utilize a known configuration in the art that may distribute non-uniform color characteristics in less perceptible patterns.
Regarding claim 13, Youn in view of Cho, Nishioka, Cui, and Hochman disclose the limitations of claim 12 as detailed above, and they further disclose that a width of the first red light emitting area (Hochman FIG. 2, upper right red LED 110 having a wide vertical width) in a second direction (FIG. 2, a vertical direction, which intersects the horizontal) intersecting the first direction is greater than a width of the second red light emitting area (Hochman FIG. 2, upper left red LED 110 having a narrow vertical width) in the second direction, a width of the first green light emitting area (Hochman FIG. 2, upper right green LED 112 having a wide vertical width) in the second direction is greater than a width of the second green light emitting area (Hochman FIG. 2, upper left green LED 112 having a narrow vertical width) in the second direction, and a width of the first blue light emitting area (Hochman FIG. 2, upper right blue LED 114 having a wide vertical width) in the second direction is greater than a width of the second blue light emitting area (Hochman FIG. 2, upper left blue LED 114 having a narrow vertical width) in the second direction.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of Cho and Nishioka as applied to claim 1 above, and further in view of US patent publication US 20160133678 A1 (Beak et al hereinafter Beak).
Regarding claim 16, Youn in view of Cho and Nishioka discloses the limitations of claim 1 as detailed above, but they do not further disclose a barrier layer disposed between the base layer and the circuit layer, the barrier layer comprising: a first lower light blocking layer disposed in the first area, and a second lower light blocking layer disposed in the second area, the first lower light blocking layer and the second lower light blocking layer are disposed on a same layer, and the first lower light blocking layer and the second lower light blocking layer do not overlap the copy light emitting element.
However, Beak discloses a display device (the device of FIGS. 5-6 ¶ [0033-0034]) which includes a barrier layer (FIG. 6, buffer layer BUF and any elements formed within the buffer layer may be considered a barrier layer ¶ [0046]) disposed between a base layer (FIG. 6, substrate SUB ¶ [0045]) and a circuit layer (FIG. 6, interlevel insulating layer IN, passivation layer PAS, and the TFTs ST/DT within those layers form a circuit layer ¶ [0047-0048]), the barrier layer comprising: a first lower light blocking layer (FIG. 6, light shielding layer DLS is formed under driving thin film transistor DT ¶ [0042]) disposed in an area of each pixel circuit in the device (FIG. 5-6 illustrate a single OLED and pixel circuit, of which a device includes a plurality e.g. shown in FIGS. 16A-16B). Beak also teaches that the light blocking layers protect the channel structures from external light.
Youn, Cho, Nishioka, and Beak all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn, Cho, and Nishioka further in view of Beak to include the buffer layer and light-shielding layers at each pixel as shown in Beak, in order to protect the channel structures of the pixel circuit of Youn from external light. By doing so, the device of Youn in view of Cho, Nishioka, and Beak consequently includes a barrier layer disposed between the base layer and the circuit layer, the barrier layer comprising: a first lower light blocking layer disposed in the first area (light shielding layer DLS of Beak FIG. 6 placed in a first pixel circuit in the first area) and a second lower light blocking layer disposed in the second area (light shielding layer DLS of Beak FIG. 6 placed in a second pixel circuit in the second area), the first lower light blocking layer and the second lower light blocking layer are disposed on a same layer (Beak FIG. 6, all light blocking layers are provided on the substrate SUB), and the first lower light blocking layer and the second lower light blocking layer do not overlap the copy light emitting element (the copy light emitting element being provided in the third area while the first and second lower light blocking layers are provided in the first and second areas respectively, there is no overlap).
Regarding claim 17, Youn in view of Cho, Nishioka, and Beak disclose the limitations of claim 16 as detailed above, and they further disclose that the first lower light blocking layer and the second lower light blocking layer are electrically insulated from each other (Youn FIG. 15 in view of Beak FIG. 6, the light shielding layers DLS of Beak are provided separately for each sub-pixel, and therefore are electrically insulated from each other), and the first lower light blocking layer and the second lower light blocking layer are configured to receive different voltages from each other (Beak ¶ [0042], in the configuration wherein the light shielding layers DLS are connected to gate electrode of the driving transistor to form double-gates, the first and second lower light blocking layers receive different voltages from each other since each of their respective gates receive different voltages).
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of Beak.
Regarding claim 20, Youn discloses an electronic device comprising: a display panel (the display panel of FIG. 15 ¶ [0220-0226], which includes the structure of FIG. 11 ¶ [0226, 0192-0203]) comprising a first area (FIG. 15, third display area DA3 ¶ [0221]) comprising a transmission area (FIG. 15, transmitting unit TA’ ¶ [0223]) and an element area (FIG. 15, auxiliary pixel Pa ¶ [0223]), a second area (FIG. 15, first display area DA1 [excluding an inner portion which includes light emitting units 200/300 which are connected to dummy light emitting units 200’/300’] is spaced apart from area DA3 ¶ [0221]) spaced apart from the first area, and an intermediate area (FIG. 15, second display area DA2 and the inner portion of area DA1 which includes units 200/300 which are connected to dummy units 200’/300’ ¶ [0221]) disposed between the first area and the second area, the display panel comprising: a base layer (FIG. 10A, substrate 100 ¶ [0078]; FIG. 10A’s structure is included in FIG. 11 ¶ [0194]);
a circuit layer (FIGS. 10A and 16, layers 111, 117, and circuit elements within and between those layers form a circuit layer; FIG. 16 illustrates a cross section of DA3 shown in FIG. 15 ¶ [0227]) comprising: a first pixel circuit (FIG. 16, auxiliary TFT” is part of a first pixel circuit in DA3 ¶ [0228]) disposed in the first area and comprising a first driving transistor (FIG. 16, auxiliary TFT” is a transistor that drives auxiliary OLED’ ¶ [0228]), a second pixel circuit (FIG. 15, unlabeled pixels unconnected to dummy pixels and having pixel circuits are shown in area DA1, e.g. pixel circuit PC2 of FIG. 6 ¶ [0138, 0221]) disposed in the second area and comprising a second driving transistor (FIG. 6, pixel circuit PC2 includes a driving transistor, as regardless of which pixel circuit structure taught in FIGS. 4A and 4B is used in a given embodiment, both have driving TFT T1 to drive the pixel ¶ [0081 ,0088]), and a third pixel circuit (FIGS. 10A and 15, TFT1 at edge of DA1 is in the intermediate area) disposed in the intermediate area and comprising a third driving transistor (FIG. 10A, TFT1 is a driving transistor ¶ [0081, 0137]);
an element layer (FIG. 10A, layer 119 and elements disposed around it are above the circuit layer) disposed on the circuit layer, the element layer comprising: a first light emitting element (FIG. 16, auxiliary OLED’ is electrically connected to auxiliary TFT” ¶ [0228]) electrically connected to the first pixel circuit, a second light emitting element (FIG. 15, unlabeled pixels unconnected to dummy pixels and having light emitting elements are shown in area DA1, e.g. pixel circuit PC2 of FIG. 6 ¶ [0138, 0221], and electrically connected to an OLED, regardless of whether the pixel circuit structure of FIG. 4A or FIG. 4B is employed ¶ [0081, 0086]) electrically connected to the second pixel circuit, a third light emitting element (FIG. 10A, first light emitting unit 300 is electrically connected to TFT1 ¶ [0189]) electrically connected to the third pixel circuit, and a copy light emitting element (FIG. 10A, first dummy light emitting unit 300’ is electrically connected to TFT1 ¶ [0187]) electrically connected to the third pixel circuit.
Youn did not explicitly show an encapsulation layer disposed on the element layer in the embodiment under consideration, and Youn does not further disclose a barrier layer disposed on the base layer, the barrier layer comprising: a first lower light blocking layer disposed in the first area, and a second lower light blocking layer disposed in the second area, the first lower light blocking layer and the second lower light blocking layer disposed on a same layer, the circuit layer being disposed on the barrier layer, wherein the first lower light blocking layer and the second lower light blocking layer do not overlap the copy light emitting element.
Regarding the limitation “an encapsulation layer disposed on the element layer”, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to include such an encapsulation layer in view of the embodiment of FIG. 14 of Youn, which shows an encapsulation layer (FIG. 14, thin film encapsulation 600 ¶ [0215-0216]) disposed on the element layer. Youn also teaches that the encapsulation protects the OLED from damage due to moisture or oxygen exposure (¶ [0216]), so a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to include an encapsulation layer disposed on the element layer as is demonstrated in the embodiment of FIG. 14 of Youn, in order to protect the OLED against external contaminants.
Regarding the “barrier layer” limitations, Beak discloses a display device (the device of FIGS. 5-6 ¶ [0033-0034]) which includes a barrier layer (FIG. 6, buffer layer BUF and any elements formed within the buffer layer may be considered a barrier layer ¶ [0046]) disposed on a base layer (FIG. 6, substrate SUB ¶ [0045]) and a circuit layer (FIG. 6, interlevel insulating layer IN, passivation layer PAS, and the TFTs ST/DT within those layers form a circuit layer ¶ [0047-0048]) disposed on the barrier layer, the barrier layer comprising: a first lower light blocking layer (FIG. 6, light shielding layer DLS is formed under driving thin film transistor DT ¶ [0042]) disposed in an area of each pixel circuit in the device (FIG. 5-6 illustrate a single OLED and pixel circuit, of which a device includes a plurality e.g. shown in FIGS. 16A-16B). Beak also teaches that the light blocking layers protect the channel structures from external light.
Youn and Beak both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn in view of Beak to include the buffer layer and light-shielding layers at each pixel as shown in Beak, in order to protect the channel structures of the pixel circuit of Youn from external light. By doing so, the device of Youn in view of Beak consequently includes a barrier layer disposed on the base layer the circuit layer disposed on the barrier layer, the barrier layer comprising: a first lower light blocking layer disposed in the first area (light shielding layer DLS of Beak FIG. 6 placed in a first pixel circuit in the first area) and a second lower light blocking layer disposed in the second area (light shielding layer DLS of Beak FIG. 6 placed in a second pixel circuit in the second area), the first lower light blocking layer and the second lower light blocking layer are disposed on a same layer (Beak FIG. 6, all light blocking layers are provided on the substrate SUB), and the first lower light blocking layer and the second lower light blocking layer do not overlap the copy light emitting element (the copy light emitting element being provided in the third area while the first and second lower light blocking layers are provided in the first and second areas respectively, there is no overlap).
Regarding claim 21, Youn in view of Beak discloses the limitations of claim 20 as detailed above, and they further disclose that the first pixel circuit entirely overlaps the first lower light blocking layer (Beak FIG. 6, light shielding layer DLS is fully overlapped by the driving transistor of a given pixel circuit, including the first pixel circuit of Youn FIG. 16, auxiliary TFT”), a portion of the second pixel circuit overlaps the second lower light blocking layer (Beak FIG. 6, light shielding layer DLS is fully overlapped by the driving transistor of a given pixel circuit, including the second pixel circuit of Youn), and another portion of the second pixel circuit does not overlap the second lower light blocking layer (Youn FIGS. 4A and 4B both show that Youn’s disclosed pixel circuits include more than one transistor, any of which that are not the driving transistor of the pixel circuit would not overlap the light shielding layer DLS of Beak FIG. 6).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of Beak as applied to claim 20 above, and further in view of Hack.
Youn in view of Beak discloses the limitations of claim 20 as detailed above, and Youn further discloses an intermediate pixel which comprises the third pixel circuit, the third light emitting element, and the copy light emitting element (FIGS. 10A and 15, first light emitting unit 300, first dummy light emitting unit 300’, and the pixel circuit in area DA1 that controls them define an intermediate pixel ¶ [0187-0189]). Youn also discloses a data driver (FIG. 3, data driver 1200 ¶ [0079]), but does not explicitly characterize it as a driving chip mounted on the display panel, the driving chip that stores a coordinate of an intermediate pixel and a brightness compensation value with respect to the intermediate pixel are stored in the driving chip.
However, Hack teaches that in a display device (Title, Abstract, ¶ [0039-0040]), a compensation driver may be included in an external driver chip to improve display uniformity, and at the same time allow the sub-pixel area to remain relatively small while still obtaining the benefit of the driver (¶ [0040]); such functionality allows the driving chip to store a coordinate of an intermediate pixel and a brightness compensation value with respect to the intermediate pixel.
Youn, Beak, and Hack all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn in view of Beak further in view of Hack such that the data driver of Youn is implemented as a driving chip mounted on the display panel, the driving chip that stores a coordinate of an intermediate pixel and a brightness compensation value with respect to the intermediate pixel, in order to improve display uniformity, and at the same time allow the sub-pixel area to remain relatively small while still obtaining the benefit of the driver as taught by Hack.
Claims 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of Beak as applied to claim 20 above, and further in view of Cho.
Regarding claim 23, Youn in view of Beak discloses the limitations of claim 20 as detailed above, and Youn further discloses a plurality of first pixels (FIG. 15, auxiliary pixels Pa are first color pixels in the element area ¶ [0223]; the pixels emit colored light through their respective OLEDs ¶ [0081]) disposed in the element area and comprising first color pixels, a plurality of second pixels (FIG. 15, the pixels in area DA1 that are unlabeled and not connected to dummy pixels in area DA2 are second color pixels, i.e. the pixel shown in FIG. 9 having circuit PC2 and emission unit 200 ¶ [0132]) disposed in the second area and comprising second color pixels, and a plurality of third pixels (FIG. 15, light emitting units 200 and 300 that connect to dummy light emitting units 200’ and 300’ and the dummy light emitting units 200’ and 300’ form third color pixels in the intermediate area portion of area DA1) disposed in the intermediate area and comprising third color pixels, each of the plurality of first pixels comprises the first pixel circuit and the first light emitting element (FIGS. 15-16, auxiliary pixels Pa include auxiliary TFT” and auxiliary OLED’ ¶ [0228]), each of the plurality of second pixels comprises the second pixel circuit and the second light emitting element (FIG. 15, the pixels in area DA1 that are unlabeled and not connected to dummy pixels in area DA2 include pixel circuit PC2 and emitting element 200 as can be seen in FIG. 9 ¶ [0132]), each of the plurality of third pixels comprises the third pixel circuit, the third light emitting element, and the copy light emitting element (FIGS. 10A and 15, third pixels include light emitting unit 300, dummy light emitting unit 300’, and transistor TFT1 included in a third pixel circuit).
Youn did not explicitly teach that a pixel density of the plurality of first pixels is smaller than a pixel density of the plurality of second pixels, a comparison of pixel densities not being a parameter emphasized in their disclosure.
However, Cho taught that in different regions of the display device (specifically a camera-region and non-camera region ¶ [0058-0059]), the pixels area arranged at different resolutions, and have different pixel densities such that a pixel density of the plurality of first pixels (pixels in the first region A ¶ [0059]) is smaller than a pixel density of the plurality of second pixels (pixels in the second region B ¶ [0059]), and also teaches that this configuration allows the first region with lower pixel density to have higher light transmission (¶ [0061]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn in view of Cho such that a pixel density of the plurality of first pixels is smaller than a pixel density of the plurality of second pixels, in order to provide increased light transmission in the transmission region of Youn.
Youn, Beak, and Cho all pertain to the field of display devices. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Youn in view of Beak further in view of Cho such that a pixel density of the plurality of first pixels is smaller than a pixel density of the plurality of second pixels, in order to provide increased light transmission in the transmission region of Youn as was taught by Cho.
Regarding claim 24, Youn in view of Beak and Cho discloses the limitations of claim 23 as detailed above, and Youn further discloses that a number of the second color pixels disposed in a reference area among the plurality of second pixels is X times of a number of the first color pixels disposed in the reference area among the plurality of first pixels, where X is a natural number equal to or greater than 2 (annotated FIG. 15 reproduced below, a reference area may be drawn up near the border of area DA3 wherein at least twice as many second color pixels are present compared to the number of first color pixels).
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Regarding claim 25, Youn in view of Beak and Cho discloses the limitations of claim 24 as detailed above, and Youn further discloses that a sum of sizes of light emitting areas included in each of the third color pixels is greater than a size of a light emitting area included in each of the second color pixels (FIG. 15, since the third color pixels include both the emissive areas of 200/300 and 200’/300’, they have larger emissive areas than the unlabeled second color pixels in area DA1; see also MPEP 2125 I), and the first color pixels, the second color pixels, and the third color pixels are configured to emit lights having a same color (the pixels may emit red, green, blue, or white light ¶ [0081, 0165]; the plurality of pixels emit light of those same colors).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20240005855 A1 and US 20210057494 A1.
Conclusion
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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