DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1 in the reply filed on 11/4/25 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites (emphasis added for clarification):
3. The semiconductor package of claim 2, wherein the first chip has a first contact gate or wiring pitch equal to about 10 nm or less, and the second chip has a second contact gate or wiring pitch greater than the first contact gate or wiring pitch and equal to about 3 nm to about 50 nm.
Applicant’s claim language recites that the second pitch is “greater than” the first but then includes a range for the second pitch which includes values less than the first? The claim is confusing and indefinite and precludes examination on the merits because one of ordinary skill in the art would not be able to clearly understand the metes and bounds of the claim. Appropriate corrections are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 11-12 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yu et al (US 2021/0407942).
1. A semiconductor package, comprising:
a first chip (Fig.19A-B (75) and [0060]) comprising a first semiconductor substrate (Fig.19A-B (72) and [0060]) comprising a first through via (Fig.19A-B (82) and [0061]), a semiconductor element (Fig.19A-B (73) and [0061 and see also 0036]) positioned on a front surface of the first semiconductor substrate (Fig.19A-B (72) and [0060]), and
a back side wiring layer (Fig.19A-B (100A and 100B) and [0061 and see also 0046]) comprising a back side power wiring (Fig.19A-B (100A and 100B) and [0061 and see also 0046]) positioned on a rear surface of the first semiconductor substrate (Fig.19A-B (72) and [0060]) and electrically connected to the semiconductor element (Fig.19A-B (73) and [0061 and see also 0036]); and
a second chip (Fig.19B (215) and [0062-0063]) bonded to and electrically connected to a front surface of the first chip (Fig.19A-B (75) and [0060]), and comprising a second through via (Fig.19B (282) and [ 0062]) having a size greater than a size of the first through via (Fig.19A-B (82) and [0061]).
2. The semiconductor package of claim 1, wherein the first chip (Fig.19A-B (75) and [0060]) has a finer wiring structure or finer pattern [0061-pitches] than the second chip (Fig.19B (215) and [0062-0063]).
11. The semiconductor package of claim 1, wherein the first chip further comprises a buried wiring (Fig.19B (82) and [0035]) electrically connecting a first transistor of the semiconductor element (Fig.19A-B (73) and [0061 and see also 0036]) with the back side power wiring (Fig.19A-B (100A and 100B) and [0061 and see also 0046]).
12. The semiconductor package of claim 11, wherein the buried wiring (Fig.19B (82) and [0035]) extends from a back side of the first transistor (Fig.19A-B (73) and [0061 and see also 0036]) to the back side power wiring (Fig.19A-B (100A and 100B) and [0061 and see also 0046]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 2021/0407942).as applied to claims 1-2 above, and further in view of Eisherbini et al (US 20210098407).
Yu teaches the limitations of claims 1-2 above, however fails to explicitly teach the limitations of claim 3 below:
3. The semiconductor package of claim 2, wherein the first chip has a first contact gate or wiring pitch equal to about 10 nm or less, and the second chip has a second contact gate or wiring pitch equal to about 3 nm to about 50 nm. {for examination purposes-this modification of the original claim language constitutes the Examiner’s best guess at understanding the intended claim meaning}.
Eisherbini teaches a first contact gate or wiring pitch equal to about 10 nm or less, and a second contact gate or wiring pitch equal to about 3 nm to about 50 nm [0063].
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Yu’s teachings to include the pitches as low as 1-10 nm and as high as 10-500 nm) because as Eisherbini teaches, such pitches are possible and suitable for gate wirings [0063].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cho et al (US 2021/0305130); Henderson et al (US 2014/0225246) and Batra et al (US 9536809) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
1/22/26
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