Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed February 12, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 8, 15, 18
b. Pending: 1, 3, 5-8, 10, and 12-20
Claims 1, 3, 5, 8, 10, and 12 have been amended, and claims 2, 4, 9, and 11 have been canceled.
Drawings
The objection to Fig. 3B has been withdrawn pursuant to the Replacement Sheet filed February 12, 2026.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3, 5-8, 10, and 12-14 have been considered but are moot because the new ground of rejection relies on newly found references along with previously used references applied in the prior rejection of record.
Applicant’s arguments, see page 10, filed February 12, 2026, with respect to the rejection of previously pending claims 4 and 11 under 35 U.S.C. 102(a)(1) and 102(a)(2) and 35 U.S.C. 103, respectively, have been fully considered and are persuasive. Claims 4 and 11 have been incorporated into independent claims 1 and 8, respectively. Upon further consideration, new grounds of rejection for these limitations are made in view of Hirabayashi (US Pub. 20090279377 A1) and Vinal (WO 9406120 A1). Hirabayashi paras. [0025] and Fig. 1 are relevant to claim 1; and Vinal page 22 and Fig. 1 are relevant to claim 8.
Applicant's arguments filed February 12, 2026 regarding claims 18-20 have been fully considered but they are not persuasive. On pages 8 and 11, the Applicant argues that Li-2 does not disclose an inverter, but rather discloses “a transmission gate driven by complementary signals (X and XB).” Examiner notes that Fig. 5C of Li-2 does not include complementary input signal XB. Both transistors 534 and 538 receive the same input. Applicant also argues on page 8 regarding the definition of an inverter. Transistors 534 and 538 indeed exhibit inverter functionality. When BL is low and BLB is high, 534 and 538 function as an inverter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15-17 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being
anticipated by Li et al. (US Pub. 20210134343 A1; “Li-2”).
Regarding independent claim 15, Li-2 discloses an apparatus (Fig. 4: computation system 400; [0050]) comprising:
a static random access memory (SRAM) cell (Fig. 5C: memory cell 500 of the SRAM 408; [0052]) comprising a first inverter (PMOS transistor 520 and NMOS transistor 522) and a second inverter (PMOS transistor 526 and NMOS transistor 524); and
a third inverter comprising a first inverter transistor (PMOS transistor 538; [0055]) and a second inverter transistor (NMOS transistor 534; [0055]),
wherein an output terminal of the second inverter is connected to a source terminal of the first inverter transistor (output terminal of the inverter formed by PMOS transistor 526 and NMOS transistor 524 is connected to the source terminal of PMOS transistor 538), and an output terminal of the first inverter is connected to a source terminal of the second inverter transistor (output terminal of the inverter formed by PMOS transistor 520 and NMOS transistor 522 is connected to the source terminal of NMOS transistor 534).
Regarding claim 16, Li-2 discloses the limitations of claim 15, and further:
wherein the apparatus (Fig. 4: 400) is configured to perform an operation between input data (Fig. 5C: input data X; [0051]. See rejection of claim 1 below) input through an input terminal of the third inverter (X is provided to the input of PMOS transistor 538 and NMOS transistor 534) and output data of the second inverter (bit line BLB 512) and output a result of the operation through an output terminal of the third inverter (node 550; [0056]).
Regarding claim 17, Li-2 discloses the limitations of claim 16, and further:
wherein the result of the operation comprises an XOR operation result between the input data and the output data of the second inverter ([0052]: FIG. 5E illustrates a truth table 501 corresponding to the memory cell 500…While the truth table 501 corresponds to an XNOR operation, any of various logical operations may be performed using the techniques described herein. XNOR operation is the logical complement of XOR operation, which may be used for binary multiply computation for convolution; [0059]: the logic state at the output node 570 may be logic high, representing an XNOR operation of the input X (logic high) and the BLB (e.g., logic low), or an XOR operation of the input X (logic high) and the BL (e.g., logic high)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Li-2 (US Pub. 20210134343 A1) in view of Hirabayashi (US Pub. 20090279377 A1).
Regarding independent claim 1, Li-2 discloses an apparatus (Fig. 4: computation system 400; [0050]), comprising:
a static random access memory (SRAM) cell (Fig. 5C: memory cell 500 of the SRAM 408; [0052]) comprising a first inverter (PMOS transistor 526 and the NMOS transistor 524; [0054]) and a second inverter (PMOS transistor 520 and the NMOS transistor 522; [0054]);
a third inverter (NMOS transistor 534 and the PMOS transistor 538; [0056]) comprising a first inverter transistor (NMOS transistor 534) and a second inverter transistor (PMOS transistor 538),
wherein an output terminal of the first inverter is connected to a source terminal of the second inverter transistor (in reference to Fig. 5C, the output of the first inverter is connected to pass gate transistor 508, which is connected to the source of PMOS transistor 538. See annotated image below), and
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wherein the apparatus (Fig. 4: 400) is configured to perform an operation between input data ([0051]: input data, labeled “X” in FIG. 4, may be input to registers 402. The input data may be provided to word lines of the SRAM 408 via digital-to-analog converters (DACs) 404. The SRAM 408 may perform in-memory convolution computation based on the input data and as a function of weights (W.sub.i) stored in the memory cells of the SRAM 408; per [0052], Figs. 4 and 5 correspond to the same system) input through an input terminal of the third inverter ([0056]: input X 540 (also referred to as a “computation input node”)) and output data of the second inverter and output a result of the operation through an output terminal of the third inverter ([0057]: During a computation process, the weight stored in the FF 514 may be read by turning on pass gate transistors 506, 508 via the WL 502 such that the voltages at the BL 510 and the BLB 512 are set to respective voltages at the output and complementary output nodes N1, N2. When the input X 540 is logic high, the transmission gate 532 is turned on, and the transmission gate 533 is turned off. Therefore, the logic state at node 550 may be set to the logic state of the BL 510. When the input X 540 is logic low, the transmission gate 532 is turned off, and the transmission gate 533 is turned on. Therefore, the logic state at node 550 may be set to the logic state of the BLB 512), and
Li-2 does not disclose:
a pull-down transistor;
wherein a gate terminal of the pull-down transistor is connected to an output terminal of the second inverter.
However, Hirabayashi teaches:
a pull-down transistor (Fig. 1: NMOS transistor N6; [0025]);
wherein a gate terminal of the pull-down transistor is connected to an output terminal of the second inverter (per Fig. 1, the gate terminal of N6 is connected to the output terminal of the second inverter IV2).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hirabayashi to Li-2 wherein an apparatus comprises a pull-down transistor; wherein a gate terminal of the pull-down transistor is connected to an output terminal of the second inverter in order to reduce disturbances by separating the read and write ports (Hirabayashi, [0005]-[0006]).
Regarding claim 3, Li-2 and Hirabayashi together disclose the limitations of claim 1, and further through Li-2:
wherein the result of the operation comprises a NOR operation result between the input data input through the input terminal of the third inverter and the output data of the second inverter ([0052]: FIG. 5E illustrates a truth table 501 corresponding to the memory cell 500 and the BNN periphery circuit 530, in accordance with certain aspects of the present disclosure...While the truth table 501 corresponds to an XNOR operation, any of various logical operations may be performed using the techniques described herein. Examiner asserts that a person with ordinary skill in the art would know that to convert an XNOR operation to a NOR operation, they must simply add another inverter to the circuit).
Regarding claim 6, Li-2 and Hirabayashi together disclose the limitations of claim 1, and further through Li-2:
wherein the apparatus (Fig. 4: 400) is configured to perform an operation between inverse input data input through an input terminal of the third inverter and output data of the first inverter and output a result of the operation through an output terminal of the third inverter ([0057]: When the input X 540 is logic low, the transmission gate 532 is turned off, and the transmission gate 533 is turned on. Therefore, the logic state at node 550 may be set to the logic state of the BLB 512; [0056]: the NMOS transistor 541 may have gates controlled by the complementary input XB 542 (also referred to as a “complementary computation input node”). Examiner concludes that Fig. 5A may produce an operation result corresponding to inverse input data XB and the output of the first inverter, which is connected to BLB).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Li-2 (US Pub. 20210134343 A1) and Hirabayashi (US Pub. 20090279377 A1) as applied to claim 1 above, and further in view of Wu et al. (CN 102034533 B; “Wu”).
Regarding claim 5, Li-2 and Hirabayashi together disclose the limitations of claim 1.
Further, through Hirabayashi:
wherein the pull-down transistor is an NMOS transistor (Fig. 1: N6; [0025]), and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hirabayashi to modified Li-2 wherein the pull-down transistor is an NMOS transistor in order to reduce disturbances by separating the read and write ports (Hirabayashi, [0005]-[0006]).
Neither Li-2 nor Hirabayashi disclose:
wherein an output terminal of the third inverter is connected to a drain terminal of the pull-down transistor.
However, Wu teaches:
wherein an output terminal of the third inverter (per Fig. 2, the terminal between PMOS 115 and NMOS 110 is an output terminal of an inverter) is connected to a drain terminal of the pull-down transistor (per Fig. 2, the drain of NMOS 130 is connected to the output of the PMOS 115 and NMOS 11 ).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Wu to modified Li-2 wherein the pull-down transistor is an NMOS transistor, and wherein an output terminal of the third inverter is connected to a drain terminal of the pull-down transistor in order to implement an SRAM with a reset function for preventing latching of an unwanted random value before a write operation (Wu, [0003]-[0005]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Li-2 (US Pub. 20210134343 A1) and Hirabayashi (US Pub. 20090279377 A1) as applied to claim 6 above, and further in view of Li et al. (US Pub. 20210279036 A1; “Li-3”).
Regarding claim 7, Li-2 and Hirabayashi together disclose the limitations of claim 6, and further through Li-2:
wherein the result of the operation comprises an AND operation result between input data corresponding to the inverse input data and the output data of the first inverter ([0057]: When the input X 540 is logic low, the transmission gate 532 is turned off, and the transmission gate 533 is turned on. Therefore, the logic state at node 550 may be set to the logic state of the BLB 512; [0056]: the NMOS transistor 541 may have gates controlled by the complementary input XB 542 (also referred to as a “complementary computation input node”). Examiner concludes that Fig. 5A may produce an operation result corresponding to inverse input data XB and the output of the first inverter, which is connected to BLB).
Neither Li-2 nor Hirabayashi discloses:
wherein the result of the operation comprises an AND operation
However, Li-3 teaches:
wherein the result of the operation comprises an AND operation (in reference to Fig. 10, per [0072]: At block 1006, the circuitry computes a logical operation (e.g., AND operation) of the first computation parameter and the second computation parameter via the computation circuit coupled to the bit-line or the complementary bit-line)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Li-3 to modified Li-2 wherein the result of the operation comprises an AND operation in order to increase the speed of MAC computations while consuming less energy (Lin-3, [0052]).
Claims 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li-2 (US Pub. 20210134343 A1) in view of Vinal (WO 9406120 A1).
Independent claim 8 contains a first, second, fourth, and fifth limitation that are nearly identical in claimed subject matter as the first, second, third, and fifth limitations of claim 1 except the fourth limitation of claim 8 recites “a source terminal of the first inverter transistor” instead of “a source terminal of the second inverter transistor”, and the fifth recites “output data of the first inverter” instead of “output data of the second inverter”. Since claim 8 is independent, the names of the first and second inverter transistors of claim 1 may be reversed for claim 8. Thus the first, second, fourth, and fifth limitations of independent claim 8 are rejected for the same reasons as the corresponding limitations of independent claim 1 using Li-2.
Li-2 does not disclose:
a pull-up transistor,
wherein a gate terminal of the pull-up transistor is connected to an output terminal of the first inverter.
However, Vinal teaches:
a pull-up transistor (Fig. 1: pull up transistor 26’),
wherein a gate terminal of the pull-up transistor is connected to an output terminal of the first inverter (page 22, lines 14-20: As shown, pull-up circuit transistors 26, 26' are connected between power supply 14 and the respective output 13, 13' of skewed inverter 11, 11'. The gates of pull up transistors 26, 26' are cross-coupled to the respective output 13, 13' of the skewed inverter 11, 11'.).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Vinal to modified Li-2 wherein an apparatus comprises a pull-up transistor, wherein a gate terminal of the pull-up transistor is connected to an output terminal of the first inverter in order to increase the latch-up speed by using pull-up transistors (Vinal, p. 26, line 26 – p.27, line 7).
Regarding claim 13, Li-2 and Vinal together disclose the limitations of claim 8. Claim 13 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Li-2 (US Pub. 20210134343 A1) and Vinal (WO 9406120 A1) as applied to claim 8 above, and further in view of Li-3 (US Pub. 20210279036 A1).
Regarding claim 10, Li-2 and Vinal together disclose the limitations of claim 8, and further through Li-2:
operation result between the input data and the output data of the first inverter ([0057]; [0056]).
Neither Li-2 nor Vinal discloses:
wherein the result of the operation comprises a NAND operation result
However, Li-3 teaches:
wherein the result of the operation comprises a NAND operation ([0072]. Examiner takes official notice that a person with ordinary skill in the art would know to add an inverter to the computation circuit of Li-3 in order to change the logical operation from AND to NAND)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Li-3 to modified Li-2 wherein the result of the operation comprises a NAND operation in order to increase the speed of MAC computations while consuming less energy (Lin-3, [0052]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Li-2 (US Pub. 20210134343 A1) and Vinal (WO 9406120 A1) as applied to claim 8 above, and further in view of Wu (CN 102034533 B).
Regarding claim 12, Li-2 and Vinal together disclose the limitations of claim 8. Further, through Vinal:
wherein the pull-up transistor is a PMOS transistor (Fig. 1: 26’ is labeled “P5”, the other PMOS transistors are labeled with a ‘P’, and the NMOS transistors are labeled with an ‘N’), and
wherein an output terminal of the third inverter (output 13’ of the skewed inverter 11’) is connected to a drain terminal of the pull-up transistor (per Fig. 1, 13’ is connected to the drain terminal of 26’).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Vinal to modified Li-2 wherein the pull-up transistor is a PMOS transistor, and wherein an output terminal of the third inverter is connected to a drain terminal of the pull-up transistor in order to increase the latch-up speed by using pull-up transistors (Vinal, p. 26, line 26 – p.27, line 7).
Also, Wu teaches:
wherein the pull-up transistor is a PMOS transistor (Fig. 1: reset pull-up PMOS transistor 135; [0043]), and
wherein an output terminal of the third inverter (the node in between the second drive NMOS transistor 120 and the second load PMOS transistor 125 is the output of the second inverter 12) is connected to a drain terminal of the pull-up transistor (per Fig. 2, the aforementioned node is connected to the drain terminal of the reset pull-up PMOS transistor 135).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Wu to modified Li-2 wherein the pull-up transistor is a PMOS transistor, and wherein an output terminal of the third inverter is connected to a drain terminal of the pull-up transistor in order to implement an SRAM with a reset function for preventing latching of an unwanted random value before a write operation (Wu, [0003]-[0005]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Li-2 (US Pub. 20210134343 A1), Vinal (WO 9406120 A1), and Hirabayashi (US Pub. 20090279377 A1) as applied to claim 13 above, and further in view of Ferrera et al. (US Pub. 20230170012 A1; “Ferrera”).
Regarding claim 14, Li-2, Vinal, and Hirabayashi together disclose all the limitations of claim 13. Li-2 discloses input data corresponding to the inverse input data and the output data of the first inverter.
Neither Li-2, Vinal, nor Hirabayashi explicitly discloses:
wherein the result of the operation comprises an OR operation result between input data corresponding to the inverse input data and the output data of the first inverter.
However, Ferrera teaches:
wherein the result of the operation comprises an OR operation result (referring to operations that can be implemented with a 6T SRAM cell, [0137]-[0138] teaches an OR operation; also see logic operation ‘OR’ in Fig. 18A; the memory cell referenced is Fig. 3: memory cell MC1; [0071] & [0075]) between input data corresponding to the inverse input data ([0181]: the write driver is to pass a bit … and to pass an inverse of the bit passed to the first write data path to the second write data path, based on one or more control signals) and the output data of the first inverter (pull-up pMOSFETs T6 and pull-down nMOSFETs T8; [0076]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ferrera to modified Li-2 wherein the result of the operation comprises an OR operation result between input data corresponding to the inverse input data and the output data of the first inverter in order to perform logic operations within the SRAM device and output a more robust logic operation result via a sense amp (Ferrera, [0059]).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Li-2 (US Pub. 20210134343 A1) in view of Chen et al. (US Pub. 20200005859 A1; “Chen”).
Independent claim 18 contains a first limitation that is substantially the same as the fifth limitation of claim 1 and a second limitation that is substantially the same as claim 6 except the limitations of claim 18 are written in method format instead of device format. These limitations are thus individually rejected for the same reasons using Li-2.
Li-2 does not disclose:
A method, comprising:
Performing a first operation; and
Performing a second operation
However, Chen teaches:
A method ([0142]: FIG. 6 is a flowchart of a method 600 of performing an in-memory computation), comprising:
Performing a first operation (Fig. 6: operation 650; [0155]: At operation 650, in some embodiments, a logic operation is performed on each combination of the latched first data bit and each second data bit of the plurality of second data bits.); and
Performing a second operation (operation 660; [0157]: At operation 660, in some embodiments, one or more or all of operations 630 through 650 are repeated. In some embodiments, repeating one or more or all of operations 630 through 650 includes latching a third data bit from the first column of memory cells, sequentially reading the plurality of second data bits from the second column of memory cells, and performing the logic operation on each combination of the latched third data bit and each second data bit of the plurality of second data bits; alternatively, Chen teaches that operation 650 may itself include multiple logic operations: [0155]: In various embodiments, performing the logic operation includes one or more of performing an OR, NOR, XOR, AND, NAND, or multiplication operation, or one or more other operations suitable for processing at least two data bits)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chen to modified Li-2 wherein a method comprises performing a first operation and performing a second operation in order to reduce power and simplify circuitry through a reduction in bus lengths and the amount of buffers (Chen, [0051]).
Regarding claim 19, Li-2 and Chen together disclose the limitations of claim 18. Claim 19 recites substantially the same limitations as claim 3, and henceforth is rejected for the same reasons.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Li-2 (US Pub. 20210134343 A1) in view of Chen (US Pub. 20200005859 A1) as applied to claim 18 above, and further in view of Li-3 (US Pub. 20210279036 A1).
Regarding claim 20, Li-2 and Chen together disclose the limitations of claim 18. Claim 20 recites substantially the same limitations as claim 7, and henceforth is rejected for the same reasons.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
/E.R.A./Examiner, Art Unit 2824
4/1/2026