DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-3, 7-12 are pending in the application and are currently being examined. Claims 4-6 and 13-20 have been withdrawn per the 4/30/2026 restriction election (see below).
Election/Restrictions
Claim 4-6 and 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II and, there being no allowable generic or linking claim. Election was made without traverse (see below) in the reply filed on 4/30/2026.
After further consideration, Examiner disagrees with the Applicant stating claim 4 is generic to all subspecies, but Examiner agrees that claims 1-3 and 11-12 are generic. Claim 4 reads on subspecies B2 and not the elected subspecies B1. In Applicant’s specification, in the description for Figs. 29A and 30A it states “In this case, the etch stop semiconductor material layers (180, 280) can be electrically isolated from each of the electrically conductive layers (146, 246, 346)” [0240]; while the description for Figs. 29B and 30B states “Further, the first etch stop conductive material layer 182(/180) can be electrically connected to the bottommost second electrically conductive layer 246, and the second etch stop conductive material layer 282(/180) can be electrically connected to the bottommost third electrically conductive layer 346” [0241(/0242)]. For this reason, claim 4 is withdrawn from examination. Claim 6 is also withdrawn from examination for being dependent upon withdrawn claim 4.
Examiner also wants to mention that Applicant elected claim 9 in the response as it is drawn to subspecies B2, however claim 9 was not listed in the final elected claims. For this reason, claim 9 is NOT withdrawn and will be examined on the merits.
Therefore, the claims being examined are 1-3 and 7-12. This decision is FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/11/2023, 10/5/2023, 1/25/2024, 2/21/2024, 5/6/2025, 10/1/2025 is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: element 180 is referred to as both an inter-tier dielectric layer as well as a semiconductive etch stop material layer throughout the specification. It is unknown how layer 180 can both be a dielectric as well as a semiconductor. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Appropriate correction is required.
Claim Objections
Claim 11 is objected to because of the following informalities: the preamble of. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2021/0305266 A1, hereafter Lee).
Regarding claim 1, Lee in Fig. 27 teaches a memory device, comprising:
a first-tier alternating stack (132, 142, [0080]) of first insulating layers (132, [0080]) and first electrically conductive layers (142, [0082]);
an etch stop semiconductor material layer (180, [0088]) located over the first-tier alternating stack (142, 132);
a second-tier alternating stack (232, 242, [0102]) of second insulating layers (232, [0103]) and second electrically conductive layers (242 is described as able to be comprised of the same material as 142, [0102]) overlying the etch stop semiconductor material layer (180);
an inter-tier memory opening (149, [0089], and 249, [0111]) vertically extending through the second-tier alternating stack (232, 242), the etch stop semiconductor material layer (180), and the first-tier alternating stack (132, 142); and
a memory opening fill structure (128, 148, [0095], and 58, [0128]) located in the inter-tier memory opening and comprising a vertical semiconductor channel (60, [0127]) and a vertical stack of memory elements (see annotated Fig. 12D, [0192]).
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Regarding claim 2, Fig. 27 of Lee teaches the memory device of claim 1, wherein:
the memory opening fill structure (128, 148, [0095], and 58, [0128]) comprises a memory film (50, [0122]) that continuously extends vertically at least from a bottommost layer (see annotated Fig. 12D) within the first-tier alternating stack (132, 142, [0080]) to a topmost layer (see annotated Fig. 12D) within the second-tier alternating stack (232, 242, [0102]); and
the vertical stack of memory elements (see annotated Fig. 12D, [0192]) comprises portions of the memory film (50) located at levels of the first electrically conductive layers (142, [0082]) and the second electrically conductive layers (242, [0102]).
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Regarding claim 3, Fig. 27 of Lee teaches the memory device of claim 2, wherein the etch stop semiconductor material layer (180, [0088]) is in direct contact with a surface segment of an outer sidewall of the memory film (50, [0122]).
Regarding claim 7, Fig. 27 of Lee teaches the memory device of Claim 2, wherein the etch stop semiconductor material layer (180, [0088]) is electrically isolated (backside isolation dielectric layer may be formed around the electrically conductive layers [0196]) from each of the second electrically conductive layers (242, [0102]).
Regarding claim 8, Fig. 27 of Lee teaches the memory device of Claim 1, wherein a bottommost second electrically conductive layer (242 on 180 in Fig. 12D) of the second electrically conductive layers (242, [0102]) is electrically isolated from the etch stop semiconductor material layer (180, [0088]) by a backside blocking dielectric layer (backside isolation dielectric layer may be formed around the first and second electrically conductive layers [0196]) that contacts a sidewall of the memory opening fill structure (128, 148, [0095], and 58, [0128]).
Regarding claim 9, Fig. 27 of Lee teaches the memory device of Claim 8, wherein the etch stop semiconductor material layer (180, [0088]) is in contact with a bottom surface of the backside blocking dielectric layer (backside isolation dielectric layer may be formed around the electrically conductive layers [0196], as a bottommost second electrically conductive layer is in contact with the etch stop semiconductor material layer, as seen in Fig. 12D, the etch stop semiconductor material layer is in contact with a bottom surface of the backside blocking dielectric layer surrounding the second electrically conductive layer).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 8 above, and further in view of O'Meara et al. (US 2021/0242020 A1, hereafter O'Meara).
Regarding claim 10, Fig. 27 of Lee teaches the memory device of Claim 8, further comprising an etch stop conductive material layer in direct contact with a top surface of the etch stop semiconductor material layer and with a bottom surface of the backside blocking dielectric layer.
However, Lee teaches that the etch stop layer may contain sublayers [0088]. O'Meara teaches in Fig. 2A a patterning process in which a conductive etch stop layer (204, [0029]) is on top of a semiconductive etch stop (203, [0028]). This is done as the conductive stop has a slower etch rate compared to the semiconductive etch rate [0030] which is used as extra protection during patterning steps. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the etch stop layer of Lee to have sublayers as taught by O'Meara in order to have etch stop layers for multiple patterning processes ([0026]).
Regarding claim 11, Lee in view of O’Meara teach the memory device of Claim 10, wherein the conductive material layer comprises a metal layer or a conductive metal compound. O'Meara teaches the second etch stop layer (204, [0029]) can comprise titanium nitride, which is a conductive metal compound.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of Tsutsumi et al. (US 2020/0251486 A1, hereafter Tsutsumi).
Regarding claim 12, Lee teaches the memory device of Claim 1. Lee doesn't explicitly show an interface between the memory opening fill structure and the etch stop semiconductor material layer is laterally offset farther away from a vertical axis passing through a geometrical center of the memory opening fill structure than an interface between the memory opening fill structure and a bottommost second insulating layer among the second insulating layers is laterally offset from the vertical axis.
However, Tsutsumi shows in Fig. 10C that an interface between the memory opening fill structure (11, 50, 60, 62, 63, [0187]) and the etch stop material layer (180, [0142]) is laterally offset farther away from a vertical axis passing through a geometrical center of the memory opening fill structure (see annotated Fig. 10B) than an interface between the memory opening fill structure (11, 50, 60, 62, 63) and a bottommost second insulating layer (232, [0156]) among the second insulating layers (232) is laterally offset from the vertical axis. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interface between the memory opening fill structure and the etch stop semiconductor material layer to be laterally offset farther away from a vertical axis passing through a geometrical center of the memory opening fill structure than an interface between the memory opening fill structure and a bottommost second insulating layer among the second insulating layers is laterally offset from the vertical axis in order to have a larger landing pad for the second-tier memory opening to be formed on, as Tsutsumi teaches in [0148].
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 2019/0304554 A1) teaches a backside blocking dielectric layer surrounding the conductive layers.
Shim et al. (US 2013/0092994 A1) teaches a backside blocking dielectric layer surrounding the conductive layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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