Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restriction
In response to election/restriction, applicant elected claims 1-12 without traverse.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0305266, hereinafter Lee) in view of Otsu et al. (US 2021/0210424, hereinafter Otsu).
With respect to claim 1, Lee discloses a memory device (Fig. 9B), comprising:
an alternating stack of insulating layers (132’s) and electrically conductive layers (142’s – Para 0082) located over a substrate (Para 0004 – alternating layers on a substrate), the electrically conductive layers having different lateral extents in a contact region that decrease with a vertical distance from a top surface of the substrate (top or bottom part of Fig. 9B – 142’s have different later extents); memory openings vertically extending through the alternating stack and located in a memory array region in which each of the electrically conductive layers is present (Fig. 9B – Para 0054; 0073 and 0090); memory opening fill structures (60L &50) located in the memory openings and comprising a vertical semiconductor channel (60L) and a respective vertical stack of memory elements located at levels of the electrically conductive layers (52/54/56).
Lee does not explicitly disclose a finned dielectric support structure located in the contact region and comprising a dielectric wall portion that continuous vertically extends from the substrate at least to a horizontal plane including top surfaces of the memory opening fill structures, and further comprises dielectric fin structures that are located at levels of the electrically conductive layers and laterally protrude outward from the dielectric wall portion.
In an analogous art, Otsu discloses a finned dielectric support structure located in the contact region and comprising a dielectric wall portion that continuous vertically extends from the substrate at least to a horizontal plane including top surfaces of the memory opening fill structures (Para 0005; 0286; 0305; and 0318 – finned dielectric pillar structure), and further comprises dielectric fin structures that are located at levels of the electrically conductive layers and laterally protrude outward from the dielectric wall portion (Para 0291-0292; 0300-0301).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device by having Otsu’s disclosure in order to increase the surface area without increasing the size of the device to improve the performance of the memory device.
With respect to claim 2, Lee does not explicitly disclose wherein the dielectric fin structures have different lateral extents along a first horizontal direction that increase with a vertical distance from a top surface of the substrate.
In an analogous art, Otsu discloses wherein the dielectric fin structures have different lateral extents along a first horizontal direction that increase with a vertical distance from a top surface of the substrate (Para 0208; Fig. 36A – 679 C are filled with dielectric - have different extents increases with a vertical distance from a top surface for the substrate). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device by having Otsu’s disclosure in order to increase the surface area without increasing the size of the device to improve the performance of the memory device.
With respect to claim 3, Lee does not explicitly disclose wherein each of the dielectric fin structures comprises a respective horizontal top surface that contacts a horizontal bottom surface of a respective overlying insulating layer among the insulating layers.
In an analogous art, Otsu discloses wherein each of the dielectric fin structures comprises a respective horizontal top surface that contacts a horizontal bottom surface of a respective overlying insulating layer among the insulating layers (Para 0204; 0288; Fig. 38A). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device by having Otsu’s disclosure in order to increase the surface area without increasing the size of the device to improve the performance of the memory device.
With respect to claim 4, Lee does not explicitly disclose wherein contact areas between each contacting pair of a respective dielectric fin structure and a respective overlying insulating layer increase with a vertical distance from a top surface of the substrate.
In an analogous art, Otsu discloses wherein contact areas between each contacting pair of a respective dielectric fin structure and a respective overlying insulating layer increase with a vertical distance from a top surface of the substrate (Fig. 38A; Para 0289– as the lateral extents along a first horizontal direction increases with a vertical distance from a top surface of the substrate, the contact area between the fin structure and overlying insulating layer increases accordingly).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device by having Otsu’s disclosure in order to increase the surface area without increasing the size of the device to improve the performance of the memory device.
With respect to claim 5, Lee does not explicitly disclose wherein a subset of the dielectric fin structures including a topmost dielectric fin structure comprises a respective set of at least one opening
therethrough.
In an analogous art, Otsu discloses wherein a subset of the dielectric fin structures including a topmost dielectric fin structure comprises a respective set of at least one opening
therethrough (Fig. 38A – top opening passes through the top stack of fin structures).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device by having Otsu’s disclosure in order to increase the surface area without increasing the size of the device to improve the performance of the memory device.
With respect to claim 6, Lee does not explicitly disclose wherein a total number of openings within each of the dielectric fin structures increases with a vertical distance from a top surface of the substrate.
In an analogous art, Otsu discloses wherein a total number of openings within each of the dielectric fin structures increases with a vertical distance from a top surface of the substrate (Fig. 38A – there are two openings top and bottom).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device by having Otsu’s disclosure in order to increase the surface area without increasing the size of the device to improve the performance of the memory device.
With respect to claim 7, Lee does not explicitly disclose wherein layer contact via structures vertically extend through a first subset of the openings through the subset of the dielectric fin structures; and each of the layer contact via structures contacts a top surface of a respective one of the
electrically conductive layers.
In an analogous art, Otsu discloses wherein layer contact via structures vertically extend through a first subset of the openings through the subset of the dielectric fin structures (Para 0251 – contact via structures 86); and each of the layer contact via structures contacts a top surface of a respective one of the electrically conductive layers (Para 0262; 0311; 0317; and Fig. 27A).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device by having Otsu’s disclosure in order to create electrical connections between different layers of a semiconductor device.
With respect to claim 8, Lee discloses wherein support pillar structures vertically extend through a second subset of the openings through the subset of the dielectric fin structures and contacts
the substrate (20 of Fig. 15 – Para 0166 and 0190).
Lee does not explicitly disclose that the support pillar structures extend through the subset of the dielectric fin structures.
In an analogous art, Otsu discloses that the support pillar structures extend through the subset of the dielectric fin structures (Para 0208; Fig. 18A – support pillar structure (52, 20)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device by having Otsu’s disclosure in order to provide vertical path for data access and electrical connections.
With respect to claim 9, Lee a backside trench fill structure (176 of Fig. 24C)
contacting sidewalls of the alternating stack and vertically extending through each layer
within the alternating stack (Para 0032; 0037; and 0193).
With respect to claim 12, Lee does not explicitly disclose wherein each of the dielectric fin structures comprises: a first sidewall that contacts a respective one of the electrically conductive layers or is laterally spaced from the respective one of the electrically conductive layers by a backside
blocking dielectric layer; and a second sidewall that is parallel to the first sidewall and contacts the backside trench fill structure.
In an analogous art, Otsu discloses wherein each of the dielectric fin structures comprises: a first sidewall that contacts a respective one of the electrically conductive layers or is laterally spaced from the respective one of the electrically conductive layers by a backside blocking dielectric layer (Fig. 40A – backside of 276F is spaced from the respective layer 242 by 52– Para 0204-0205); and a second sidewall that is parallel to the first sidewall and contacts the backside trench fill structure (front side of 276F contacts 176).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device by having Otsu’s disclosure in order to increase the surface area without increasing the size of the device to improve the performance of the memory device.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 11 is objected because of its dependency on claim 10.
With respect to claim 10, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the backside trench fill structure comprises: at least two first elongated portions that laterally extend along a first horizontal direction and contact lengthwise sidewalls of each of the insulating layers and each of the electrically conductive layers; and at least one second elongated portion that laterally extends along a second horizontal direction that is different from the first horizontal direction and connecting a respective neighboring pair of first elongated portions of the backside trench fill structure” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
Prosecution Insights