DETAILED ACTION
Claims 1-8 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application (17/266,338) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 17/266,338 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner recommends incorporating the copying of a result from a buffer register to a destination register.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because it includes a number of typographical errors/informalities that were pointed out in the parent application. Please review the specification objections in the Office actions mailed on April 5, 2022, and January 12, 2023, in application 17/266,338, and make amendments to the instant disclosure to address these issues, where appropriate.
Drawings
FIG.2 is objected to because of the following minor informalities:
The examiner questions whether the arrows are drawn correctly. For phase 1, only $v3 is identified in the instruction, which leads the examiner to believe that $v3 is both a source register and a destination register. However, the arrow shows reading data from $v4. Should the right arrow be shifted up to connect to $v3? Similarly, for phase 2 for the same instruction, it appears the arrow leading to “COPY” should source from the $buffer register where the result of phase 1 was written (not $v7), and the output arrow should point to $v3 (not $v4).
A corrected drawing sheet in compliance with 37 CFR 1.121(d) is required in reply to the Office action to avoid abandonment of the application. Please ensure that any replacement is in only black and white to avoid pixelation and further objection. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections/Recommendations
Claim 1 is objected to because of the following informalities:
In lines 4-5, applicant claims that a core is connected to the register file and buffer register. The word “core” only appears once in paragraph [0024] of the specification, where processor 100 is described as a core (in one embodiment). From FIG.1, core 100 is not connected to the register file and buffer register. Instead, the core includes the register file and buffer register. As such, it appears lines 4-5 include a typographical error. The examiner recommends rewording to --a vector processing core, comprising the vector register file and the at least one buffer register, to:--.
In claim 6, the examiner recommends replacing “location of a memory” with --memory location-- to match the language used in paragraph 33 of the specification.
In claim 7, line 1, the examiner recommends inserting --vector-- before “processing”.
In claim 7, line 4, the examiner recommends replacing “micro-ops” with --micro-operations--.
Claim 8 is objected to for similar reasoning as claim 1.
Claim 8 is further objected to because of the following informalities:
In line 5, delete “to execute a vector instruction” (make similar to claim 1) and, in line 6, replace “the” with --a--, to remove the redundancy in the 5th to last line (currently applicant’s claim states “…core…to execute a vector instruction to:…execute the vector instruction”). The examiner’s proposal will eliminate this redundancy. Additionally, this will overcome the 112(b) rejection set forth below for claim 8.
In line 9, replace “determining” with --determine--.
In line 12, insert --and-- after the semicolon.
In line 14, replace the comma with a colon.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 7-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 3, “the vector instruction set”. Applicant could replace “the” with --a--.
In claim 7, last paragraph, “the result”, because it isn’t clear if applicant is referring to the first result of the previous paragraph, or the result of claim 1. The examiner recommends just using one term for the result throughout the claims, e.g. “first result”.
Claim 8 is indefinite because it is inconsistent with the disclosure. Claim 8 sets forth that the core executes the instruction, prior to performing an operation of the instruction, to determine whether the instruction has an opportunity to cause an interrupt. It is the examiner’s understanding from paragraphs 38 and 40, that applicant has disclosed determining whether an instruction could potentially cause an interrupt (or determining that it won’t cause an interrupt) early in the pipeline (including “prior to starting execution”). If this is the case, it wouldn’t be the executing of the instruction that results in the determination, as claimed. This inconsistency renders the claim indefinite because, when read in light of the specification, the examiner is not clear what “execute a vector instruction” constitutes if it does not actually include known execution. See MPEP 2173.03. Applicant is asked to provide any necessary explanation as to what is meant by the claim, or amend the claim as proposed above (i.e., remove “to execute a vector instruction” from line 5).
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 5 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends. Specifically, apart from using the words “phase” and “phases” in claim 1, the last two paragraphs of claim 1 encompass the limitations of claim 5. That is, the storing the result in the buffer register in claim 1 is a first phase and the copying of the result from the buffer register to the second register in claim 1 is a second phase. Thus, claim 5 sets forth nothing beyond that which is already set forth by claim 1 (explicit or otherwise). Applicant may cancel claim 5, amend it to be in proper dependent form, or present a sufficient showing that it complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moudgill et al. (US 2016/0224346 A1).
Referring to claim 1, Moudgill has taught a processor (FIG.1), comprising:
a vector register file comprising a plurality of vector registers (FIG.2, 206);
at least one buffer register (paragraph [0410], “intermediate register”); and
a vector processing core (FIG.2, components above and below registers 214, along with at least some of the components shown in FIG.1), communicatively connected to the vector register file and the at least one buffer register (the core is shown as connected to registers 206 in FIG.2. And, from paragraph [0410], the core writes to the intermediate/buffer register and, thus, is connected to the buffer register), to:
receive a vector instruction (paragraph [0410]) comprising a first identifier representing a first vector register of the plurality of vector registers (e.g. see paragraphs [0362]-[0363]. An example long vector instruction is a vector add instruction that includes $v2, a first identifier of a source register), and a second identifier representing a second vector register of the plurality of vector registers (e.g. see paragraph [0362]. The vector add instruction includes $v1, a second identifier of a destination register), wherein the first vector register is a source register and the second vector register is a destination register (again, the first and second registers are source and destination registers, respectively, as explained above);
execute the vector instruction based on data values stored in the first vector register to generate a result and store the result in the at least one buffer register (see paragraph [0362] and [0410]); and
copy the result from the at least one buffer register to the second vector register (see paragraph [0410]).
Referring to claim 2, Moudgill has taught the processor of claim 1, wherein the source register is one of identical to or different than the destination register (in paragraph [0362], source register v2 is different from destination register v1).
Referring to claim 3, Moudgill has taught the processor of claim 1, wherein the vector instruction set defines a plurality of architected registers (from paragraphs [0362] and [0413]-[0414], the $v (lowercase) registers are architected registers), and wherein each of the plurality of the architected registers is mapped to a corresponding one of the plurality of vector registers (see paragraphs [0074] and [0413]-[0414], and FIG.9. Register renaming may be implemented to efficiently map $v registers to $V (physical) registers. Alternatively, see paragraphs [0397]-[0398]. If renaming is not implemented, there is simply a 1-to-1 mapping of architected to physical registers).
Referring to claim 4, Moudgill has taught the processor of claim 1, wherein each of the plurality of the architected registers is fixedly mapped to a corresponding one of the plurality of vector registers (again, see paragraphs [0074] and [0413]-[0414], and FIG.9. Renaming causes a fixed mapping between architected and physical registers for some time period. For instance, in FIG.9, $v2 is fixedly mapped to $V2 for at least the time period represented in FIG.9. Alternatively, see paragraphs [0397]-[0398]. If renaming is not implemented, there is simply a 1-to-1 fixed mapping of architected to physical registers), and wherein a mapping between an architected register and a corresponding vector register is not altered by register renaming during execution of a second vector instruction (see FIG.9. When renaming is implemented, a second vector instruction (e.g. vmul) does not change the $v2-to-$V2 mapping. Alternatively, when renaming is not implemented, the mappings do not change).
Referring to claim 5, Moudgill has taught the processor of claim 1, wherein execution of the vector instruction is performed in two phases comprising a first phase to generate a first result and store the first result in the at least one buffer register and a second phase to copy the result from the at least one buffer register to the second vector register (from paragraph [0410], a result is first written to an intermediate/buffer register (which is the first phase), and then copied from that register to the second register/destination (which is the second phase)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Moudgill in view of the examiner’s taking of Official Notice.
Referring to claim 6, Moudgill has taught the processor of claim 1, but has not taught wherein the at least one buffer register is one of a location of a memory associated with the processor, a logic circuit separate from the vector register file, or an additional vector register other than the plurality of vector registers in the vector register file. However, implementing a temporary/intermediate register in each of these ways was well-known in the art before applicant’s invention. Taking the intermediate register being separate from the vector register file as an example, this would allow the processor to fully utilize all registers of the file for a non-intermediate purpose. In short, with N registers in a file and a separate intermediate register, there is more storage (N+1 registers) than if the intermediate register was part of the file (N registers). As such, for increased storage, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moudgill such that the at least one buffer register is a logic circuit separate from the vector register file.
Referring to claim 7, Moudgill has taught the processor of claim 1, wherein the processing core comprises a vector instruction execution pipeline (e.g. FIG.4, FIG.6), the vector instruction execution pipeline comprising:
an instruction fetch circuit to receive the vector instruction (see FIG.1, fetch circuit 104, which corresponds to the instruction fetch (IF) stage in FIG.4);
an instruction execute circuit to execute the vector instruction based on data values stored in the first vector register to generate a first result and store the first result in the at least one buffer register (see paragraph [0410]; FIG.1, 108; FIG.2, units 216-224 (which make up one or more execution units; and FIG.4, execute (EX) stage); and
an instruction write-back circuit to responsive to determining that the second vector register is safe to write, copy the result from the at least one buffer register to the second vector register (again, see paragraph [0410]. Also, see FIG.2, and note that ultimately, results from the execution unit are written back to registers 206. Also see FIG.4, write-back (WB) stage).
Moudgill has further taught an instruction decode circuit (FIG.4, decode stage (DEC)) but has not taught that that the decode circuit is to generate micro-ops based on the vector instruction. However, such a decoder was well-known in the art before applicant’s invention. This allows a processor to decode a complex instruction into smaller simple instructions designed to execute in a single cycle, thereby reducing cycles per instruction. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moudgill such that the instruction decode circuit is to generate micro-ops based on the vector instruction.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Moudgill in view of Songu (JP H07271582 A), a translation of which is included herewith.
Referring to claim 8, Moudgill has taught a processor (FIG.1), comprising:
a vector register file comprising a plurality of vector registers (FIG.2, 206);
at least one buffer register (paragraph [0410], “intermediate register”); and
a vector processing core (FIG.2, components above and below registers 214, along with at least some of the components shown in FIG.1), communicatively connected to the vector register file and the at least one buffer register (the core is shown as connected to registers 206 in FIG.2. And, from paragraph [0410], the core writes to the intermediate/buffer register and, thus, is connected to the buffer register), to execute a vector instruction (e.g. the vector instruction of paragraph [0410], which could be, for example, a vector add instruction as shown in paragraph [0362]-[0363]) to:
responsive to receiving the vector instruction comprising a first identifier representing a first vector register of the plurality of vector registers (e.g. from paragraph [0362], the vector add instruction includes source register v2) and a second identifier representing a second vector register of the plurality of vector registers (e.g. from paragraph [0362], the vector add instruction includes a target/destination register v1), wherein the first vector register is a source register and the second vector register is a destination register (again, the first and second registers are source and destination registers, respectively, as explained above);
execute the vector instruction based on data values stored in the first vector register to generate a result and store the result in the at least one buffer register (see paragraph [0362] and [0410]); and
copy the result from the at least one buffer register to the second vector register (see paragraph [0410]).
Moudgill has not taught that the core is to, prior to performing an operation of the vector instruction, determining whether the operation of the vector instruction has an opportunity to cause a precise interrupt, nor that the storage of the result in a buffer register and the copying of the result from the buffer register to the second register occurs responsive to determining that performance of the operation has the opportunity to cause the precise interrupt. However, Songu has taught determining, prior to execution, whether execution of an instruction can cause an exception, and adjusting accordingly (see p.18 of the translation, 2nd to last paragraph, which states “An important feature of the preferred embodiment is that sequencer unit 18 determines whether the execution of an instruction can cause an exception. The sequencer unit 18 makes this determination prior to executing the instruction.”). Recall that Moudgill temporarily stores a result for a vector instruction in case a precise exception occurs (paragraph [0410]). One of ordinary skill in the art would have recognized that this temporary buffering is beneficial when an exception does occur. However, when an exception does not occur, the buffering constitutes an unnecessary additional storage step (with additional associated delay), compared to writing the result directly to the destination register. As such, one of ordinary skill in the art would have been motivated to determine ahead of time in Moudgill that an instruction cannot cause an exception (as taught by Songu) so that the temporary buffering of the result could be bypassed/skipped, thereby speeding up the time it takes to write the result to its final destination and lowering power consumption by not performing an extra write where unnecessary. Consequently, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moudgill such that the core is to, prior to performing an operation of the vector instruction in paragraph [0410], determining whether the operation of the vector instruction has an opportunity to cause a precise interrupt (as taught by Songu), and only performing the storage of the result in the intermediate register (buffer register) and the copying of the result from the buffer register to the second register responsive to determining that performance of the operation has the opportunity to cause the precise interrupt.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Gonion (US 2014/0059328 A1) has taught a holding unit 707 that holds a result until the predicate of the instruction generating the result becomes available, at which point the result is written from 707 to a register.
Nguyen (US 5,961,629) has taught either storing a result to a temporary buffer prior to storing it to a register, or bypassing the temporary buffer and storing directly to the register (FIG.6A). However, the choice is based on whether the current instruction is the next instruction to retire, and not based on whether an instruction is determined to potentially cause a precise interrupt.
Song (CA 2,137,046) has taught setting a “finished” bit to ‘1’ for an instruction that cannot cause an exception determining whether an instruction. However, there is no disclosure that storing a result to a buffer register, and then copying that result from the buffer register to a second register is done in response to this determining.
Cheong (US 5,805,906) has taught “In the completion stage an instruction waits for the point at which there is no longer a possibility of an interrupt so that depositing its results will not violate the program order, at which point the instruction is considered "complete", as the term is used herein. Associated with a completion stage, there are buffers to hold execution results before results are deposited into the destination register, and buffers to backup content of registers at specified checkpoints in case an interrupt needs to revert the register content to its pre-checkpoint value. Either or both types of buffers can be employed in a particular implementation. At completion, the results of execution in the holding buffer will be deposited into the destination register and the backup buffer will be released.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183