DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed June 6, 2026 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
No English translation for Notice of Allowance for Korean Patent Application No. 10-2022-0190597 issued by the Korean Patent Office on May 26, 2026
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the wherein the third work function electrode includes an inner surface covering the first barrier layer and an outer surface contacting a first electrode of the data storage element in claim 16 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. 2023/0048424), and further in view of Choi et al (U.S. 2023/0180455).
Regarding claim 1. Kim teaches a semiconductor device (FIG. 1 and 2, item MC), comprising:
a lower structure (FIG. 2, item SUB);
a horizontal layer (FIG. 1 and 2, item ACT) spaced apart from the lower structure (FIG. 1 and 2, item SUB) and extending in a direction (FIG. 1 and 2, item D2) parallel to the lower structure (FIG. 2, item SUB);
a vertical conductive line (FIG. 1 and 2, item BL) extending in a direction (FIG. 1 and 2, item D1) perpendicular to the lower structure (FIG. 1 and 2, item SUB) and coupled (FIG. 1 and 2, item BLC) to a first-side end (FIG. 1 and 2, itemSR) of the horizontal layer (FIG. 1 and 2, item ACT);
a data storage element (FIG. 1 and 2, item CAP) coupled (FIG. 1 and 2, item SNC) to a second-side end (FIG. 1 and 2, item DR) of the horizontal layer (FIG. 1 and 2, item ACT); and
a horizontal conductive line (FIG. 1 and 2, item DWL) extending in a direction (FIG. 1 and 2, item D3) crossing the horizontal layer (FIG. 1 and 2, item ACT),
wherein the horizontal conductive line (FIG. 1 and 2, item DWL) includes:
a first work function electrode (FIG. 1 and 2, item HWG);
a second work function electrode (FIG. 1 and 2, item LWG of item WL2) disposed adjacent to the vertical conductive line (FIG. 1 and 2, item HWG) and having a lower work function ([0043]) than the first work function electrode (FIG. 1 and 2, item HWG);
a third work function electrode (FIG. 1 and 2, item LWG of item WL1) disposed adjacent to the data storage element (FIG. 1 and 2, item CAP) and having a lower work function ([0043]) than the first work function electrode (FIG. 1 and 2, item HWG);
a first barrier layer (FIG. 1 and 2, item P1) between the first work function electrode (FIG. 1 and 2, item HWG) and the third work function electrode (FIG. 1 and 2, item LWG of item WL1); and
a second barrier layer (FIG. 1 and 2, item P2) between the first work function electrode (FIG. 1 and 2, item HWG) and the second work function electrode(FIG. 1 and 2, item LWG of item WL2);
Kim fails to explicitly disclose wherein the third work function electrode has a bent shape or a cup shape.
However, Choi et al teaches wherein the third work function ([0091]) electrode (FIG. 10, item WF1) has a bent shape or a cup shape ([0091], i.e. Referring to FIG. 10, the first and second work function adjusting layers WF1 and WF2 may wrap one end portions of the first and second gate body layers GB1 and GB2).
Since Kim and Choi et al teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Kim et al with the teachings of wherein the third work function electrode has a bent shape or a cup shape as disclosed by Choi et al. The use of layers WF1 and WF2 may wrap one end portions of the first and second gate body layers GB1 and GB2 in Choi et al provides for work function adjusting layers (Choi et al, [0091]).
Regarding claim 16. Kim and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim further discloses wherein the third work function electrode (FIG. 1 and 2, item LWG of item WL1) includes an inner surface covering (FIG. 1 and 2 shows item LWG of item WL1 covers a surface of item P1) the first barrier layer (FIG. 1 and 2, item P1) and an outer surface contacting (FIG. 1 and 2 shows item LWG of item WL1 contacts item SNC through item DR) a first electrode (FIG. 1 and 2, item SNC) of the data storage element (FIG. 1 and 2, item CAP).
Regarding claim 17. Kim and Choi et al discloses all the limitations of the semiconductor device of claim 1 above
Kim further discloses wherein the third work function electrode (FIG. 1 and 2, item LWG of item WL1) is disposed between ([0024]) the first work function electrode (FIG. 1 and 2, item HWG) and the data storage element (FIG. 1 and 2, item CAP).
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2024/0215216), and Choi et al (U.S. 2023/0180455).
Regarding claim 1. Kim et al discloses all the limitations of a semiconductor device (FIG. 3A-3B; [0007]), comprising:
a lower structure (FIG. 3A-3B, item LS);
a horizontal layer (FIG. 3A-3B, item HL) spaced apart from the lower structure (FIG. 3A-3B, item LS) and extending in a direction parallel (FIG. 3A-3B, item D2) to the lower structure (FIG. 3A-3B, item LS);
a vertical conductive line (FIG. 3A-3B, item BL) extending in a direction perpendicular (FIG. 3A-3B, item D1) to the lower structure(FIG. 3A-3B, item LS) and coupled (FIG. 3A-3B, item BLC) to a first-side end (FIG. 3A-3B, item BLC) of the horizontal layer (FIG. 3A-3B, item HL);
a data storage element (FIG. 3A-3B, item CAP) coupled to a second-side end (FIG. 3A-3B, item SNC) of the horizontal layer (FIG. 3A-3B, item HL); and
a horizontal conductive line (FIG. 3A-3B, item DWL) extending in a direction crossing (FIG. 3A-3B, item D3) the horizontal layer (FIG. 3A-3B, item HL),
wherein the horizontal conductive line (FIG. 3A-3B, item DWL) includes:
a first work function electrode (FIG. 3A-3B, item G11);
a second work function electrode (FIG. 3A-3B, item G12) disposed adjacent to the vertical conductive line (FIG. 3A-3B, item BL) and having a lower work function ([0007]) than the first work function electrode (FIG. 3A-3B, item G11);
a third work function electrode (FIG. 3A-3B, item G13) disposed adjacent to the data storage element (FIG. 3A-3B, item CAP) and having a lower work function ([0007]) than the first work function electrode (FIG. 3A-3B, item G11);
a first barrier layer (FIG. 3A-3B, item G13L) between the first work function electrode (FIG. 3A-3B, item G11) and the third work function electrode (FIG. 3A-3B, item G13); and
a second barrier layer (FIG. 3A-3B, item G12L) between the first work function electrode (FIG. 3A-3B, item G11) and the second work function electrode (FIG. 3A-3B, item G12).
Kim et al fails to explicitly disclose wherein the third work function electrode has a bent shape or a cup shape.
However, Choi et al teaches wherein the third work function ([0091]) electrode (FIG. 10, item WF1) has a bent shape or a cup shape ([0091], i.e. Referring to FIG. 10, the first and second work function adjusting layers WF1 and WF2 may wrap one end portions of the first and second gate body layers GB1 and GB2).
Since Kim et al and Choi et al teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Kim et al with the teachings of wherein the third work function electrode has a bent shape or a cup shape as disclosed by Choi et al. The use of layers WF1 and WF2 may wrap one end portions of the first and second gate body layers GB1 and GB2 in Choi et al provides for work function adjusting layers (Choi et al, [0091]).
Regarding claim 2. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the second and third work function electrodes have a work function that is lower than a mid-gap work function of silicon ([0075]), and the first work function electrode has a work function that is higher than the mid-gap work function of silicon ([0075]).
Regarding claim 3. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the second and third work function electrodes include doped polysilicon that is doped with an N-type dopant ([0076]).
Regarding claim 4. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the first work function electrode includes a metal-based material ([0076]).
Regarding claim 5. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the first work function electrode includes a metal, a metal nitride, or a combination thereof ([0076], i.e. The first work function electrode G11 may include a metal, a metal nitride, or a combination thereof).
Regarding claim 6. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the first work function electrode has a greater volume than the second and third work function electrodes ([0082], i.e. The first work function electrode G11 may have a larger volume than the second and third work function electrodes G12 and G13).
Regarding claim 7. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein each of the first, second, and third work function electrodes vertically overlaps with the horizontal layer ([0083], The first work function electrodes G11 of the horizontal conductive line DWL may vertically overlap with the channel CH, and the second work function electrodes G12 of the horizontal conductive line DWL may overlap with the first doped region SR of the horizontal layer HL. The third work function electrodes G13 of the horizontal conductive line DWL may vertically overlap with the second doped region DR of the horizontal layer HL.).
Regarding claim 8. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the second work function electrode and the third work function electrode have the same work function ([0085], i.e. second and third work function electrodes G12 and G13 of a low work function may be disposed at both ends of the horizontal conductive line DWL).
Regarding claim 9. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the horizontal layer has a thickness that is smaller than thicknesses of the first, second, and third work function electrodes ([0074], i.e. . The horizontal layer HL may have a thickness that is smaller than the thicknesses of the first, second, and third work function electrodes G11, G12, and G13).
Regarding claim 10. Kim discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the horizontal layer includes a monocrystalline semiconductor material, a polycrystalline semiconductor material, or an oxide semiconductor material ([0034]).
Regarding claim 11. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the horizontal layer includes: a first doped region coupled to the vertical conductive line; a second doped region coupled to the data storage element; and a channel between the first doped region and the second doped region ([0036], i.e. a first doped region SR disposed between the channel CH and the vertical conductive line BL, and a second doped region DR disposed between the channel CH and the data storage element CAP).
Regarding claim 12. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the horizontal conductive line includes a double structure of horizontal conductive lines that face each other with the horizontal layer interposed therebetween ([0033]; i.e. The horizontal conductive line DWL may have a double structure. For example, the horizontal conductive line DWL may include first and second horizontal conductive lines WL1 and WL2 facing each other with the horizontal layer HL interposed therebetween).
Regarding claim 13. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the data storage element includes a capacitor, and the capacitor includes a cylindrical first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode ([0041], i.e. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally arranged in the second direction D2. The first electrode SN may have a horizontally oriented cylindrical-shape.).
Regarding claim 14. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses further comprising: a first contact node between the vertical conductive line and the first-side end of the horizontal layer; and a second contact node between the data storage element and the second-side end of the horizontal layer ([0071], i.e. The memory cell MC1 may further include a first contact node BLC between the vertical conductive line BL and the horizontal layer HL and a second contact node SNC between the horizontal layer HL and the data storage element CAP).
Regarding claim 15. Kim et al and Choi et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the first and second barrier layers include a metal nitride ([0079], i.e. The first and second barrier layers G12L and G13L may include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride).
Response to Arguments
Applicant's arguments filed March 2, 2026 have been fully considered but they are not persuasive.
On pages 10-14 of applicant’s remarks, applicant appears to argue that neither Kim ‘424, Kim ‘216, nor Oh et al disclose applicant’s amended claim limitation of a bent-shape or cup-shaped third work function electrode.
Examiner respectfully agrees with applicant’s assertion.
However, neither Kim ‘424, Kim ‘216, nor Oh et al were used to teach applicant’s amended claim limitation.
Choi et al teaches applicant’s amended claim limitation.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim (U.S. 2022/0399340) Semiconductor memory device.
Cho (U.S. 2022/0285353) semiconductor memory device.
Masuoka et al (U.S. 2018/0062009) Semiconductor device.
Cho (U.S. 2023/0397403) Semiconductor device and method of fabricating the same.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.E.B./Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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