Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18350765 filed on 07/12/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of claims 1-20 in the reply filed on 11/17/2025 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (US 2019/0096744).
Regarding independent claim 1, Hu et al. teach a semiconductor device comprising:
a chip (Figs. 1A & 1B, element 100, paragraph 0020) that has a first main surface on one side and a second main surface on another side;
a pn-junction portion (Figs. 1B & 1B, element 105, paragraph 0022 discloses pn junction formed between layers 106 and 104) that is formed in an interior of the chip such as to extend along the first main surface;
a device region (Figs. 1A & 1B, element 101, paragraph 0021) that is provided in the first main surface;
a first trench (Figs. 1A & 1B, element 114, paragraph 0020) structure that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in the first main surface (Figs. 1A & 1B); and
a second trench structure (Figs. 1A & 1B, element 174, paragraph 0020) that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in a region further to the device region side than the first trench structure (Figs. 1A & 1B).
Regarding claim 2, Hu et al. teach wherein the first trench structure is constituted of a first trench electrode structure (Figs. 1A & 1B, element 118, paragraph 0028) that is electrically connected to the chip, and the second trench structure is constituted of a second trench electrode structure (Figs. 1A & 1B, element 178, paragraph 0028) that is electrically insulated (Figs. 1A & 1B, element 176, paragraph 0040) from the chip.
Regarding claim 3, Hu et al. teach wherein the first trench structure has a lower end portion that is electrically connected to the chip (Figs. 1A & 1B disclose bottom portion without dielectric liner 116).
Regarding claim 4, Hu et al. teach wherein the second trench structure is electrically separated from the first trench structure (Figs. 1A & 1B disclose dielectric liner 176 surrounding the trench structure).
Regarding claim 5, Hu et al. teach wherein the second trench structure is formed in an electrically floating state (paragraph 0041).
Regarding claim 6, Hu et al. teach wherein a potential different from that of the first trench structure is to be occurred in the second trench structure (paragraph 0028,0041).
Regarding claim 7, Hu et al. teach wherein the first trench structure has a first width, and the second trench structure has a second width that is not more than the first width (Figs. 1A & 1B, paragraph 0023).
Regarding claim 8, Hu et al. teach wherein the second trench structure is formed at an interval of not more than the first width from the first trench structure (paragraph 0050 discloses inter-trench distance d.sub.T of 2 μm, paragraph 0037 discloses first trench width 2.65 μm).
Regarding claim 9, Hu et al. teach wherein the first trench structure includes a first trench (Figs. 1A & 1B, element 114, paragraph 0020) that penetrates through the pn-junction portion, a first insulating film (Figs. 1A & 1B, element 116, paragraph 0027) that covers an inner wall of the first trench such as to expose the chip from a bottom wall of the first trench, and a first electrode (Figs. 1A & 1B, element 118, paragraph 0028) that is embedded in the first trench with the first insulating film therebetween and is electrically connected to the chip at the bottom wall of the first trench, and the second trench structure includes a second trench (Figs. 1A & 1B, element 174, paragraph 0020) that penetrates through the pn-junction portion, a second insulating film (Figs. 1A & 1B, element 176, paragraph 0040) that covers an inner wall of the second trench, and a second electrode (Figs. 1A & 1B, element 178, paragraph 0028) that is embedded in the second trench with the second insulating film therebetween and is electrically insulated from the chip.
Regarding claim 10, Hu et al. teach wherein the second trench structure includes a bottom side insulator (Figs. 1A & 1B, bottom portion of element 176, paragraph 0040) that is embedded in a bottom wall side of the second trench such as to be continuous to the second insulating film and has a thickness exceeding a thickness of the second insulating film (Figs. 1A & 1B), and the second electrode is embedded in the second trench with the second insulating film and the bottom side insulator therebetween (Figs. 1A & 1B).
Regarding claim 11, Hu et al. teach further comprising: a first layer (Figs. 1A & 1B, element 104, paragraph 0024 discloses p type) of a first conductivity type that is formed in a region inside the chip on the second main surface side; a second layer (Figs. 1A & 1B, element 108, paragraph 0024 discloses p type) of the first conductivity type or a second conductivity type that is formed in a region inside the chip on the first main surface side; and a third layer (Figs. 1A & 1B, element 106, paragraph 0025 discloses n type) of the second conductivity type that is interposed in a region inside the chip between the first layer and the second layer and forms the pn-junction portion with the first layer; wherein the first trench structure penetrates through the second layer and the third layer such as to reach the first layer and demarcates the device region in the second layer (Figs. 1A & 1B), and the second trench structure penetrates through the second layer and the third layer such as to reach the first layer and demarcates the device region in a region of the second layer further to the device region side than the first trench structure (Figs. 1A & 1B).
Regarding claim 12, Hu et al. teach wherein the first trench structure is electrically connected to the first layer and electrically insulated Figs. 1A & 1B, element 116, paragraph 0027) from the second layer and the third layer, and the second trench structure is electrically insulated (Figs. 1A & 1B, element 176, paragraph 0040) from the first layer, the second layer and the third layer.
Regarding claim 13, Hu et al. teach further comprising: a first layer (Figs. 1A & 1B, element 104, paragraph 0024 discloses p type) of a first conductivity type that is formed in a region inside the chip on the second main surface side; and a second layer (Figs. 1A & 1B, element 106, paragraph 0025 discloses n type) of a second conductivity type that is formed in a region inside the chip on the first main surface side and forms the pn-junction portion with the first layer; wherein the first trench structure penetrates through the second layer such as to reach the first layer and demarcates the device region in the second layer (Figs. 1A & 1B), and the second trench structure penetrates through the second layer such as to reach the first layer and demarcates the device region in a region of the second layer further to the device region side than the first trench structure (Figs. 1A & 1B).
Regarding claim 14, Hu et al. teach wherein the first trench structure is electrically connected to the first layer and electrically insulated (Figs. 1A & 1B, element 116, paragraph 0027) from the second layer, and the second trench structure is electrically insulated (Figs. 1A & 1B, element 176, paragraph 0040) from the first layer and the second layer.
Regarding claim 15, Hu et al. teach wherein further comprising: an inter-trench region (paragraph 0050 discloses inter-trench distance d.sub.T) that is demarcated in a region between the first trench structure and the second trench structure and is formed in an electrically floating state (paragraph 0045-0050).
Regarding claim 16, Hu et al. teach further comprising: a transistor that is formed in the device region (paragraph 0026 discloses forming low voltage NLDMOS transistor in device region 101).
Regarding independent claim 17, Hu et al. teach a semiconductor device comprising:
a first layer (Figs. 1A & 1B, element 104, paragraph 0024 discloses p type) of a first conductivity type;
a second layer (Figs. 1A & 1B, element 108, paragraph 0024 discloses p type) of the first conductivity type or a second conductivity type that is laminated on the first layer;
a third layer (Figs. 1A & 1B, element 106, paragraph 0025 discloses n type) of the second conductivity type that is interposed between the first layer and the second layer;
a device region (Figs. 1A & 1B, element 101, paragraph 0021) that is provided in the second layer;
a first trench structure (Figs. 1A & 1B, element 114, paragraph 0020) that penetrates through the second layer and the third layer such as to reach the first layer and demarcates the device region in the second layer (Figs. 1A & 1B); and
a second trench structure (Figs. 1A & 1B, element 174, paragraph 0020) that penetrates through the second layer and the third layer such as to reach the first layer and demarcates the device region in a region of the second layer further to the device region side than the first trench structure (Figs. 1A & 1B).
Regarding claim 18, Hu et al. teach wherein the first trench structure is constituted of a first trench electrode structure (Figs. 1A & 1B, element 118, paragraph 0028) that is electrically connected to the first layer and electrically insulated (Figs. 1A & 1B, element 116, paragraph 0027) from the second and the third layer, and the second trench structure is constituted of a second trench electrode structure (Figs. 1A & 1B, element 178, paragraph 0028) that is electrically insulated (Figs. 1A & 1B, element 176, paragraph 0040) from the first layer, the second layer and the third layer.
Regarding independent claim 19, Hu et al. teach a semiconductor device comprising:
a first layer (Figs. 1A & 1B, element 106, paragraph 0025 discloses n type) of a first conductivity type;
a second layer of (Figs. 1A & 1B, element 108, paragraph 0024 discloses p type) a second conductivity type that is laminated on the first layer;
a device region (Figs. 1A & 1B, element 101, paragraph 0021) that is provided in the second layer;
a first trench structure (Figs. 1A & 1B, element 114, paragraph 0020) that penetrates through the second layer such as to reach the first layer and demarcates the device region in the second layer (Figs. 1A & 1B); and
a second trench structure (Figs. 1A & 1B, element 174, paragraph 0020) that penetrates through the second layer such as to reach the first layer and demarcates the device region in a region of the second layer further to the device region side than the first trench structure (Figs. 1A & 1B).
Regarding claim 20, Hu et al. teach wherein the first trench structure is constituted of a first trench electrode structure (Figs. 1A & 1B, element 118, paragraph 0028) that is electrically connected to the first layer and electrically insulated (Figs. 1A & 1B, element 116, paragraph 0027) from the second layer, and the second trench structure is constituted of a second trench electrode structure (Figs. 1A & 1B, element 178, paragraph 0028) that is electrically insulated (Figs. 1A & 1B, element 176, paragraph 0040) from the first layer and the second layer.
Conclusion
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813