Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18350898 filed on 07/12/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of claims 1-2 in the reply filed on 10/15/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagaoka et al. (US 2018/0240914).
Regarding independent claim 1, Nagaoka et al. teach a semiconductor device comprising:
a semiconductor substrate (Fig. 2, element 12, paragraph 0041) including an element region (Fig. 2, element X) and a peripheral region (Fig. 2, element Y) located around the element region,
the semiconductor substrate having a recess (Fig. 2, paragraph 0042) located at an upper surface of the semiconductor substrate in the peripheral region such that an upper surface of the semiconductor substrate in the element region protrudes further than the upper surface of the semiconductor substrate in the peripheral region;
an upper electrode (Fig. 2, element 16, paragraph 0041) being in contact with the upper surface of the semiconductor substrate in the element region;
a lower electrode (Fig. 2, element 24, paragraph 0041) being in contact with a lower surface of the semiconductor substrate in both of the element region and the peripheral region;
an insulation layer (Fig. 2, element 20, paragraph 0041) covering a side surface and a bottom surface of the recess; and
a field plate (Fig. 2, element 18, paragraph 0041) extending from the upper electrode to an upper portion of the peripheral region, the field plate being on a side of the insulation layer opposite to the side surface and the bottom surface of the recess with the insulation layer interposed between the field plate and each of the side surface and the bottom surface of the recess,
wherein the semiconductor substrate includes:
a high-concentration layer (Fig. 2, element 32, paragraph 0043) being an n-type layer and extending from the element region to the peripheral region, the high-concentration layer being in contact with the lower electrode, the high-concentration layer having a thick plate portion and a thin plate portion, an upper surface of the thick plate portion protruding further than an upper surface of the thin plate portion, the thick plate portion located in the element region, the thin plate portion extending from the element region to the peripheral region (Fig. 2);
a drift layer (Fig. 2, element 34, paragraph 0043) being an n-type layer and located in the element region, the drift layer being in contact with the upper surface of the thick plate portion, the drift layer having a lower n-type impurity concentration than the high-concentration layer; and
a low-concentration layer (Fig. 2, element 36, paragraph 0043) being an n-type layer and extending from the element region to the peripheral region, the low-concentration layer being in contact with a side surface of the drift layer, the low-concentration layer being in contact with the upper surface of the thin plate portion, the low-concentration layer being in contact with a side surface of a stepped portion located at a boundary between the thick plate portion and the thin plate portion, the low-concentration layer being in contact with the insulation layer at the side surface and the bottom surface of the recess, the low-concentration layer having a lower n-type impurity concentration than the drift layer (Fig. 2),
the drift layer is connected to the upper electrode through at least one of a p-n junction or a Schottky barrier junction (Fig. 2, paragraph 0057),
a cross section of the semiconductor substrate perpendicularly intersects the stepped portion, the cross section of the semiconductor substrate includes a quadrilateral region surrounded by the side surface of the stepped portion, a first virtual line, the upper surface of the thin plate portion, and a second virtual line, the first virtual line is at a location shifted from the side surface of the stepped portion toward the peripheral region by a distance identical to a height of the stepped portion, the second virtual line is at a location shifted upward from the upper surface of the thin plate portion by a distance identical to the height of the stepped portion (Fig. 2, the quadrilateral region and the virtual lines can be formed as the claimed structure of the prior art is analogous to the instant application), and
a half or more of the quadrilateral region is not depleted in a case where an electric potential of the lower electrode with respect to the upper electrode is raised to a level causing an avalanche breakdown in the semiconductor substrate (This is an intended use recitation. The examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. See, e.g., In re Schreiber, 128 F.3d 1473, 1477, 44 USPQ2d 1429, 1431 (Fed. Cir. 1997); In re Otto, 136 USPQ 458,459 (CCPA 1963)).
Regarding claim 2, Nagaoka et al. teach wherein the low-concentration layer includes a region below a straight line that forms an angle of 45 degrees with the side surface of the stepped portion and extends from an upper end of the stepped portion to the upper surface of the thin plate portion (Fig. 2, the claimed structure of the prior art is analogous to the instant application), and the region below the straight line is not depleted in a case where the electric potential of the lower electrode with respect to the upper electrode is raised to the level causing the avalanche breakdown in the semiconductor substrate (This is an intended use recitation. The examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. See, e.g., In re Schreiber, 128 F.3d 1473, 1477, 44 USPQ2d 1429, 1431 (Fed. Cir. 1997); In re Otto, 136 USPQ 458,459 (CCPA 1963)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813