DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6 and 9-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/08/2025.
Applicant’s election without traverse of Device Embodiment 7 in the reply filed on 12/08/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7, 11-12 and 14-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawasaki et al. (US 2020/0312765 A1, hereinafter Kawasaki ‘765).
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With respect to Claim 1 Kawasaki ‘765 discloses a semiconductor device (Fig. 1-5B, 20-38B and 65A-67) comprising:
a first conductive plate structure (6 of 1000A, Fig 2A and Fig. 32, Para [0113] discloses memory plane 1000A and Para [0228] discloses 6 as part of that memory plane, first conductive plate structure hereinafter FCPS) and a second conductive plate structure (6 of 1000B, Fig 2A and Fig. 32, Para [0113] discloses memory plane 1000B and Para [0228] discloses 6 as part of that memory plane, second conductive plate structure hereinafter SCPS), arranged at a same vertical level (Para [0113 and 0114] disclose FCPS and SCPS formed on chip arranged on a wafer) on a semiconductor chip (2000, Fig 2A, Para [0113]) and spaced apart horizontally from each other (Fig. 2A discloses FCPS and SCPS spaced apart on chip 2000) on the semiconductor chip (2000);
a first structure (structure of 1000A disclosed in Para [0116], hereinafter FS, Para [0116] discloses 1000A contains memory array (100), staircase region (300) and bit lines and word lines, which examiner notes is the structure of first structure (ST1a) and second structure (ST2a) of the instant application) on the first conductive plate structure (FCPS) and including first separation structures (79 of 1000A, Fig. 38B, Para [0294], hereinafter FSS)(Note: Para [0145] discloses multiple instance of the exemplary structure maybe replicated therefore Kawasaki ‘765 describes a structure used in the first and second structure) and first memory blocks (B1, Fig. 2A, Para [0119]); and
a second structure (structure of 1000B disclosed in Para [0116] hereinafter SS, Para [0116] discloses 1000B contains memory array (100), staircase region (300) and bit lines and word lines, which examiner notes is the structure of first structure (ST1a) and second structure (ST2a) of the instant application) on the second conductive plate structure (SCPS) and including second separation structures (79 of 1000B, Fig. 38B, Para [0294], hereinafter SSS) (Note: Para [0145] discloses multiple instance of the exemplary structure maybe replicated therefore Kawasaki ‘765 describes a structure used in the first and second structure) and second memory blocks (B2, Fig. 2A, Para [0119]),
wherein the first memory blocks (B1) are spaced apart from each other (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) by the first separation structures (FSS), and extend in parallel (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) to each other in a first horizontal direction (hd1, Fig 2A, Para [0110]),
wherein the second memory blocks (B2) are spaced apart from each other (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) by the second separation structures (SSS), and extend in parallel (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) to each other in a second horizontal direction (hd2, Fig 2A, Para [0110]), and
wherein the first (hd1) and second horizontal directions (hd2) are parallel to an upper surface (top of layer 280 as shown in Fig. 38A and 38B and disclosed in Para [0111]) of the first conductive plate structure (FCPS), and are perpendicular to each other (disclosed in Fig 2A and Para [0110]).
With respect to Claim 2 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 1, and Kawasaki ‘765 further discloses
wherein the first conductive plate structure (FCPS) includes a first common source (114 of FCPS, Fig 35E, Para [0299]),
wherein the second conductive plate structure (SCPS) includes a second common source (114 of SCPS, Fig 35E, Para [0299]),
wherein each of the first memory blocks (B1) includes:
first word lines (146/246 of FCPS, Fig 38A, Para [0314]) spaced apart from each other in a vertical direction (146/246 spaced apart from each other in a vertical direction disclosed in Fig 38A); and
first vertical memory structures (55 of FCPS, Fig 38A, Para [0288]) that extend through (shown in Fig 38A) the first word lines (146/246 of FCPS) and electrically connected (through layer 114 of structure 110 as disclosed in Fig 35E and Para [0299]) to the first common source (114 of FCPS), and wherein each of the second memory blocks (B2) includes:
second word lines (146/246 of SCPS, Fig 38A, Para [0314]) spaced apart from each other in the vertical direction (146/246 spaced apart from each other in a vertical direction disclosed in Fig 38A); and
second vertical memory structures (55 of SCPS, Fig 38A, Para [0288]) that extend through (shown in Fig 38A) the second word lines (146/246 of SCPS) and electrically connected (through layer 114 of structure 110 as disclosed in Fig 35E and Para [0299]) to the second common source (114 of SCPS).
With respect to Claim 7 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 2, and Kawasaki ‘765 further discloses
wherein each of the first memory blocks (B1) has a first memory cell array region (100 of B1, Fig 34, Para [0116]) and a first extension region (200 of B1, Fig 34, Para [0236]) that are adjacent to each other in the first horizontal direction (Fig 33B discloses 100 and 200 adjacent to each other in the hd1 direction),
wherein each of the second memory blocks (B2) has a second memory cell array region (100 of B2, Fig 34, Para [0116]) and a second extension region (200 of B2, Fig 34, Para [0236]) that are adjacent to each other in the second horizontal direction (Fig 33B discloses 100 and 200 adjacent to each other in the hd1 direction),
wherein the first vertical memory structures (55 of FCPS) extend through the first word lines (146/246 of FCPS) in the first memory cell array region (100 of B1)(Fig 34 disclose vertical memory structures extending through word lines in memory cell array region),
wherein the second vertical memory structures (55 of SCPS) extend through the second word lines (146/246 of SCPS) in the second memory cell array region (100 of B2)(Fig 34 disclose vertical memory structures extending through word lines in memory cell array region),
wherein the first word lines (146/246 of FCPS) include first word line pads (a top surface of a respective one of the electrically conductive layers 146, 246, Fig 66A and Para [0367], hereinafter FWLP) arranged to have a stair shape (disclosed in Fig 66A and Para [0367]) in the first extension region (200 of B1), and
wherein the second word lines (146/246 of SCPS) include second word line pads (a top surface of a respective one of the electrically conductive layers 146, 246, Fig 66A and Para [0367], hereinafter SWLP) arranged to have a stair shape (disclosed in Fig 66A and Para [0367]) in the second extension region (200 of B2).
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With respect to Claim 11 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 1, and Kawasaki ‘765 discloses further comprising:
a third conductive plate structure (6 of rightmost 1000B, as shown in annotated Fig 2A of Kawasaki ‘765 and Fig. 32, Para [0113] discloses memory plane 1000B and Para [0228] discloses 6 as part of that memory plane, first conductive plate structure hereinafter TCPS) on the semiconductor chip (2000, Para [0110] discloses multiple 1000A/1000B on chip);
a fourth conductive plate structure (6 of rightmost 1000A, as shown in annotated Fig 2A of Kawasaki ‘765 and Fig. 32, Para [0113] discloses memory plane 1000A and Para [0228] discloses 6 as part of that memory plane, first conductive plate structure hereinafter 4CPS) on the semiconductor chip (2000, Para [0110] discloses multiple 1000A/1000B on chip);
a third structure (structure of 1000B disclosed in Para [0116] hereinafter TS, Para [0116] discloses 1000B contains memory array (100), staircase region (300) and bit lines and word lines, which examiner notes is the structure of first structure (ST1a) and second structure (ST2a) of the instant application) on the third conductive plate structure (TCPS) and including third separation structures (79 of 1000B, Fig. 38B, Para [0294], hereinafter TSS) (Note: Para [0145] discloses multiple instance of the exemplary structure maybe replicated therefore Kawasaki ‘765 describes a structure used in the first and second structure) and third memory blocks (B2 of rightmost 1000B, Fig. 2A, Para [0119]); and
a fourth structure (structure of 1000A disclosed in Para [0116], hereinafter FS, Para [0116] discloses 1000A contains memory array (100), staircase region (300) and bit lines and word lines, which examiner notes is the structure of first structure (ST1a) and second structure (ST2a) of the instant application) on the fourth conductive plate structure (4CPS) and including fourth separation structures (79 of 1000A, Fig. 38B, Para [0294], hereinafter 4SS)(Note: Para [0145] discloses multiple instance of the exemplary structure maybe replicated therefore Kawasaki ‘765 describes a structure used in the first and second structure) and fourth memory blocks (B1 of rightmost 1000A, Fig. 2A, Para [0119]) ,
wherein the third memory blocks (B2 of rightmost 1000B, Fig. 2A) are spaced apart from each other (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) by the third separation structures (TSS), and extend in parallel to each other (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765),
wherein the fourth memory blocks (B1 of rightmost 1000A, Fig. 2A) are spaced apart from each other (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) by the fourth separation structures (4SS), and extend in parallel to each other (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765),
wherein the first to fourth conductive plate structures (FCPS/SCPS/TCPS/4CPS) are spaced apart from each other (disclosed in annotated Fig 2A of Kawasaki ‘765), and
wherein the first to fourth structures (FS/SS/TS/4S) are spaced apart from each other (disclosed in annotated Fig 2A of Kawasaki ‘765, FS/SS/TS/4S are part of FCPS/SCPS/TCPS/4CPS which are separated as shown in annotated Fig 2A of Kawasaki ‘765, therefore FS/SS.TS/4S are also separated).
With respect to Claim 12 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 11, and Kawasaki ‘765 further discloses
wherein the first (FCPS) and second conductive plate structures (SCPS) are adjacent to each other in the second horizontal direction (hd2)(position disclosed in annotated Fig 2A of Kawasaki ‘765),
wherein the third (TCPS) and fourth conductive plate structures ($CPS) are adjacent to each other in the second horizontal direction (hd2)(position disclosed in annotated Fig 2A of Kawasaki ‘765),
wherein the first (FCPS) and third conductive plate structures (TCPS) are adjacent to each other in the first horizontal direction (hd1) (position disclosed in annotated Fig 2A of Kawasaki ‘765),
wherein the second (SCPS) and fourth conductive plate structures (4CPS) are adjacent to each other in the first horizontal direction (hd1) (position disclosed in annotated Fig 2A of Kawasaki ‘765),
wherein each of the third memory blocks (B2 of rightmost 1000B, Fig. 2A) extends in the second horizontal direction (hd2)(Fig 2A discloses B2 runs in the hd2 direction), and
wherein each of the fourth memory blocks (B1 of rightmost 1000B, Fig. 2A) extends in the first horizontal direction (hd1) (Fig 2A discloses B1 runs in the hd1 direction).
With respect to Claim 14 Kawasaki ‘765 discloses a semiconductor device (Fig. 1-5B, 20-38B and 65A-67) comprising:
first word lines (146/246 in structure 1000A (Para [0113]), Fig 38A, Para [0314]) stacked in a vertical direction (146/246 spaced apart from each other in a vertical direction disclosed in Fig 38A) and spaced apart from each other (Fig 38A and Para [0314] discloses 146/246 spaced apart from each other by structures 132/232), the first word lines (146/246 in structure 1000A) extending in a first horizontal direction (hd2, Para [0118] discloses first word lines extending in hd2);
second word lines (146/246 in structure 1000B (Para [0113]), Fig 38A, Para [0314]) stacked in the vertical direction (146/246 spaced apart from each other in a vertical direction disclosed in Fig 38A), spaced apart from each other (Fig 38A and Para [0314] discloses 146/246 spaced apart from each other by structures 132/232), and at the same level as the first word lines (Para [0113 and 0114] disclose 1000A and 1000B formed on chip arranged on a wafer, word lines of 1000A and 1000B are part of 1000A and 1000B, therefore they are on the same level), the second word lines (146/246 in structure 1000B) extending in a second horizontal direction (hd1)(Para [0118] discloses second word lines extending in hd1) that is perpendicular to the first horizontal direction (hd2)(hd2 perpendicular to hd1, disclosed in Fig 2A and Para [0110]);
a first vertical memory structure (55 of 1000A, Para [0113] discloses memory plane 1000A and Fig 38A, Para [0288] disclose 55 as part of memory structure), extending through the first word lines (146/246 in structure 1000A), in the vertical direction (146/246 spaced apart from each other in a vertical direction disclosed in Fig 38A);
a second vertical memory structure (55 of 1000B, Para [0113] discloses memory plane 1000B and Fig 38A, Para [0288] disclose 55 as part of memory structure), extending through the second word lines (146/246 in structure 1000B), in the vertical direction (146/246 spaced apart from each other in a vertical direction disclosed in Fig 38A);
a first bit line (bd (bit lines of 1000A), Fig 2A, Para [0117]), electrically connected to the first vertical memory structure (55 of 1000A)(electrical connection disclosed in Para [0116]), on the first vertical memory structure (55 of 1000A)(Para [0116] discloses bit lines connect to vertical semiconductor channels); and
a second bit line (bd (bit lines of 1000B), Fig 2A, Para [0117]), electrically connected to the second vertical memory structure (55 of 1000B)(electrical connection disclosed in Para [0116]), on the second vertical memory structure (55 of 1000B)(Para [0116] discloses bit lines connect to vertical semiconductor channels).
With respect to Claim 15 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 14, and Kawasaki ‘765 further discloses
wherein the first bit line (bd (bit lines of 1000A) extends in the second horizontal direction (hd1)(disclosed in Fig 2A (lower left image)), and
wherein the second bit line (bd (bit lines of 1000B) extends in the first horizontal direction (hd2)(disclosed in Fig 2A (lower left image)).
With respect to Claim 16 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 14, and Kawasaki ‘765 discloses further comprising:
a first conductive plate structure (6 of 1000A, Fig 2A and Fig. 32, Para [0113] discloses memory plane 1000A and Para [0228] discloses 6 as part of that memory plane, first conductive plate structure hereinafter FCPS) including a first common source (114 of FCPS, Fig 35E, Para [0299]); and
a second conductive plate structure (6 of 1000B, Fig 2A and Fig. 32, Para [0113] discloses memory plane 1000B and Para [0228] discloses 6 as part of that memory plane, second conductive plate structure hereinafter SCPS) including a second common source (114 of SCPS, Fig 35E, Para [0299]),
wherein the first vertical memory structure (55 of 1000A) includes a first channel layer (60 of FCPS, Fig 35D, Para [0299]) that is electrically connected (disclosed in Para [0299]) to the first common source (114 of FCPS), and
wherein the second vertical memory structure (55 of 1000B) includes a second channel layer (60 of SCPS, Fig 35D, Para [0299]) that is electrically connected (disclosed in Para [0299]) to the second common source (114 of SCPS).
With respect to Claim 17 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 16, and Kawasaki ‘765 further discloses
wherein the first conductive plate structure (FCPS) and the second conductive plate structure (SCPS) are spaced apart from each other in either the first (hd2) or second horizontal direction (hd1)(Fig 2A discloses 1000A and 1000B separated from each other in hd1 direction, FCPS is part of 1000A and SCPS is part of 1000B).
With respect to Claim 18 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 14, and Kawasaki ‘765 discloses further comprising:
a structure (structure of Fig 21A, described in Para [0237 and 0238]) including a peripheral circuit (700, Fig 21A, Para [0116]),
wherein the structure (FS) vertically overlaps the first (146/246 in structure 1000A) and second word lines (146/246 in structure 1000B)(Fig 36 discloses structure of Fig 21A, described in Para [0237 and 0238] vertically overlaps word lines 146/246).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki ‘765 in view of Yeh et al. (US 2021/0335804 A1, hereinafter Yeh ‘804), in view of the following arguments.
With respect to Claim 3 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 2, and Kawasaki ‘765 discloses further comprising
a peripheral circuit structure (700, Fig 21A, Para [0116]) that vertically overlaps the first (FS as described above) and second structures (SS as described above)(structures of FS (1000A) and SS (1000B) vertically overlapping 700 disclosed in Fig 32 of Kawasaki ‘765),
a first transistor circuit region (710 of 1000A, Fig 21A, Para [0238]) including first transistors (742 of 1000A, Fig 21A, Para [0238]) electrically connected (disclosed in Para [0238]) to the first word lines (146/246 of 1000A); and a second transistor circuit region (710 of 1000B, Fig 21A, Para [0238]) including second transistors (742 of 1000B, Fig 21A, Para [0238]) electrically connected (disclosed in Para [0238]) to the second word lines (146/246 of 1000A).
But Kawasaki ‘765 fails to explicitly disclose wherein the transistor is a pass transistor.
Nevertheless, in a related endeavor (Fig 1A-11 of Yeh ‘804), Yeh ‘804 teaches a pass transistor (840, Fig 1A of Yeh ‘804, Para [0023]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yeh ‘804’s teaching of using a pass transistor into Kawasaki ‘765’s device. Kawasaki ‘765 and Yeh ‘804 both teach NAND memory devices and Yeh ‘804 teaches using a pass transistor to pass or block word line voltage from reaching the word lines in the memory array (Para [0023] of Yeh ‘804. Therefore the person of ordinary skill in the art would have been motivated to use the teaching of a pass transistor to achieve the well-known advantage of having to use fewer transistors in the device.
As incorporated, pass transistor (804) taught by Yeh ‘804 would be used as the first and second transistors (742) of Kawasaki ‘765 .
With respect to Claim 4 Kawasaki ‘765 as modified by Yeh ‘804 discloses all limitations of the semiconductor device of claim 3, and Kawasaki ‘765 as modified by Yeh ‘804 further discloses
wherein the first pass transistor circuit region (710 of 1000A of Kawasaki ‘765 as modified by Yeh ‘804), and
wherein the second pass transistor circuit region (710 of 1000B of Kawasaki ‘765 as modified by Yeh ‘804)
But Kawasaki ‘765 as modified by Yeh ‘804 fails to explicitly disclose the first transistor circuit region has a shape that is elongated in the second horizontal direction and the second transistor circuit region has a shape that is elongated in the first horizontal direction.
However, the examiner notes that in the applicants disclosure teaches wherein the recited device orientation has the advantage of “the first memory blocks MB1a and the second memory blocks MB2a may extend in directions, perpendicular to each other, thereby minimizing warpage of the semiconductor device 1aa. Accordingly, defects of the semiconductor device 1aa caused by warpage may be prevented, and the semiconductor device 1aa may have improved reliability due to the minimized warpage”. Having this mind, Kawasaki ‘765 teaches “methods for wafer warpage reduction through stress balancing by using rotated memory blocks including three-dimensional memory devices and structures formed by the same…”. Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation through routine optimization, to obtain the well-known advantage of reducing warpage by rotating the memory blocks on the semiconductor device. See MPEP§2144.05 (II)(A),(B).
Therefore, as memory blocks are rotated, as described above, the first pass transistor circuit region has a shape that is elongated in the second horizontal direction and the second pass transistor circuit region has a shape that is elongated in the first horizontal direction.
With respect to Claim 5 Kawasaki ‘765 as modified by Yeh ‘804 discloses all limitations of the semiconductor device of claim 3, and Kawasaki ‘765 further discloses
wherein the first conductive plate structure (FCPS) is between the peripheral circuit structure (700) and the first structure (FS)(Fig 34 discloses FCPS(6) between 700 and FS), and
wherein the second conductive plate structure (SCPS) is between the peripheral circuit structure (700) and the second structure (SS)(Fig 34 discloses FCPS(6) between 700 and FS).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki ‘765 in view of Oh et al. (US 10,896,918 B1, hereinafter Oh ‘918), in view of the following arguments.
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With respect to Claim 8 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 2, and Kawasaki ‘765 further discloses
wherein each of the first memory blocks (B1) has first memory cell array regions (100 of B1) that are spaced apart from each other (Fig 38B discloses 100 spaced apart from each other and Fig 2A and Para [0125] discloses B1, and therefore the memory cell arrays 100, extend in the hd1 direction) in the first horizontal direction (hd1), and a first extension region (200 of B1, Fig 34, Para [0236])
wherein each of the second memory blocks (B2) has second memory cell array regions (100 of B2) that are spaced apart from each other (Fig 38B discloses 100 spaced apart from each other and Fig 2A and Para [0125] discloses B1, and therefore the memory cell arrays 100, extend in the hd2 direction) in the second horizontal direction (hd2), and a second extension region (200 of B2, Fig 34, Para [0236]),
wherein the first extension region (200 of B1) includes a first connection region (connection region of 200 as shown in annotated Fig 65B of Kawasaki ‘765) and a first stair region (first stair region of 200 as shown in annotated Fig 65B of Kawasaki ‘765),
wherein the second extension region (200 of B2) includes a second connection region (connection region of 200 as shown in annotated Fig 65B of Kawasaki ‘765) and a second stair region (second stair region of 200 as shown in annotated Fig 65B of Kawasaki ‘765),
wherein the first vertical memory structures (55 of FCPS) extend through the first word lines (146/246 of FCPS) in the first memory cell array regions (100 of B1)(disclosed in Fig 65A),
wherein the second vertical memory structures (55 of SCPS) extend through the second word lines (146/246 of SCPS) in the second memory cell array regions (100 of B2)(disclosed in Fig 65A),
wherein the first word lines (146/246 of FCPS) continuously extend (disclosed in Fig 65A) in the first memory cell array regions (100 of B1) and the first connection region (connection region of 200 as shown in annotated Fig 65B of Kawasaki ‘765 and in Fig 65A),
wherein the first word lines (146/246 of FCPS) include first word line pads (a top surface of a respective one of the electrically conductive layers 146, 246, Fig 66A and Para [0367], hereinafter FWLP) arranged to have a stair shape (disclosed in Fig 66A) in the first stair region (first stair region of 200 as shown in Fig 65A and annotated Fig 65B of Kawasaki ‘765),
wherein the second word lines (146/246 of SCPS) continuously extend (disclosed in Fig 65A) in the second memory cell array regions (100 of B2) and the second connection region (connection region of 200 as shown in annotated Fig 65B of Kawasaki ‘765 and Fig 65A), and
wherein the second word lines (146/246 of SCPS) include second word line pads (a top surface of a respective one of the electrically conductive layers 146, 246, Fig 66A and Para [0367], hereinafter SWLP) arranged to have a stair shape (disclosed in Fig 66A) in the second stair region (second stair region of 200 as shown in Fig 66A and annotated Fig 65B of Kawasaki ‘765).
But Kawasaki ‘765 fails to explicitly disclose the extension region between the memory cell array regions.
Nevertheless, in a related endeavor (Fig 3 of Oh ‘918), Oh ‘918 teaches the extension region (CNR, Fig 3 of Oh ‘918, Col 6, Lines 21-30) between the memory cell array regions (CAR1 and CAR2, Fig 3 of Oh ‘918, Lines 21-30).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Oh ‘918’s teaching of the extension region between the memory cell array regions into Kawasaki ‘804’s device. The ordinary artisan would have been motivated to modify Kawasaki ‘804 in the manner set forth above, at least, incorporating a connection area between two memory cell array regions would enable additional functionality to the device by allowing control of two memory cell arrays with one control transistor.
As incorporated, the teaching of Oh ‘918 of having an extension region (CNR) between the memory cell array regions (CAR1/CAR2) would be used between memory cells ((100 of B1 and 100 of B2) of Kawasaki ‘765.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki ‘765, in view of the following arguments.
With respect to Claim 13 Kawasaki ‘765 discloses all limitations of the semiconductor device of claim 1, and Kawasaki ‘765 further discloses
wherein the first structure (FS) further includes first bit lines (bd of 1000A structure shown in Fig 2A and disclosed in Para [0117]) that cross the first memory blocks (B1, Fig. 2A, Para [0119], Para [0117] discloses bit lines (bd) cross memory blocks), on the first memory blocks (B1)(Para [0117] discloses 1000A contains bit lines bd),
wherein the second structure (SS) further includes second bit lines (bd of 1000B structure shown in Fig 2A and disclosed in Para [0117]) that cross the second memory blocks (B2, Fig. 2A, Para [0119], Para [0117] discloses bit lines (bd) cross memory blocks), on the second memory blocks (B1)(Para [0117] discloses 1000B contains bit lines bd),
And in an further embodiment, Kawasaki ‘765 further discloses wherein each of the first bit lines (bd of 1000A structure) extends in the second horizontal direction (hd2)(Para [0118] discloses bit lines of 1000A run in the hd2 direction), and wherein each of the second bit lines (bd of 1000B structure) extends in the first horizontal direction (hd1) (Para [0118] discloses bit lines of 1000A run in the hd1 direction).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Kawasaki ‘765’s further teaching of wherein each of the first bit lines extends in the second horizontal direction, and wherein each of the second bit lines extends in the first horizontal direction into Kawasaki ‘765’s device. The ordinary artisan would have been motivated to modify Pu ‘864 in the manner set forth above, at least, because this design flexibility would enable the alternating placement directions taught by Kawasaki ‘765 that can minimize warpage as taught in Para [0105] of Kawasaki ‘765
As incorporated, the first bit lines (bd of 1000A structure) extends in the second horizontal direction (hd2), and wherein each of the second bit lines (bd of 1000B structure) extends in the first horizontal direction (hd1) would be used as the bit line directions of Kawasaki ‘765’ device.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki ‘765 in view of Lin et al. (US 2020/0118630 A1, hereinafter Lin ‘630), in view of the following arguments.
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With respect to Claim 19 Kawasaki ‘765 discloses all limitations of the data storage system (Fig. 1-5B, 20-38B and 65A-67) comprising:
a semiconductor device (2000, Fig 2B, Para [0127]) including an input/output pad (400, Fig 2B, Para [0127]); and
wherein the semiconductor device (2000) includes:
a first conductive plate structure (6 of 1000A, Fig 2A and Fig. 32, Para [0113] discloses memory plane 1000A and Para [0228] discloses 6 as part of that memory plane, first conductive plate structure hereinafter FCPS) and a second conductive plate structure (6 of 1000B, Fig 2A and Fig. 32, Para [0113] discloses memory plane 1000B and Para [0228] discloses 6 as part of that memory plane, second conductive plate structure hereinafter SCPS), arranged at the same level (Para [0113 and 0114] disclose FCPS and SCPS formed on chip arranged on a wafer) on a semiconductor chip (2000, Fig 2A, Para [0113]) and spaced apart horizontally from each other (Fig. 2A discloses FCPS and SCPS spaced apart on chip 2000) on the semiconductor chip (2000);
a first structure (structure of 1000A disclosed in Para [0116], hereinafter FS, Para [0116] discloses 1000A contains memory array (100), staircase region (300) and bit lines and word lines, which examiner notes is the structure of first structure (ST1a) and second structure (ST2a) of the instant application) on the first conductive plate structure (FCPS) and including first separation structures (79 of 1000A, Fig. 38B, Para [0294], hereinafter FSS)(Note: Para [0145] discloses multiple instance of the exemplary structure maybe replicated therefore Kawasaki ‘765 describes a structure used in the first and second structure) and first memory blocks (B1, Fig. 2A, Para [0119]); and
a second structure (structure of 1000B disclosed in Para [0116] hereinafter SS, Para [0116] discloses 1000B contains memory array (100), staircase region (300) and bit lines and word lines, which examiner notes is the structure of first structure (ST1a) and second structure (ST2a) of the instant application) on the second conductive plate structure (SCPS) and including second separation structures (79 of 1000B, Fig. 38B, Para [0294], hereinafter SSS) (Note: Para [0145] discloses multiple instance of the exemplary structure maybe replicated therefore Kawasaki ‘765 describes a structure used in the first and second structure) and second memory blocks (B2, Fig. 2A, Para [0119]),
wherein the first memory blocks (B1) are spaced apart from each other (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) by the first separation structures (FSS), and extend in parallel (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) to each other in a first horizontal direction (hd1, Fig 2A, Para [0110]),
wherein the second memory blocks (B2) are spaced apart from each other (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) by the second separation structures (SSS), and extend in parallel (disclosed in Fig 2A and in detail in annotated Fig 38B of Kawasaki ‘765) to each other in a second horizontal direction (hd2, Fig 2A, Para [0110]), and
wherein the first (hd1) and second horizontal directions (hd2) are parallel to an upper surface (top of layer 280 as shown in Fig. 38A and 38B and disclosed in Para [0111]) of the first conductive plate structure (FCPS), and are perpendicular to each other (disclosed in Fig 2A and Para [0110]).
But Kawasaki ‘765 fails to explicitly disclose a controller electrically connected to the semiconductor device through the input/output pad, the controller configured to control the semiconductor device;
Nevertheless, in a related endeavor (Fig 1 of Lin ‘630), Lin ‘630 teaches a controller (134, Fig 1 of Lin ‘630, Para [0028]) electrically connected (disclosed in Fig 1 of Lin ‘630 and Para [0028]) to the semiconductor device (178, Fig 1 of Lin ‘630, Para [0028]) through the input/output pad (118, Fig 1 of Lin ‘630, Para [0027]), the controller (134) configured to control (disclosed in Para [00028]) the semiconductor device (178).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lin ‘630’s teaching of a controller electrically connected to the semiconductor device through the input/output pad, the controller configured to control the semiconductor device into Kawasaki ‘765’s device. Kawasaki ‘765 teaches a NAND memory structure but is silent on the controls for that device. Lin ‘630 teaches systems for controlling NAND memory structures. The ordinary artisan would have been motivated, then, to use the control teachings of Lin ‘630 in the device of Kawasaki ‘765 because those teachings allow them to incorporate a control system faster than completing the R&D to design a control system for the end device.
As incorporated, the teachings of Lin ‘630 of a controller electrically connected to the semiconductor device through the input/output pad, the controller configured to control the semiconductor device would be incorporated in the device of Kawasaki ‘765 to control that device.
With respect to Claim 20 Kawasaki ‘765 as modified by Lin ‘630 discloses all limitations of the data storage system of claim 19, and Kawasaki ‘765 further discloses
wherein the first structure (FS) further includes first bit lines (bd (bit lines of 1000A), Fig 2A, Para [0117]) that cross the first memory blocks (B1)(disclosed in Fig 2A, lower left image), on the first memory blocks (B1)(disclosed in Para [0117]);
wherein the second structure (SS) further includes second bit lines (bd (bit lines of 1000B), Fig 2A, Para [0117]) that cross the second memory blocks (B2)(disclosed in Fig 2A, lower left image), on the second memory blocks (B2)(disclosed in Para [0117]);
wherein each of the first bit lines (bd (bit lines of 1000A)) extends in the second horizontal direction (hd1)(disclosed in Fig 2A (lower left image)),
wherein each of the second bit lines (bd (bit lines of 1000B)) extends in the first horizontal direction (hd2)(disclosed in Fig 2A (lower left image)),
wherein the first conductive plate structure (FCPS) includes a first common source (114 of FCPS, Fig 35E, Para [0299]),
wherein the second conductive plate structure (SCPS) includes a second common source (114 of SCPS, Fig 35E, Para [0299]),
wherein each of the first memory blocks (B1) includes:
first word lines (146/246 of FCPS, Fig 38A, Para [0314]) that are spaced apart from each other in a vertical direction (146/246 spaced apart from each other in a vertical direction disclosed in Fig 38A); and
first vertical memory structures (55 of FCPS, Fig 38A, Para [0288]), that extend through (shown in Fig 38A) the first word lines (146/246 of FCPS) and electrically connected (through layer 114 of structure 110 as disclosed in Fig 35E and Para [0299]) to the first common source (114 of FCPS), and wherein each of the second memory blocks (B2) includes:
second word lines (146/246 of SCPS, Fig 38A, Para [0314]) spaced apart from each other in the vertical direction (146/246 spaced apart from each other in a vertical direction disclosed in Fig 38A), and
second vertical memory structures (55 of SCPS, Fig 38A, Para [0288]) that extend through (shown in Fig 38A) the second word lines (146/246 of SCPS) and electrically connected (through layer 114 of structure 110 as disclosed in Fig 35E and Para [0299]) to the second common source (114 of SCPS).
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898