Office Action Predictor
Last updated: April 15, 2026
Application No. 18/351,170

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE FOR UPRIGHT MOUNTING

Non-Final OA §102§112
Filed
Jul 12, 2023
Examiner
CHEN, YU
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies Austria AG
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
82%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allow Rate
711 granted / 1052 resolved
At TC average
Moderate +15% lift
Without
With
+14.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
110 currently pending
Career history
1162
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
43.8%
+3.8% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
20.7%
-19.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1052 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of invention Group I, Species I (FIGs. 1A-1F), and Species IA (FIG. 1G), encompassing claims 1-12 (as best understood), in the reply filed on 12/01/2025 is acknowledged. Claims 13-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/01/2025. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “70” in FIG. 1E. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “40” has been used to designate both “lower side surface” and “upper surface” in FIG. 1E. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a lower side face of the first lead, a lower side face of the second lead, and a lower side face of the third lead are arranged within an area of the semiconductor package defined by the mold compound” recited in claim 11 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 reciting “substantially perpendicularly” renders the claim indefinite. The degree and magnitude of perpendicularly that is intended to be covered by “substantially” is unclear. There is no clear indication how much deviation from perpendicularly is allowed to be considered “substantially perpendicularly”. Claim 1 reciting “the first lead provides the output contact pad”, “the second lead provides the low voltage contact pad”, and “the third lead provides the high voltage contact pad” render the claim indefinite. In the claim, the leads and the contact pads are recited as separate structure elements. It unclear what is meant for the leads to provide the contact pads. E.g. how is the first lead related to or different from the output contact pad? How does the first lead provide the output contact pad? Claim 3 reciting “substantially perpendicularly” and “substantially parallel” render the claim indefinite for reasons similar to claim 1 above as to the intended scope of “substantially”. Claim 3 reciting “the first lead has a lower side face ... that provides the output contact pad”, “the second lead has a lower side face that provides the lower voltage contact pad”, and “the third lead has a lower side face that provides the high voltage contact pad” render the claim indefinite for reasons similar to claim 1 above. How do the lower side faces provide the contact pads? Claim 3 reciting “the second lead has a lower side face … that extends substantially perpendicularly to the inner surface” renders the claim indefinite for improper antecedent basis. It is unclear if “the inner surface” pertains to that of the first lead or the second lead. Claim 3 reciting “the third lead has a lower side face … that extends substantially perpendicularly to the inner surface” renders the claim indefinite for improper antecedent basis. It is unclear if “the inner surface” pertains to that of the first lead or the second lead. Claim 4 reciting “the first and second gate leads are arranged in a common plane with second lead and the third lead” renders the claim indefinite. The first and second gate leads pertains to elements 38 and 39 in the elected embodiment shown in FIGs. 1A-1D. As shown in FIG. 1A and 1C, the first gate lead 38 is arranged to be coplanar with the second lead 12 that provides the low voltage contact pad 12, and the second gate lead 39 is arranged to be coplanar with the first lead 27 that provides the output contact pad 14. However, the first and second gate leads 38,39 are not “arranged in a common plane” with both the second lead 28 and the third lead 29. In fact, neither gate leads 38,39 is “arranged in a common plane” as the third lead 29 that provides the high voltage contact pad 13 as shown in FIGs. 1A & 1C. Therefore, it is unclear what constitutes “arranged in a common plane” due to lack of consistent description in the disclosure. Claim 5 reciting “the second gate lead is extends from a plane that is common with the first lead” renders the claim indefinite. Claim 4 previously requires the second gate lead 39 to be arranged in a common plane with the second lead 28 and the third lead 29. Claim 5 further requires the second gate lead to be in a common plane with the first lead 27. However, the first lead 27, the second lead 28, and the third lead 29 are not on a single common plane. The first lead 27 is specifically disclosed to be on a different plane from the second and third leads 28,39. Claim 5 reciting “substantially parallel” renders the claim indefinite for reasons similar to claim 1 above as to the intended scope of “substantially”. Claim 5 reciting “the first gate lead … has a lower side face that provides a second gate pad” renders the claim indefinite for reasons similar to claim 1 above. How does the lower side face provides a second gate pad? Claim 6 reciting “a first control electrode” and “a second control electrode” render the claim indefinite for improper antecedent basis. Claim 4 previously recite “a first control electrode” and “a second control electrode” it is unclear if claim 6 is intended to reference the same control electrodes or recite additional and different control electrodes. Claim 6 reciting “the second major surface of the second transistor device” renders the claim indefinite for lacking antecedent basis. No “second major surface” has been recited previously. It is unclear what is referred to by “the second major surface”. Claim 8 reciting “substantially parallel” renders the claim indefinite for reasons similar to claim 1 above as to the intended scope of “substantially”. Claim 8 reciting “the first gate lead has a lower side face that … provides a first gate contact pad” and “the second gate lead has a lower side face that … provides a second gate contact pad” renders the claim indefinite for reasons similar to claim 1 above. How do the lower side faces provide the gate contact pads? Claim 9 reciting “substantially parallel” renders the claim indefinite for reasons similar to claim 1 above as to the intended scope of “substantially”. Claim 9 reciting “an auxiliary lead .. that has a lower side face … that provides an auxiliary contact pad” renders the claim indefinite for reasons similar to claim 1 above. How does the lower side face of the auxiliary lead provides the auxiliary contact pad? Claim 11 reciting “a lower side face of the first lead, a lower side face of the second lead, and a lower side face of the third lead are arranged within an area of the semiconductor package defined by the mold compound” renders the claim indefinite. It is unclear what constitutes “an area of the semiconductor package defined by the mold compound”. Applicant’s disclosure does not provide clarification. Rather, the specification describes the leads 27,28,29 are “uncovered by the mold compound”, seemingly in contradiction to the claim. Claim 12 reciting “a lower surface of the foot provides a lower side face of the first lead” renders the claim indefinite for reasons similar to claim 1 above. How does the lower surface of the foot provides a lower side face of the first lead? Other claims are rejected for depending on a rejected claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stella US 2013/0003309 A1. PNG media_image1.png 686 1016 media_image1.png Greyscale In re claim 1, as best understood, Stella discloses (e.g. FIGs. 1, 3 & 4) a semiconductor package, comprising: a low voltage contact pad Lsl (FIG. 3A, ¶ 24); a high voltage contact pad Ldh (FIG. 3A, ¶ 24); an output contact pad Lout (FIG. 3A); a half-bridge circuit (see FIG. 1) comprising a first transistor device Ml,405l and a second transistor device Mh,405h coupled in series at an output node Tout (¶ 23-24), wherein the first transistor device Ml,405l has a first major surface (top or bottom surface in FIG. 4C), the second transistor device Mh,405h has a first major surface (top or bottom surface in FIG. 4C), and the first major surface of the first transistor device Ml,405l and of the second transistor device Mh,405h extends “substantially perpendicularly” to the low voltage contact pad Lsl, the high voltage contact pad Ldh, and the output contact pad Lout (e.g. top/bottom main surface of devices 405l,405h are perpendicular to the lateral side surfaces of Lsl,Ldh,Lout); a first lead 315a(450+455)+440out+435out; a second lead 315l(420l+425l)+440sl+435sl; and a third lead 315h(420h+425h); wherein the first and second transistor devices 405l,405h are arranged in a device portion (portion sandwich between 420 and 450) of the semiconductor package and are mounted on the first lead 315a+440out+435out, wherein “the first lead 315a+440out+435out provides the output contact pad Lout” (as best understood, 435out having exposed surface that services as output contact pad Lout) and is arranged on a first side of the device portion (315a on top side shown in FIG. 4C), wherein the second and third leads 315l+440sl+435sl and 315h are arranged in a common plane (see FIG. 4C) on a second side of the device portion (315l,315h on bottom side shown in FIG. 4C) that opposes the first side (top side in FIG. 4C), wherein “the second lead 315l+440sl+435sl provides the low voltage contact pad Lsl (as best understood, 435sl having exposed surface that services as low voltage contact pad Lsl) and the third lead 315h (420h+425h) provides the high voltage contact pad Ldh” (as best understood, 425h having exposed surface that services as high voltage contact pad Ldh). In re claim 2, Stella discloses (e.g. FIG. 4C) wherein: the first transistor device 405l comprises a first power electrode Tsl on the first (bottom) major surface of the first transistor device 405l and a second power electrode Tdl on a second (top) major surface of the first transistor device 405l opposing the first (bottom) major surface of the first transistor device 405l; the second transistor device 405h comprises a first power electrode Tsh on the first (top) major surface of the second transistor device 405h and a second power electrode Tdh on a second (bottom) major surface of the second transistor device 405h opposing the first (top) major surface of the second transistor device 405h; the first lead 315a(450+455)+440out+435out comprises an inner surface (bottom surface of 450 in FIG. 4C), onto which the second power electrode Tdl of the first transistor device 405l and the first power electrode Tsh of the second transistor device 405h are attached; the second lead 315l(420l+425l)+440sl+435sl comprises an inner surface (top surface of 315l in FIG. 4C)) that is attached to the first power electrode Tsl of the first transistor device 405l; and the third lead 315h comprises an inner surface (top surface of 315h in FIG. 4C) that is attached to the second power electrode Tdh of the second transistor device 405h. In re claim 3, as best understood, Stella discloses (e.g. FIGs. 3-4) wherein: the first lead 315a(450+455)+440out+435out has a lower side face (e.g. exposed side face of 435out,Lout shown in FIG. 3B) that extends “substantially perpendicularly” to the inner surface of the first lead (bottom surface of 450 facing 405l,405h in FIG. 4C) and that “provides the output contact pad Lout” (as best understood, 435out having exposed surface that services as output contact pad Lout); the second lead 315l(420l+425l)+440sl+435sl has a lower side face (e.g. exposed side face of 435sl,Lsl shown in FIG. 3B) that provides the low voltage contact pad Lsl (as best understood, 435sl having exposed surface that services as low voltage contact pad Lsl) and that extends “substantially perpendicularly” to “the inner surface” (side face of 435sl is perpendicular to top surface of 315l contacting 405l) and “substantially parallel” to the lower side face of the first lead (side face of 435sl is parallel to side face of 435out); and the third lead 315h(420h+425h) has a lower side face (e.g. side face of 425h) that provides the high voltage contact pad Ldh (as best understood, 425h forms the high voltage contact pad Ldh) and that extends “substantially perpendicularly” to the inner surface (side face of 425h is perpendicular to top surface of 315h contacting 405h) and “substantially parallel” to the lower side face of the first lead (side face of 425h is pralle to side face of 435out). In re claim 4, Stella discloses (e.g. FIGs. 4A-4C) wherein: the first transistor device 405l further comprises a first control electrode Tgl that is arranged on the first major surface of the first transistor device 405l (lower surface in FIG. 4C) and connected to a first gate lead Lgl,440gl+435gl; the second transistor device 405h further comprises a second control electrode Tgh that is arranged on the first major surface of the second transistor device 405h (upper surface in FIG. 4C) and connected to a second gate lead Lgh,440gh+435gh; and “the first and second gate leads Lgl,Lgh are arranged in a common plane with the second lead 315l and the third lead 315h” (see FIG. 4A). In re claim 5, Stella discloses (e.g. FIGs. 4A-4C) wherein the first gate lead Lgl,440gl+435gl is positioned in a cut-out 430 of the second lead 315l (FIG. 4B), and wherein the second gate lead Lgh,445gh+435gh extends from a plane that is common with the first lead 315a (wire lead portion 440gh extends from a common plane with 315a), under the second transistor device 405h (under as viewed in FIG. 4B), and “has a lower side face (exposed side face surface of 435gh,Lgh in FIG. 4B) that provides a second gate pad” Lgh and that extends “substantially parallel” to a lower side face (exposed side face of 425h) of the third lead 315h(420+425h). In re claim 6, as best understood, Stella discloses (e.g. FIG. 4C) wherein the first transistor device 405l comprises “a first control electrode” Tgl arranged on the first major surface of the first transistor device (lower surface of 405l in FIG. 4C), and wherein the second transistor device 405h comprises “a second control electrode” Tgh arranged on “the second major surface” of the second transistor device (as best understood, upper surface of 405h in FIG. 4C). In re claim 7, Stella discloses (e.g. FIG. 4B) wherein the first gate lead Lgl,440gl+435gl is arranged in a cut-out 430 of the second lead 315l and the second gate lead Lgh is arranged in a cut-out of the third lead 315h (the cut-out being a region adjacent the third lead 315h where the third lead is not provided). In re claim 8, as best understood, Stella discloses (e.g. FIGs. 3A) wherein the first gate lead Lgl has a lower side face (upper face of Lgl in FIG. 3A) that extends “substantially parallel” to a lower side face of the second lead (supper face of 315l in FIG. 3A) and “provides a first gate contact pad” Lgl, and wherein the second gate lead Lgh has a lower side face (upper face of Lgh in FIG. 3A) that extends “substantially parallel” to a lower side face of the third lead (upper face of 315h in FIG. 3A) and “provides a second gate contact pad” Lgh. In re claim 9, as best understood, Stella discloses (e.g. FIGs. 4A-4C) wherein the first transistor device 405l and/or the second transistor device 405h further comprises an auxiliary terminal Tgl,Tgh, the semiconductor package further comprising an auxiliary lead (440gl+435gl,Lgl or 440gh+435gh,Lgh) that is mounted on the auxiliary terminal Tgl,Tgh and that has a lower side face (upper face in FIG. 4B) that extends “substantially parallel” to a lower side face of the second lead (upper face of 315l in FIG. 4B) and that “provides an auxiliary contact pad” Lgl,Lgh. In re claim 10, Stella discloses (e.g. FIGs. 3-4) further comprising a mold compound 310 enclosing at least part of the first and second transistor devices 405l,405h and at least part of the first, second, and third leads 315a+440out+435out, 315l+440sl+435sl, 315h. In re claim 11, as best understood, Stella discloses (e.g. FIG. 3A,4B) wherein a lower side face of the first lead 315a+440out+435out, a lower side face of the second lead 315l+440sl+435sl, and a lower side face of the third lead 315h are “arranged within an area of the semiconductor package defined by the mold compound 310” (as best understood, mold compound encloses the entire package). In re claim 12, as best understood, Stella disclose (e.g. FIGs. 4A-4C) wherein the first lead 315a+440out+435out has an L-shape (cantilever 440out having a bent L-shape) having a foot (bent portion of 440out) that extends in a first direction (the bent portion extends vertically, e.g. extending in the downward direction) and perpendicularly to the first major surface (top or bottom surface) of the first transistor device 405l, wherein “a lower surface of the foot provides a lower side face of the first lead” (as best understood, bent portion of 440out has a lower surface which is a lower side face of the first lead), wherein the second lead 315l+440sl+435sl has a L-shape (step from cantilever 440sl to 435sl) having a foot (435sl or Lsl) that extends in a second direction (435sl having vertical extension, e.g. extending in the upward direction) opposing the first direction (downward direction), and wherein the third lead 315h has a L-shape (step from 420h to 425h) having a foot 425h that extends parallel to the second direction (425h having vertical extension, e.g. extending in the upward direction). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896
Read full office action

Prosecution Timeline

Jul 12, 2023
Application Filed
Aug 02, 2023
Response after Non-Final Action
Jan 14, 2026
Non-Final Rejection — §102, §112
Apr 02, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
82%
With Interview (+14.9%)
2y 10m
Median Time to Grant
Low
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