DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 12, 2023 is being considered by the examiner.
Election/Restrictions
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on October 28, 2025.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: THREE-DIMENSIONAL MEMORY DEVICE INCLUDING CAPPED HOLLOW TUBE-SHAPED DRAIN REGIONS.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 10, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rabkin (US 2020/0203381 A1).
Claim 1, Rabkin discloses a semiconductor structure (memory device includes a semiconductor structure, Figs. 26B and 28A) comprising:
an alternating stack (alternating stack 132/142/146, hereinafter, alternating stack 132/146, [0190], Figs. 26B and 28A) of insulating layers (insulating layers 132, [0190], Figs. 26B and 28A) and electrically conductive layers (sacrificial material layers 142 are replaced with electrically conductive layers 146, [0202], Figs. 22A and 26B);
a memory opening (memory opening 49, [0187], Figs. 19A and 22A) vertically extending through the alternating stack 132/146 (memory opening 49 vertically extends through 132/146, [0187], Figs. 19A, 22A, and 26B); and
a memory opening fill structure (memory opening fill structure 58, [0187], Figs. 26B) located in the memory opening 49 and comprising a memory film (tubular ferroelectric dielectric layer 500, hereinafter, memory film 500, [0176], Fig. 26B), a vertical semiconductor channel (two-dimensional electron gas (i.e. 2DEG) channel 60, [0176], Fig. 26B), a dielectric core (dielectric core 62, [0178], Fig. 26B) laterally surrounded by the vertical semiconductor channel 60 (62 is laterally surrounded by 60, [0178], Fig. 26B), and a drain region (drain region 63, [0177], Fig. 26B) overlying the dielectric core 62 and the vertical semiconductor channel 60 (63 is overlying 62 and 60, [0177], Fig. 26B), wherein the drain region 63 comprises an end cap portion (doped semiconducting drain portion 630 is an end cap portion of the drain region, hereinafter, end cap portion of drain region 630, [0187], Figs. 22A and 26B) and a hollow tubular portion (gold layer 634 and titanium layer 632 is a hollow tubular portion of the drain region, hereinafter, hollow tubular portion of drain region 632/634, [0187], Figs. 22A and 26B) vertically protruding downward from the end cap portion 630 and laterally surrounding a top tip portion of the dielectric core 62 (drain region 63 is comprised of an end cap portion 630 and a hollow tubular portion 632/634 vertically protruding downward from the end cap portion 630 and laterally surrounding a top tip portion of the dielectric core 62, [0185]-[0187], Fig. 26B).
Claim 2, Rabkin discloses the semiconductor structure (memory device includes a semiconductor structure, Figs. 26B and 28A) of Claim 1, wherein:
the vertical semiconductor channel 60 comprises a first semiconductor material having a doping (pedestal channel portion 111 is in contact with metal dichalcogenide layer 60L and is a first semiconductor material having a doping of a first conductivity type, hereinafter, first semiconductor material 111/60L, [0152], Fig. 19F) of a first conductivity type (first conductivity type is p-type, [0135]);
the drain region 63 comprises a second semiconductor material 630 having a doping of a second conductivity type (drain region 63 comprises doped semiconductor drain portion 630 which is n-type, hereinafter, second semiconductor material 630, [0177], Fig. 19K) that is an opposite of the first conductivity type (p-type is opposite of n-type); and
a p-n junction between the vertical semiconductor channel 60 and the drain region 63 is located entirely below a horizontal plane including a bottom surface of the end cap portion of the drain region 630 (a p-n junction is between 60 and 63, located entirely below a horizontal plane including a bottom surface of 630, Annotated Fig. 26B).
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Annotated Figs. 21C and 26B (Rabkin) – Illustrates a horizontal plane including a bottom surface of the end cap portion of the drain region 630, wherein a p-n junction between the vertical semiconductor channel 60 and the drain region 63 is located entirely below the horizontal plane
Claim 3, Rabkin discloses the semiconductor structure (memory device includes a semiconductor structure, Figs. 26B and 28A) of Claim 2, wherein the p-n junction is located within a horizontal plane including a bottom surface of the hollow tubular portion of the drain region 632/634 (p-n junction is located within a horizontal plane including a bottom surface of 632, Annotated Figs. 21C and 26B).
Claim 6, Rabkin discloses the semiconductor structure (memory device includes a semiconductor structure, Figs. 26B and 28A) of Claim 2, wherein the hollow tubular portion of the drain region 632/634 comprises an inner portion and an outer portion surrounding the inner portion (632/634 comprises an inner portion 634 disposed within 632, hereinafter, inner portion of hollow tubular portion of the drain region 634 and an outer portion of hollow tubular portion of the drain region 632, [0185], Figs. 21C and 26B).
Claim 10, Rabkin discloses the semiconductor structure (memory device includes a semiconductor structure, Figs. 26B and 28A) of Claim 6, wherein the dielectric core 62 comprises:
a peripheral dielectric core portion (channel-side interfacial dielectric layer 522 is a peripheral dielectric core portion of the structure of the dielectric core 62, [0169], Fig. 19I) comprising a first dielectric material (522 is composed of a first dielectric material, [0169], Fig. 19I); and
a central dielectric core portion (dielectric core 62 is a central dielectric core portion of the structure of the dielectric core 62, [0170], Fig. 19I) comprising a second dielectric material (62 is composed of a second dielectric material, [0170], Fig. 19I) and laterally surrounded by the peripheral dielectric core portion 522 (62 is laterally surrounded by 522, [0171], Fig. 19I).
Claim 13, Rabkin discloses the semiconductor structure (memory device includes a semiconductor structure, Figs. 26B and 28A) of Claim 1, wherein the memory film 500 comprises a layer stack including a tunneling dielectric layer (second ferroelectric dielectric layer 506 is a tunneling dielectric layer, [0245], Fig. 34A), a charge storage layer (first ferroelectric dielectric layer 504 is a charge storage layer, [0244]), and a blocking dielectric layer (ferroelectric-side interfacial dielectric layer 530 is a blocking dielectric layer, [0247], Fig. 34A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Rabkin in view of Zhao (US 2021/0159169 A1).
Claim 4, Rabkin discloses the semiconductor structure (memory device includes a semiconductor structure, Figs. 26B and 28A) of Claim 3.
Rabkin does not explicitly disclose the bottom surface of the hollow tubular portion of the drain region is located below a horizontal plane including a top surface of a topmost electrically conductive layer within the alternating stack; and
the topmost electrically conductive layer comprises a drain side select gate electrode.
However, Zhao in view of Rabkin discloses the bottom surface of the hollow tubular portion of the drain region (Zhao, bottom surface of the drain region 63, [0138], Fig. 15; Rabkin, hollow tubular portion of drain region 632/634, [0187], Figs. 22A and 26B) is located below a horizontal plane including a top surface of a topmost electrically conductive layer within the alternating stack (Zhao, bottom surface of the drain region 63 is located below a horizontal plane including a top surface of a topmost electrically conductive layer 46D within alternating stack of electrically conductive layers 46 and insulating layers 32, [0100] and [0138], Fig. 15; Rabkin, hollow tubular portion of drain region 632/634, [0187], Figs. 22A and 26B); and
the topmost electrically conductive layer comprises a drain side select gate electrode (Zhao, topmost electrically conductive layer 46D comprises a drain side select gate electrode 46D, [0138], Fig. 15; Rabkin, hollow tubular portion of drain region 632/634, [0187], Figs. 22A and 26B). The combination to position the bottom surface of the drain region below the top surface of the drain side select gate electrode enables formation of an optimal p-n junction which can be formed within a horizontal plane along the channel (Zhao, [0138]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to position the bottom surface of the drain region below the top surface of the drain side select gate electrode enables formation of an optimal p-n junction which can be formed within a horizontal plane along the channel (Zhao, [0138]).
Allowable Subject Matter
Claims 5, 7-9, and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Rabkin (US 2020/0203381 A1), Zhao (US 2021/0159169 A1), Cui (US 2021/0305384 A1), fails to disclose the following limitations in combination with the rest of the claim.
Regarding claim 5, wherein the bottom surface of the hollow tubular portion of the drain region is located below a horizontal plane including a bottom surface of the topmost electrically conductive layer.
Regarding claim 7 (from which claims 8-9 depend), wherein the inner portion of the hollow tubular portion of the drain region contains a higher concentration of dopants of the second conductivity type than the outer portion of the hollow tubular portion of the drain region.
Regarding claim 11, the top tip portion of the dielectric core comprises a segment of the central dielectric core portion that protrudes above a horizontal plane including a topmost surface of the peripheral dielectric core portion; and
the top tip portion of the dielectric core comprises a planar top surface that contacts a bottom surface of the end cap portion and a cylindrical sidewall that contacts an inner sidewall of the inner portion of the hollow tubular portion of the drain region.
Regarding claim 12, an inner portion of the bottom surface of the hollow tubular portion of the drain region contacts a top surface of the peripheral dielectric core portion.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cui (US 2021/0305384 A1) discloses a memory film 50 comprises a layer stack (memory stack structure 55) including a tunneling dielectric layer 56, a charge storage layer 54, and a blocking dielectric layer 52 (Cui, [0104], Fig. 7G).
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812