Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 01/06/2026 have been fully considered but they are not persuasive.
The Applicant argues that in regard to claims 1, 11, and 17 that the combination of Yang and Yang’253 prior art, does not teach the limitation of “a first contact connected to the conductive line and that extends in the third direction on the conductive line;
wherein the conductive line in the extension region has first and second regions alternatively arranged in the first direction,
wherein the first contact is connected to the first region, and
wherein the second insulating layer is disposed in the second region.”
In response to this argument, the Examiner directs the applicant’s attention to the combination of Yang and Yang’253 prior art, which teaches the recited limitation as follows:
a first contact (610) connected to the conductive line (221/241/261) and that extends in the third direction on the conductive line (221/241/261) (see Yang’253, Figs.25, 28-29 and 30C as shown below and ¶ [0050]);
wherein the conductive line (221/241/261) in the extension region (SR) has first and second regions alternatively arranged in the first direction (see Yang’253, Figs.25, 28-29 and 30C as shown below and ¶ [0050]),
wherein the first contact (610) is connected to the first region (see Yang’253, Figs.25, 28-29 and 30C as shown below and ¶ [0050]), and
wherein the second insulating layer (235/255/275/251/232/271/272) is disposed in the second region (see Yang’253, Figs.25, 28-29 and 30C as shown below and ¶ [0050]).
In addition, during patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). While the claims of issued patents are interpreted in light of the specification, prosecution history, prior art and other claims, this is not the mode of claim interpretation to be applied during examination. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004) (The USPTO uses a different standard for construing claims than that used by district courts; during examination the USPTO must give claims their broadest reasonable interpretation.) This means that the words of the claim must be given their plain meaning unless applicant has provided a clear definition in the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) >; Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004).
The Examiner would further point out that “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). Therefore, the combination of Yang and Yang’253 prior art reference does meet all the limitation in claims 1, 11, and 17.
Allowable Subject Matter
Claim 5 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the second insulating layer is not disposed in the first region,” as recited in claim 5.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the first contact is not formed in the second region, and
more of the sacrificial layer is removed from the first region than from the second region”, as recited in claim 19.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein a length of the sacrificial layer removed from the extension region is less than or equal to a sum of a length of the sacrificial layer removed to form the first conductive pattern in the cell region and a length of the sacrificial layer removed to form the second conductive pattern in the cell region”, as recited in claim 20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-7, and 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. 2022/0285395 A1, hereinafter refer to Yang) in view of Yang et al. (U.S. 2022/0037253 A1, hereinafter refer to Yang’253).
Regarding Claim 1: Yang discloses a semiconductor device (see Yang, Figs.3-4 and 14 as shown below and ¶ [0010]), comprising:
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a substrate (118) that extends in first and second directions that cross each other (see Yang, Fig.14 as shown above);
first and second insulating layers (104/114) alternately stacked on the substrate (118) in a third direction that crosses the first and second directions (see Yang, Figs.3-4 and 14 as shown above);
a conductive line (WL) disposed on one sidewall of the second insulating layer (114) in the second direction (see Yang, Fig.14 as shown above);
a conductive pillar (BL-2) that extends in the third direction and penetrates through the first insulating layer (104) (see Yang, Fig.14 as shown above);
a semiconductor layer (108) disposed on one sidewall of the conductive pillar (BL-2) and that extends in the third direction (see Yang, Fig.14 as shown above and ¶ [0020]); and
a ferroelectric layer (106) disposed between the conductive line (WL) and the semiconductor layer (108) and that extends in the third direction (see Yang, Fig.14 as shown above and ¶ [0020]),
wherein the conductive line (WL) includes first (WL1-2) and second (WL1-2’) conductive patterns spaced apart from each other in the second direction, and the second insulating layer (114) is disposed between the first (WL1-2) and second (WL1-2’) conductive patterns (see Yang, Fig.14 as shown above and ¶ [0020]).
Yang is silent upon explicitly disclosing wherein the substrate includes a cell region and an extension region that extends from the cell region in the first direction;
a first contact connected to the conductive line and that extends in the third direction on the conductive line;
wherein the conductive line in the extension region has first and second regions alternatively arranged in the first direction,
wherein the first contact is connected to the first region, and
wherein the second insulating layer is disposed in the second region.
Before effective filing date of the claimed invention the disclosed substrate were known to include a cell region and an extension region that extends from the cell region in the first direction in order to electrically connect the conductive lines and reduce the overall footprint of the array of memory cells.
For support see Yang’253, which teaches wherein the substrate (100) includes a cell region (CR) and an extension region (SR) that extends from the cell region (CR) in the first direction (see Yang’253, Figs.25, 28-29 and 30C as shown below and ¶ [0050]);
a first contact (610) connected to the conductive line (221/241/261) and that extends in the third direction on the conductive line (221/241/261) (see Yang’253, Figs.25, 28-29 and 30C as shown below and ¶ [0050]);
wherein the conductive line (221/241/261) in the extension region (SR) has first and second regions alternatively arranged in the first direction (see Yang’253, Figs.25, 28-29 and 30C as shown below and ¶ [0050]),
wherein the first contact (610) is connected to the first region (see Yang’253, Figs.25, 28-29 and 30C as shown below and ¶ [0050]), and
wherein the second insulating layer (235/255/275/251/232/271/272) is disposed in the second region (see Yang’253, Figs.25, 28-29 and 30C as shown below and ¶ [0050]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teaches of Yang and Yang’253 to enable the Yang substrate to includes a cell region and an extension region that extends from the cell region in the first direction, wherein the conductive line in the extension region to have first and second regions alternatively arranged in the first direction, wherein the first contact to be connected to the first region, and wherein the second insulating layer to be disposed in the second region as taught by Yang’253 in order to electrically connect the conductive lines and reduce the overall footprint of the array of memory cells.
Regarding Claim 2: Yang as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Yang and Yang’253 further teaches wherein the conductive line in the extension region has a different width in the second direction from that of the conductive line in the cell region (see Yang’253, Figs.25 and 28-29 as shown above).
Regarding Claim 3: Yang as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Yang and Yang’253 further teaches wherein the conductive line has a stepwise shape in the extension region (see Yang’253, Figs.25 and 28-29 as shown above), and
the semiconductor device further comprises a first contact (610) connected to the conductive line and that extends in the third direction on the conductive line (see Yang’253, Figs.25 and 28-29 as shown above).
Regarding Claim 4: Yang as modified teaches a semiconductor device as set forth in claim 3 as above. The combination of Yang and Yang’253 further teaches wherein the first contact (610) is not formed in the second region (see Yang’253, Figs.25 and 28-29 as shown above).
The combination of Yang and Yang’253 is silent upon explicitly disclosing wherein a width in the second direction of the first region is less than that of the second region.
However, the combination of Yang and Yang’253 teaches wherein a width in the second direction of the first region is greater than that of the second region (see Yang’253, Figs.25, 28-29, and 30C as shown above).
Hence, It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of first region and the second region through routine experimentation and optimization to obtain optimal or desired contact resistance because the width of the first region and the second region is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 6: Yang as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Yang and Yang’253 further teaches wherein the conductive line in the extension region has a smaller width in the second direction than the conductive line in the cell region (see Yang’253, Fig. 30C as shown above).
Regarding Claim 7: Yang as modified teaches a semiconductor device as set forth in claim 6 as above. The combination of Yang and Yang’253 further teaches wherein the second insulating layer (114) is disposed in the cell region (see Yang, Fig.14 as shown above), and
the second insulating layer is not disposed in the extension region (see Yang’253, Figs.25, 28-29, and 30C as shown above).
Regarding Claim 9: Yang as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Yang and Yang’253 further teaches wherein the conductive pillar (BL-2) includes a plurality of conductive pillars spaced apart from each other in the first direction (note: the Yang single conductive pillar is equivalent to the claimed limitation of plurality of conductive pillars because before effective filing date of the claimed invention ordinary skill in the art capable of demonstrating the duplicated conductive pillars of Yang, for support see Chia et al. (U.S. 2021/0375927 A1, hereinafter refer to Chia), which teaches a plurality of conductive pillars (134), see Chia, Fig.16A) (see Yang, Fig.14 as shown above), and
the semiconductor device further comprises an isolation plug (112) disposed between the plurality of conductive pillars (BL-2) and that extends in the third direction (note: the Yang single isolation plug is equivalent to the claimed limitation of plurality of isolation plug because before effective filing date of the claimed invention ordinary skill in the art capable of demonstrating the duplicated isolation plug of Yang, for support see Chia et al. (U.S. 2021/0375927 A1, hereinafter refer to Chia), which teaches a plurality of isolation plug (118) between plurality of conductive pillars (134), see Chia, Fig.16A) (see Yang, Fig.14 as shown above).
Regarding Claim 10: Yang as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Yang and Yang’253 further teaches wherein the first and second conductive patterns (WL) include tungsten (W) (see Yang, Fig.14 as shown above and ¶ [0020]), and
the second insulating layer (114) includes silicon nitride (SiN) (see Yang, Fig.14 as shown above and ¶ [0020]).
Regarding Claim 11: Yang discloses a semiconductor device (see Yang, Figs.3-4 and 14 as shown above and ¶ [0010]), comprising:
a substrate (118) that includes a cell region that extends in first and second directions that cross each other and includes a ferroelectric memory cell formed thereon, and an extension region that extends from the cell region in the first direction (see Yang, Fig.14 as shown above and ¶ [0020]);
a first conductive line (WL) that extends in the first direction on the substrate (118) (see Yang, Fig.14 as shown above);
a plurality of second conductive lines (BL-2) spaced apart from the first conductive line (WL) in the second direction and spaced apart from each other in the first direction (note: the Yang single second conductive lines is equivalent to the claimed limitation of plurality of second conductive lines because before effective filing date of the claimed invention ordinary skill in the art capable of demonstrating the duplicated second conductive lines of Yang, for support see Chia et al. (U.S. 2021/0375927 A1, hereinafter refer to Chia), which teaches a plurality of second conductive lines (134), see Chia, Fig.16A) (see Yang, Fig.14 as shown above);
a ferroelectric layer (106) disposed between one sidewall of the first conductive line (WL) and the plurality of second conductive lines (BL-2) and that extends in the first direction (see Yang, Fig.14 as shown above and ¶ [0020]);
a semiconductor layer (108) disposed between the ferroelectric layer (106) and the plurality of second conductive lines (BL-2) and that extends in the first direction (see Yang, Fig.14 as shown above and ¶ [0020]); and
an isolation plug (112) disposed between the plurality of second conductive lines (BL-2) (note: the Yang single isolation plug is equivalent to the claimed limitation of plurality of isolation plug because before effective filing date of the claimed invention ordinary skill in the art capable of demonstrating the duplicated isolation plug of Yang, for support see Chia et al. (U.S. 2021/0375927 A1, hereinafter refer to Chia), which teaches a plurality of isolation plug (118) between plurality of second conductive lines (134), see Chia, Fig.16A) (see Yang, Fig.14 as shown above),
wherein the first conductive line (WL) includes a plurality of first (WL1-2) and second (WL1-2’) conductive patterns spaced apart from each other in the second direction, and a silicon material layer (114) that extends in the first direction and is disposed between the first and second conductive patterns (see Yang, Fig.14 as shown above and ¶ [0020]).
Yang is silent upon explicitly disclosing wherein the substrate includes a cell region and an extension region that extends from the cell region in the first direction;
a first contact connected to the first conductive line on the first conductive line, and extending in a third direction that crosses the first and second directions;
wherein the first conductive line in the extension region has first and second regions alternatively arranged in the first direction,
wherein the first contact is connected to the first region, and
wherein silicon material layer is disposed in the second region.
Before effective filing date of the claimed invention the disclosed substrate were known to include a cell region and an extension region that extends from the cell region in the first direction in order to electrically connect the conductive lines and reduce the overall footprint of the array of memory cells.
For support see Yang’253, which teaches wherein the substrate (100) includes a cell region (CR) and an extension region (SR) that extends from the cell region (CR) in the first direction (see Yang’253, Figs.25, 28-29 and 30C as shown above and ¶ [0050]);
a first contact (610) connected to the first conductive line (221/241/261) on the first conductive line (221/241/261), and extending in a third direction that crosses the first and second directions (see Yang, Fig.14 as shown above and ¶ [0020]);
wherein the first conductive line (221/241/261) in the extension region has first and second regions alternatively arranged in the first direction (see Yang, Fig.14 as shown above and ¶ [0020]),
wherein the first contact (610) is connected to the first region (see Yang, Fig.14 as shown above and ¶ [0020]), and
wherein silicon material layer (235/255/275/251/232/271/272)) is disposed in the second region (see Yang, Fig.14 as shown above and ¶ [0020]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teaches of Yang and Yang’253 to enable the Yang substrate to includes a cell region and an extension region that extends from the cell region in the first direction, wherein the first conductive line in the extension region has first and second regions alternatively arranged in the first direction, wherein the first contact to be connected to the first region, and wherein silicon material layer to be disposed in the second region as taught by Yang’253 in order to electrically connect the conductive lines and reduce the overall footprint of the array of memory cells.
Regarding Claim 12: Yang as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Yang and Yang’253 further teaches wherein the first conductive line further includes an uneven structure in a plan view (see Yang’253, Fig. 30C as shown above).
Regarding Claim 13: Yang as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Yang and Yang’253 further teaches wherein the first conductive line in the extension region has a different width in the second direction from that of the first conductive line in the cell region (see Yang’253, Fig. 30C as shown above).
Regarding Claim 14: Yang as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Yang and Yang’253 further teaches wherein the first contact (610) is not formed in the second region (see Yang’253, Figs.25, 28-29 and 30C as shown above),
the silicon material layer (114) includes a plurality of silicon material layers spaced apart from each other in the first direction (see Yang, Fig.14 as shown above and ¶ [0020]).
The combination of Yang and Yang’253 is silent upon explicitly disclosing wherein the first region has a smaller width in the second direction than the second region
However, the combination of Yang and Yang’253 teaches wherein the first region has a larger width in the second direction than the second region (see Yang’253, Figs.25, 28-29, and 30C as shown above).
Hence, It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of first region and the second region through routine experimentation and optimization to obtain optimal or desired contact resistance because the width of the first region and the second region is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 15: Yang as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Yang and Yang’253 further teaches wherein the first conductive line in the extension region has a smaller width in the second direction than the first conductive line in the cell region (see Yang’253, Fig. 30C as shown above), and
the silicon material layer (114) is not disposed in the extension region (see Yang’253, Fig. 30C as shown above).
Regarding Claim 16: Yang as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Yang and Yang’253 further teaches wherein the first conductive line in the extension region has a smaller width in the second direction than the first conductive line in the cell region (see Yang’253, Fig. 30C as shown above).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. 2022/0285395 A1, hereinafter refer to Yang) and Yang et al. (U.S. 2022/0037253 A1, hereinafter refer to Yang’253) as applied to claim 1 above, and further in view of Chia et al. (U.S. 2021/0375927 A1, hereinafter refer to Chia).
Regarding Claim 8: Yang as modified teaches a semiconductor device as applied to claim 1 above. The combination of Yang and Yang’253 is silent upon explicitly disclosing wherein the conductive line further includes an adhesive layer respectively disposed between the first conductive pattern and the second insulating layer and between the second conductive pattern and the second insulating layer.
Before effective filing date of the claimed invention the disclosed conductive line were known to includes an adhesive layer in order to improve the performance of the word lines.
For support see Chia, which teaches wherein the conductive line (112) were includes an adhesive (glue) layer (see Chia, Fig.11B and ¶ [0069]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yang, Yang’253, and Chia to enable the conductive line of Yang to includes an adhesive layer as taught by Chia in order to improve the performance of the word lines.
Hence, practicing the combination of Yang, Yang’253, and Chia to enable the Yang conductive line to includes an adhesive layer according to the teachings of Chia necessarily results the claimed limitation of “the conductive line further includes an adhesive layer respectively disposed between the first conductive pattern and the second insulating layer and between the second conductive pattern and the second insulating layer” as now specified in claim 8.
Claim(s) 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. 2022/0285395 A1, hereinafter refer to Yang) in view of Yang et al. (U.S. 2022/0037253 A1, hereinafter refer to Yang’253) and Chia et al. (U.S. 2021/0375927 A1, hereinafter refer to Chia).
Regarding Claim 17: Yang discloses a method of fabricating a semiconductor device (see Yang, Figs.3- 14 as shown above and ¶ [0010]), the method comprising:
forming a stacked structure on a substrate (118), wherein the stacked structure includes an insulating layer (104) and a sacrificial layer (402/114) that are alternately stacked (see Yang, Figs.3- 4 as shown above), and
forming first (502) and second (502) trenches that penetrate through at least a portion of the stacked structure and are spaced apart from each other in a first direction (see Yang, Figs.3- 4 as shown above),
forming a sacrificial pattern (114) that has a smaller width than the sacrificial layer (402/114) by partially removing the sacrificial layer (402/114) (see Yang, Figs.3- 4 as shown above);
forming a first conductive line (WL) that includes first and second conductive patterns (WL1-2/WL1-2’) that are spaced apart from each other on both sidewalls of the sacrificial pattern (114) (see Yang, Figs.3- 4 and 14 as shown above);
respectively forming a ferroelectric layer (106), a semiconductor layer (108) and a first dielectric layer (112) in the first to second trenches (502) (see Yang, Figs.6 and 14 as shown above);
forming an opening (802/902/1102/1202/1302) that passes through the first dielectric layer (112) and the semiconductor layer (108) in the first and second trench (502) (see Yang, Figs.7-13 as shown above);
forming a second dielectric layer (102) within the opening (802/902/1102/1202/1302) (see Yang, Figs.9- 13 as shown above);
forming a plurality of second conductive layers (BL-2) by respectively removing the first dielectric layers (112) from the first and second trenches (502) (see Yang, Figs.12- 14 as shown above).
Yang is silent upon explicitly disclosing wherein the substrate includes a cell region and an extension region;
forming a first contact, on the first conductive line in the extension region,
wherein the first conductive line in the extension region has first and second regions alternatively arranged in a second direction that crosses the first direction,
wherein the first contact is disposed in the first region, and
wherein the sacrificial pattern is disposed in the second region.
Before effective filing date of the claimed invention the disclosed substrate were known to include a cell region and an extension region in order to electrically connect the conductive lines and reduce the overall footprint of the array of memory cells.
For support see Yang’253, which teaches wherein the substrate (100) includes a cell region (CR) and an extension region (SR) (see Yang’253, Figs.25, 28-29 and 30C as shown above and ¶ [0050]);
forming a first contact (610), on the first conductive line (221/241/261) in the extension region (see Yang’253, Figs.25, 28-29 and 30C as shown above and ¶ [0050]),
wherein the first conductive line (221/241/261) in the extension region has first and second regions alternatively arranged in a second direction that crosses the first direction (see Yang’253, Figs.25, 28-29 and 30C as shown above and ¶ [0050]),
wherein the first contact (610) is disposed in the first region (see Yang’253, Figs.25, 28-29 and 30C as shown above and ¶ [0050]), and
wherein the sacrificial pattern is disposed in the second region (note: “layers of sacrificial material (not shown) may be initially formed between the dielectric layers 210, 230, 250, 270, and the conductive layers 220, 240, 260 may be formed by substituting a conductive material in place of the originally formed sacrificial material”) (see Yang’253, Figs.25, 28-29 and 30C as shown above, ¶ [0015], and ¶ [0050]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teaches of Yang and Yang’253 to enable the Yang substrate to includes a cell region and an extension region that extends from the cell region in the first direction, wherein forming a first contact, on the first conductive line in the extension region, wherein the first conductive line in the extension region to have first and second regions alternatively arranged in a second direction that crosses the first direction, wherein the first contact to be disposed in the first region, and wherein the sacrificial pattern to be disposed in the second region as taught by Yang’253 in order to electrically connect the conductive lines and reduce the overall footprint of the array of memory cells.
The combination of Yang and Yang’253 is silent upon explicitly disclosing wherein a third trench between the first and second trenches;
respectively forming a ferroelectric layer, a semiconductor layer and a first dielectric layer in the first to third second trenches.
Before effective filing date of the claimed invention the disclosed processing conditions were known in order to improve the aspect ratio of the columns of the memory array and avoid twisting or collapsing of the features.
For support see Chia, which teaches forming first and second trenches (106) that penetrate through at least a portion of the stacked structure and are spaced apart from each other in a first direction, and a third trench (106) between the first and second trenches (106) (see Chia, Figs.3-4A as shown below and ¶ [0016]);
forming a sacrificial pattern that has a smaller width than the sacrificial layer (104B) by partially removing the sacrificial layer (104B) (see Chia, Figs.4A and 5A as shown below and ¶ [0016]);
respectively forming a ferroelectric layer (114), a semiconductor layer (116) and a first dielectric layer (118) in the first to third trenches (106) (see Chia, Figs.5A and 7A as shown below and ¶ [0016]).
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Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yang, Yang’253, and Chia to enable the combination of Yang and Yang’253 trenches to include three or more trenches according to the teachings of Chia in order to obtain a plurality of trenches that improve the aspect ratio of the columns of the memory array and avoid twisting or collapsing of the features because one of ordinary skill in the art at the time of the invention would have been motivated to look to alternative suitable methods of performing the disclosed trenches of the combination of Yang and Yang’253 and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Hence, practicing the combination of Yang, Yang’253, and Chia to enable the Yang trenches to include three or more trenches according to the teachings of Chia and to enable forming an opening that passes through the first dielectric layer and the semiconductor layer in at least one of the trench according to the teachings of Yang necessarily results the claimed limitation of “forming an opening that passes through the first dielectric layer and the semiconductor layer in the third first and second trench’ as now specified in claim 17.
Regarding Claim 18: Yang as modified teaches a method of fabricating a semiconductor device as set forth in claim 17 as above. The combination of Yang, Yang’253, and Chia further teaches wherein the sacrificial pattern (114) includes a material that has as etch selectivity with respect to the insulating layer (104) (see Yang, Figs.3- 4 as shown above and ¶ [0020]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812