DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1, 3-7, and 10-15 are rejected under 35 U.S.C. 103 as obvious over Simek-Ege et al. (US 2020/0066729 A1), hereinafter as S1, in view of Kuo et al. (US 9,685,533 B1), hereinafter as K1
4. Regarding Claim 1, S1 discloses a semiconductor device (see in particular Fig. 11), comprising:
a conductive pattern (element 104, see [0021] “digit lines 104 (e.g. data lines, bit lines)”); and
a spacer structure (element 108, 112, 148, see [0025] “low-K dielectric material may comprise one or more of silicon oxycarbide”, see [0026] “nitride dielectric material 112”, and [0045] “air gaps 148”) disposed on a side surface (at least a right side) of the conductive pattern (see Fig. 11),
wherein the spacer structure includes:
an inner spacer (element 108) in contact with the side surface of the conductive pattern (see Fig. 11);
an outer spacer (element 112) that is spaced apart from the side surface of the conductive pattern; and
an air gap (element 148) disposed between the inner spacer and the outer spacer (see Fig. 11), wherein the inner spacer includes an inner oxidized region exposed by the air gap (see [0025] element 108 comprises an silicon oxycarbide which shares a side surface boundary with the air gap;
The language, term, or phrase “oxidized region exposed by the air gap” is directed towards the process of manufacturing the inner spacer. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Pilkington 162 USPQ 145, 147; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. The applicant must show that different methods of manufacturing produce articles having inherently different characteristics, Ex parte Skinner 2 USPQ 2d 1788.
Therefore, the claim does not distinguish from the prior art which discloses an oxygen containing material.).
S1 does not disclose a concentration of oxygen in the inner oxidized region has a gradient in which the oxygen concentration decreases in a direction away from the air gap.
K1 discloses a concentration of oxygen in the inner oxidized region has a gradient in which the oxygen concentration decreases in a direction away from the outer region towards the inner region (see Fig. 8 inner region element 131 Claim 1 “said spacer comprises an inner first spacer portion primarily made of SiCN directly contacting said gate structure and an outer second spacer portion primarily made of SiOCN, wherein the oxygen concentration of each said outer second spacer is gradually increased from the boundary between said first spacer portion and said second portion to the outer surface of said second spacer portion”)
The inner and outer regions material of the spacer of K1 is incorporated as inner and outer regions material of the spacers of S1, wherein the combination discloses in a direction away from the air gap (The concentration decreases away from the outer region towards the inner region).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with K1 because the combination allows for multilayer gradient material SiCN and SiOCN spacers with appropriate chemical and mechanical protection and parasitic capacitance mitigation (see Column 4 lines 56-67 and Column 5 lines 16-35); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sidewall spacer layer material comprising low-k SiOCN lining sidewalls of a conductive layer for another to obtain predictable results (see S1 Column 4 lines 56-67 and Column 5 lines 16-35).
5. Regarding Claim 3, S1, K1 disclose the semiconductor device of claim 1, wherein
the inner spacer further includes an inner non-oxidized region (inner SiCN portion as combined; see K1 Fig. 8 and Column 5 lines 42-44 “the spacer films 131a/132a would include a first spacer portion 131a made of SiCN and a second spacer portion 132a made of SiOCN”), and
the inner oxidized region is disposed between the inner non-oxidized region and the air gap (the order is conductive pattern, inner non-oxidized region, inner oxidized region, and air gap).
6. Regarding Claim 4, S1, K1 disclose the semiconductor device of claim 3, wherein
the inner non-oxidized region of the inner spacer is in contact with the side surface of the conductive pattern (the order of layers is conductive pattern, inner non-oxidized region, inner oxidized region, and air gap such that the non-oxidized region is in contact with the side surface of the conductive pattern).
7. Regarding Claim 5, S1, K1 disclose the semiconductor device of claim 3, wherein
the inner non-oxidized region of the inner spacer includes a silicon carbonitride (SiCN) material (see K1 element 131a portion is SiCN).
[Park (US 2019/0123051), hereinafter as P1 is utilized herein as evidence]
8. Regarding Claim 6, S1, K1 disclose the semiconductor device of claim 1.
S1, K1 as previously combined do not explicitly disclose wherein the outer spacer includes: an outer oxidized region exposed by the air gap; and an outer non-oxidized region in contact with the outer oxidized region.
The inner and outer regions material of the spacer of K1 is further incorporated as inner and outer regions material of the outer spacer of S1, the combination discloses wherein the outer spacer includes: an outer oxidized region exposed by the air gap; and an outer non-oxidized region in contact with the outer oxidized region (The outer spacer of S1 element 112 has a same two layer material mirrored across the air gap; see K1 Fig. 8 and Column 5 lines 42-44 “the spacer films 131a/132a would include a first spacer portion 131a made of SiCN and a second spacer portion 132a made of SiOCN”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with K1 because the combination allows for multilayer gradient material SiCN and SiOCN spacers with appropriate chemical and mechanical protection and parasitic capacitance mitigation (see Column 4 lines 56-67 and Column 5 lines 16-35); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sidewall spacer layer material comprising low-k SiOCN lining sidewalls of a conductive layer for another to obtain predictable results (see S1 Column 4 lines 56-67 and Column 5 lines 16-35 and see S1 [0027] “a different dielectric material (e.g., an oxide dielectric material, an oxynitride dielectric material, a carbonitride dielectric material, a carboxynitride dielectric material) may be employed in place of the nitride dielectric material 112”; also see evidentiary reference P1 Fig. 2 showing an outer spacer element 146 opposite to the air gap element AS1 with respect to the inner spacer element 142 can be a combination of SiCN and SiOCN and [0040] “Each of the outer insulating portion 146A and the insertion portion 146P constituting the second insulating spacer 146 may include, for example, a silicon nitride film, an SiOCN film, an SiCN film, or combinations thereof”).
9. Regarding Claim 7, S1, K1 disclose the semiconductor device of claim 6, wherein
a concentration of oxygen in the outer oxidized region has a gradient in which the oxygen concentration decreases in a direction away from the air gap (the order of layers is conductive pattern, inner non-oxidized region, inner oxidized region, air gap, outer oxidized region, outer non-oxidized region with the material of the inner and outer spacers mirrored such that the concentration decreases in a direction away from the air gap).
10. Regarding Claim 10, S1, K1 disclose the semiconductor device of claim 6, wherein
the outer oxidized region includes a same material as the inner oxidized region (both are SiOCN).
11. Regarding Claim 11, S1, K1 disclose the semiconductor device of claim 10, wherein
the inner oxidized region and the outer oxidized region each include a silicon oxycarbonitride (SiOCN) material (the oxidized region as combined from K1 are both SiOCN), and
the outer non-oxidized region includes a silicon carbonitride (SiCN) material (the non-oxidized region as combined from K1 are both SiCN).
[Park (US 2019/0123051), hereinafter as P1 is utilized herein as evidence]
12. Regarding Claim 12, S1 disclose a semiconductor device (see in particular Fig. 11), comprising:
a conductive pattern (element 104, see [0021] “digit lines 104 (e.g. data lines, bit lines)”); and
a spacer structure (element 108, 112, 148, see [0025] “low-K dielectric material may comprise one or more of silicon oxycarbide”, see [0026] “nitride dielectric material 112”, and [0045] “air gaps 148”) disposed on a side surface (at least a right side) of the conductive pattern (see Fig. 11),
wherein
the spacer structure includes:
an inner spacer (element 108) in contact with the side surface of the conductive pattern (see Fig. 11);
an outer spacer (element 112) that is spaced apart from the side surface of the conductive pattern (see Fig. 11); and
an air gap (element 148) disposed between the inner spacer and the outer spacer (see Fig. 11),
wherein the inner spacer includes an inner oxidized region exposed by the air gap (see [0025] element 108 comprises an silicon oxycarbide which shares a side surface boundary with the air gap;
The language, term, or phrase “oxidized region exposed by the air gap” is directed towards the process of manufacturing the inner spacer. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Pilkington 162 USPQ 145, 147; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. The applicant must show that different methods of manufacturing produce articles having inherently different characteristics, Ex parte Skinner 2 USPQ 2d 1788.
Therefore, the claim does not distinguish from the prior art which discloses an oxygen containing material), and
the outer spacer includes an outer oxidized region exposed by the air gap (see [0027] “a different dielectric material (e.g., an oxide dielectric material, an oxynitride dielectric material, a carbonitride dielectric material, a carboxynitride dielectric material) may be employed in place of the nitride dielectric material 112”).
S1 does not disclose the outer spacer includes an outer non-oxidized region in contact with the outer oxidized region.
K1 discloses an outer non-oxidized region in contact with the outer oxidized region (see Fig. 8 and Column 5 lines 42-44 “the spacer films 131a/132a would include a first spacer portion 131a made of SiCN and a second spacer portion 132a made of SiOCN”)
The inner and outer regions material of the spacer of K1 is incorporated as inner and outer regions material of the spacers of S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with K1 because the combination allows for multilayer gradient material SiCN and SiOCN spacers with appropriate chemical and mechanical protection and parasitic capacitance mitigation (see Column 4 lines 56-67 and Column 5 lines 16-35); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sidewall spacer layer material comprising low-k SiOCN lining sidewalls of a conductive layer for another to obtain predictable results (see S1 Column 4 lines 56-67 and Column 5 lines 16-35 and see K1 [0027] “a different dielectric material (e.g., an oxide dielectric material, an oxynitride dielectric material, a carbonitride dielectric material, a carboxynitride dielectric material) may be employed in place of the nitride dielectric material 112”; also see evidentiary reference P1 Fig. 2 showing an outer spacer element 146 opposite to the air gap element AS1 with respect to the inner spacer element 142 can be a combination of SiCN and SiOCN and [0040] “Each of the outer insulating portion 146A and the insertion portion 146P constituting the second insulating spacer 146 may include, for example, a silicon nitride film, an SiOCN film, an SiCN film, or combinations thereof”).
13. Regarding Claim 13, S1, K1 disclose the semiconductor device of claim 12, wherein a thickness of the outer spacer is greater than a thickness of the inner spacer (see S1 [0025] “the low-K dielectric material 108 may be formed to any desired thickness (e.g., lateral dimension in the X-direction), such as a thickness less than or equal to about 5 nm, such as within a range of from about 1 nm to about 3 nm, or about 2 nm” and [0027] “the nitride dielectric material 112 may be formed to any desired thickness (e.g., lateral dimension in the X-direction), such as a thickness less than or equal to about 10 nm, less than or equal to about 6 nm, or less than or equal to about 4 nm” The inner spacer element 108 is selected as equal to about 1 nm and the outer spacer element 112 is selected as equal to about 10 nm)
14. Regarding Claim 14, S1, K1 disclose the semiconductor device of claim 13, wherein the thickness of the outer spacer is greater than a width of the air gap (see S1 [0027] and [0026] “the oxide dielectric material 110 may be formed to any desired thickness (e.g., lateral dimension in the X-direction), such as a thickness less than or equal to about 10 nm, less than or equal to about 6 nm, or less than or equal to about 4 nm” The outer spacer element 112 is selected to equal to about 10 nm and the oxide dielectric material 110 which becomes the air gap is selected as equal to about 6 nm)
15. Regarding Claim 15, S1, K1 disclose the semiconductor device of claim 14, wherein the width of the air gap is greater than the thickness of the inner spacer (The air gap is selected as equal to about 6 nm and the inner spacer is selected as equal to about 1 nm).
16. Claims 13-16 are rejected under 35 U.S.C. 103 as obvious over Simek-Ege et al. (US 2020/0066729 A1), hereinafter as S1, in view of Kuo et al. (US 9,685,533 B1), hereinafter as K1
17. Regarding Claim 13, S1, K1 disclose the semiconductor device of claim 12, wherein a thickness of the outer spacer is greater than a thickness of the inner spacer (see S1 [0025] “the low-K dielectric material 108 may be formed to any desired thickness (e.g., lateral dimension in the X-direction), such as a thickness less than or equal to about 5 nm, such as within a range of from about 1 nm to about 3 nm, or about 2 nm” and [0027] “the nitride dielectric material 112 may be formed to any desired thickness (e.g., lateral dimension in the X-direction), such as a thickness less than or equal to about 10 nm, less than or equal to about 6 nm, or less than or equal to about 4 nm” The inner spacer element 108 is selected as equal to about 5 nm and the outer spacer element 112 is selected as equal to about 10 nm)
18. Regarding Claim 14, S1, K1 disclose the semiconductor device of claim 13, wherein the thickness of the outer spacer is greater than a width of the air gap (see S1 [0027] and [0026] “the oxide dielectric material 110 may be formed to any desired thickness (e.g., lateral dimension in the X-direction), such as a thickness less than or equal to about 10 nm, less than or equal to about 6 nm, or less than or equal to about 4 nm” The outer spacer element 112 is selected to equal to about 10 nm and the oxide dielectric material 110 which becomes the air gap is selected as equal to about 4 nm)
19. Regarding Claim 16, S1, K1 disclose the semiconductor device of claim 14, wherein the width of the air gap is less than the thickness of the inner spacer (The air gap is selected as equal to about 4 nm and the inner spacer is selected as equal to about 5 nm).
20. Claims 13 and 17 are rejected under 35 U.S.C. 103 as obvious over Simek-Ege et al. (US 2020/0066729 A1), hereinafter as S1, in view of Kuo et al. (US 9,685,533 B1), hereinafter as K1
21. Regarding Claim 13, S1, K1 disclose the semiconductor device of claim 12, wherein a thickness of the outer spacer is greater than a thickness of the inner spacer (see S1 [0025] “the low-K dielectric material 108 may be formed to any desired thickness (e.g., lateral dimension in the X-direction), such as a thickness less than or equal to about 5 nm, such as within a range of from about 1 nm to about 3 nm, or about 2 nm” and [0027] “the nitride dielectric material 112 may be formed to any desired thickness (e.g., lateral dimension in the X-direction), such as a thickness less than or equal to about 10 nm, less than or equal to about 6 nm, or less than or equal to about 4 nm” The inner spacer element 108 is selected as equal to about 1 nm and the outer spacer element 112 is selected as equal to about 4 nm)
22. Regarding Claim 17, S1, K1 disclose the semiconductor device of claim 13, wherein the 13, wherein the width of the air gap is greater than the thickness of the outer spacer (see S1 [0027] and [0026] “the oxide dielectric material 110 may be formed to any desired thickness (e.g., lateral dimension in the X-direction), such as a thickness less than or equal to about 10 nm, less than or equal to about 6 nm, or less than or equal to about 4 nm” The outer spacer element 112 is selected to equal to about 4 nm and the oxide dielectric material 110 which becomes the air gap is selected as equal to about 10 nm).
23. Claim 18 is rejected under 35 U.S.C. 103 as obvious over Choi et al. (US 2020/0013668 A1), hereinafter as C1, in view of Kuo et al. (US 9,685,533 B1), hereinafter as K1
24. Regarding Claim 18, C1 discloses a semiconductor device (see in particular Figs. 1A-F, part of embodiment 1 represented by Figs. 1-18, and [0023] “semiconductor device”), comprising:
an active region (region of element ACT, see [0074] “active portions ACT”);
an isolation region (region of element 102, see [0074] “device isolation pattern 102”) disposed on a side surface of the active region (see Fig. 1A-F);
a gate structure (element GE, see [0075] “gate electrodes GE”) disposed in a gate trench (trench lined by element 107) that intersects the active region and extends into the isolation region (see in particular Fig. 1C);
a first impurity region (element 112b, see [0079] “second doped regions 112b”) and a second impurity region (element 112a, see [0079] “first doped region 112a”) disposed in the active region adjacent to the gate structure and that are spaced apart from each other (see in particular Fig. 1B);
a plurality of structures that intersect the gate structure at a higher level than a level of the gate structure (elements at a height above the gate structure excluding elements 160, 170);
a contact plug (element 160, see [0086] “Contact plugs 160”) that includes a portion disposed between the plurality of structures and electrically connected to the first impurity region (see in particular Fig. 1B); and
spacer structures (elements 170, see [0086] “spacer structure 170”) disposed on side surfaces of the plurality of structures (see in particular Fig. 1B),
wherein
each of the plurality of structures includes a bit line (elements 135,130, see [0107] “conductive wire 135 may be a bit line” and [0083] “wire-plugs 130”) and an insulating capping pattern (element 137, see [0085] “hard mask pattern 137 is formed of an insulating material”) disposed on the bit line (see in particular Fig. 1B),
the bit line includes:
a first bit line portion disposed on the isolation region (in particular see Fig. 1B element 135 portion over element 102); and
a second bit line portion (element 130 portion contacting a bottom surface of element 135 over element 112a) that includes a lower surface disposed at a level that is lower than a level of a lower surface of the first bit line portion, and that vertically overlaps the second impurity region (see in particular Fig. 1B),
each of the spacer structures includes a first spacer portion (elements 143a,155 on a side of the first bit line portion) disposed on a side surface of the first bit line portion and a second spacer portion (elements 143a,155 on a left side of the second bit line portion) disposed on a side surface of the second bit line portion,
the first spacer portion includes: a first inner spacer (element 143a of the first spacer portion) in contact with a side surface of the first bit line portion;
a first outer spacer (element 155 of the first spacer portion); and
a first air gap (element AG of the first spacer portion, see [0086] “air gap AG”) disposed between the first inner spacer and the first outer spacer (see Fig. 1B), the second spacer portion includes:
a second inner spacer (element 143a of the second spacer portion) in contact with a side surface of the second bit line portion; a second outer spacer (element 155 of the second spacer portion); and
a second air gap (element AG of the second spacer portion) disposed between the second inner spacer and the second outer spacer,
each of the first and second inner spacers includes an inner oxidized region (see [0094] “first protecting spacer 143a may include a nitride (e.g., silicon nitride) and/or an oxynitride (e.g., silicon oxynitride)” Selected as an oxynitride – the process of oxidation for forming the oxygen containing spacer material is directed towards a “product by process” limitation which does not distinguish from the structure disclosed by the prior art.).
C1 does not disclose a concentration of oxygen in the inner oxidized region of the first inner spacer has a gradient in which the oxygen concentration decreases in a direction away from the first air gap, and a concentration of oxygen in the inner oxidized region of the second inner spacer has a gradient in which the oxygen concentration decreases in a direction away from the second air gap.
K1 discloses a concentration of oxygen in the inner oxidized region has a gradient in which the oxygen concentration decreases in a direction away from the outer region towards the inner region (see Fig. 8 inner region element 131 Claim 1 “said spacer comprises an inner first spacer portion primarily made of SiCN directly contacting said gate structure and an outer second spacer portion primarily made of SiOCN, wherein the oxygen concentration of each said outer second spacer is gradually increased from the boundary between said first spacer portion and said second portion to the outer surface of said second spacer portion”)
The inner and outer regions material of the spacer of K1 is incorporated as inner and outer regions material of the spacers of S1, wherein the combination discloses a concentration of oxygen in the inner oxidized region of the first and second inner spacers in a direction away from the first and second air gaps respectively (The concentration decreases away from the outer region towards the inner region for each of the first spacer portion and second spacer portions).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with C1 because the combination allows for multilayer gradient material SiCN and SiOCN spacers with appropriate chemical and mechanical protection and parasitic capacitance mitigation (see Column 4 lines 56-67 and Column 5 lines 16-35); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sidewall spacer layer material comprising low-k SiOCN lining sidewalls of a conductive layer for another to obtain predictable results (see S1 Column 4 lines 56-67 and Column 5 lines 16-35; and see C1 [0094] both elements 143a and 155 may include a nitride layer and/or an oxynitride layer).
25. Claim 20 is rejected under 35 U.S.C. 103 as obvious over Choi et al. (US 2020/0013668 A1), hereinafter as C1, in view of Kuo et al. (US 9,685,533 B1), hereinafter as K1, in view of Sung (US 2023/0017800 A1), hereinafter as S1
26. Regarding Claim 20, C1, K1 discloses the semiconductor device of claim 18.
C1, K1 do not disclose wherein a thickness of each of the first and second inner spacers ranges from 7 angstroms to 25 angstroms.
S2 discloses wherein a thickness of each of the first and second inner spacers ranges from 7 angstroms to 25 angstroms (see [0028] “The first spacer 215 may include ultra-thin silicon nitride of approximately 10 Å or less.” See MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)")
The thickness range of the first and second inner spacers range as taught by S2 is incorporated as a thickness range of the first and second inner spacers range of C1, K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S2 with C1, K1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sidewall spacer layer thickness for another in a similar device to obtain predictable results (see S2 Fig. 2A and [0028]).
Allowable Subject Matter
27. Claims 2, 8-9, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
28. Claim 2, “the inner oxidized region includes a silicon oxycarbonitride (SiOCN) material, and a concentration of carbon in the inner oxidized region has a gradient in which the carbon concentration increases in the direction away from the air gap” – as instantly claimed and in combination with the additionally claimed limitations.
18. Claim 8, “a material of the outer oxidized region differs from a material of the inner oxidized region” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on claim 8 incorporate the same allowable subject matter.
18. Claim 19, “the inner oxidized regions of the first and second inner spacers include a silicon oxycarbonitride (SiOCN) material, a concentration of carbon in the inner oxidized region of the first inner spacer has a gradient in which the carbon concentration increases in a direction away from the first air gap, and a concentration of carbon in the inner oxidized region of the second inner spacer has a gradient in which the carbon concentration increases in a direction away from the second air gap” – as instantly claimed and in combination with the additionally claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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