DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1 (and dependent claims 2-14) is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites the limitation “A semiconductor package, comprising:a lower surface comprising:a low voltage contact pad;a high voltage contact pad;an output contact pad; andat least one control contact pad;at least one half-bridge circuit(Fig1) comprising a first transistor device having a first major surface and a second transistor device having a first major surface” in lines 1-8. Claim 1 also recites the limitation “wherein the first major surface of the first transistor device and the first major surface of the second transistor device are arranged substantially perpendicularly to the lower surface of the semiconductor package” in lines 13-15. Examiner is unclear as to the meaning of “substantially perpendicularly”. The first major surface of the first transistor device and the first major surface of the second transistor device would be parallel to the lower surface of the semiconductor package since the semiconductor package comprises the first transistor device and the second transistor device.
Additionally, the metes and bounds of the claimed limitation can not be determined for the following reasons: the term "substantially” is a relative term, which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The relative term modifies a target (“equal”), and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “about” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation from being equal (such as the first height being within 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. For the purposes of examination, the “lower surface of the semiconductor package” will be considered as the surface of the semiconductor package.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stella(USPGPUB DOCUMENT: 2013/0003309, hereinafter Stella) in view of Otremba (USPGPUB DOCUMENT: 2015/0145112, hereinafter Otremba).
Re claim 1 Stella discloses (insofar as best understood, see 112 above) a semiconductor package, comprising: a lower surface comprising: a low voltage contact pad(Lsl); a high voltage contact pad(Ldh); an output contact pad(Lout); and at least one control contact pad(Lout’); at least one half-bridge circuit(Fig1) comprising a first transistor device(Ml/405l) having a first major surface(top/bottom) and a second transistor device(Mh/405h) having a first major surface(top/bottom), the first and second transistor device(Mh/405h)s being electrically coupled in series at an output node(Tout)[0023,0024]; wherein the first major surface(top/bottom) of the first transistor device(Ml/405l) and the first major surface(top/bottom) of the second transistor device(Mh/405h) are arranged substantially perpendicularly to the surface of the semiconductor package(surface of 450/420).
Stella does not discloses at least one control device electrically coupled to the first transistor device(Ml/405l) and the second transistor device(Mh/405h),
Otremba discloses in Fig 6 at least one control device(182 of Otremba) electrically coupled(by way of 144/194/195) to the first transistor device(178) and the second transistor device(180),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Otremba to the teachings of Stella in order to electronic component may include two or more semiconductor devices in a package with outer contacts [0001, Otremba].
Re claim 2 Stella and Otremba disclose the semiconductor package of claim 1, further comprising:a first lead having an inner surface that extends substantially perpendicularly to the lower surface and a lower side face that forms the low voltage contact pad(Lsl);a second lead having an inner surface that extends substantially perpendicularly to the lower surface and a lower side face that provides the high voltage contact pad(Ldh);anda third lead having a first inner surface and a second inner surface opposing the first inner surface, wherein the first transistor device(Ml/405l) is mounted on the first inner surface,the second transistor device(Mh/405h) is mounted on the second inner surface, and the third lead provides the output node(Tout)[0023,0024],wherein the first lead is arranged at a first package side face, the second lead is arranged at a second package side face that opposes the first package side face, and the third lead has a lower side face that is arranged in the lower surface between the low voltage contact pad(Lsl) and the high voltage contact pad(Ldh).
Re claim 3 Stella and Otremba disclose the semiconductor package of claim 2, wherein the at least one control contact pad(Lout’) is arranged in a common plane with the low voltage contact pad(Lsl).
Re claim 4 Stella and Otremba disclose the semiconductor package of claim 2, wherein the low voltage contact pad(Lsl), the high voltage contact pad(Ldh), and the at least one output contact pad(Lout) each have a width that is less than or equal to a thickness of the first lead, the second lead, and the third lead, respectively, and a length that is less than the length of the lower surface of the package.
Re claim 5 Stella and Otremba disclose the semiconductor package of claim 2, wherein:the first transistor device(Ml/405l) comprises a first power pad on the first major surface(top/bottom) of the first transistor device(Ml/405l) and a second power pad on a second major surface(top/bottom) of the first transistor device(Ml/405l) opposing the first major surface(top/bottom) of the first transistor device(Ml/405l);the second transistor device(Mh/405h) comprises a first power pad on the first major surface(top/bottom) of the second transistor device(Mh/405h) and a second power pad on a second major surface(top/bottom) of thesecond transistor device(Mh/405h) opposing the first major surface(top/bottom) of the second transistor device(Mh/405h); the second power pad of the first transistor device(Ml/405l) is mounted on the first inner surface of the third lead and the first power pad of the second transistor device(Mh/405h) is arranged on the second inner surface of the third lead; and the first lead comprises an inner surface attached to the first power pad of the first transistor device(Ml/405l) and the second lead comprises an inner surface attached to the second power pad of the second transistor device(Mh/405h).
Re claim 6 Stella and Otremba disclose the semiconductor package of claim 2, wherein the third lead comprises a recess in which the second transistor device(Mh/405h) is arranged.
Re claim 7 Stella and Otremba disclose the semiconductor package of claim 5, wherein the first transistor device(Ml/405l) further comprises a first gate pad on the second major surface(top/bottom) of the first transistor device(Ml/405l), and wherein the second transistor device(Mh/405h) further comprises a second gate pad on the second major surface(top/bottom) of the second transistor device(Mh/405h).
Re claim 8 Stella and Otremba disclose the semiconductor package of claim 7, wherein the at least one control device(182 of Otremba) is mounted on the first lead.
Re claim 9 Stella and Otremba disclose the semiconductor package of claim 7, wherein the at least one control device(182 of Otremba) is electrically connected to the first gate pad, the second gate pad, and the at least one control contact pad(Lout’) by bond wires.
Re claim 10 Stella and Otremba disclose the semiconductor package of claim 5, wherein the first transistor device(Ml/405l) further comprises a first gate pad on the first major surface(top/bottom) of the first transistor device(Ml/405l), and wherein the second transistor device(Mh/405h) further comprises a second gate pad on the second major surface(top/bottom) of the second transistor device(Mh/405h).
Re claim 11 Stella and Otremba disclose the semiconductor package of claim 10, wherein the third lead is provided by a lead frame that comprises electrically insulating material on which conductive traces and the at least one control contact pad(Lout’) are formed, and wherein the at least one control device(182 of Otremba) is mounted on the lead frame.
Re claim 12 Stella and Otremba disclose the semiconductor package of claim 11, wherein the first gate pad and the second gate pad are connected to the conductive traces of the lead frame by a bond wire, and wherein the at least one control device(182 of Otremba) is connected to the at least one control contact pad(Lout’) and/or the conductive traces by a bond wire.
Re claim 13 Stella and Otremba disclose the semiconductor package of claim 2, wherein the at least one control contact pad(Lout’) is arranged in a common plane with the high voltage contact pad(Ldh) and/or with the at least one output contact pad(Lout).
Re claim 14 Stella and Otremba disclose the semiconductor package of claim 1, wherein the at least one half-bridge circuit(Fig1) comprises a first half bridge circuit and a second half bridge circuit that are electrically coupled to form a full bridge circuit.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Prosecution Insights