Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/351,591 filed on July 13, 2023.
Information Disclosure Statement
3. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Objections
4. Claims 4, 7, 19, 22 are objected to because of the following informalities: In the following, the claim should be recited to avoid indefiniteness due to lack of antecedent basis, and/or perform proper alignment along with the prior claim languages:
4. (Currently amended) The IC package of Claim 1, wherein the conductive routing structure includes at least one conductive element connecting the at least one winding of the inductive device to the bare die.
7. (Currently amended) The IC package of Claim 1, wherein the inductive device including the at least one winding comprises a transformer including a first winding and a second winding magnetically coupled to the first winding.
19. (Currently amended) The method of Claim 18, comprising forming the opening by a laser drilling process.
22. (Currently amended) The method for manufacturing a self-aligned interconnection structure according to claim 15, wherein the first barrier layer is an adhesive layer or an anti-oxidation layer, and the second barrier layer is an etch stop layer or a hermetic layer.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-6, 10-11, 14-17, 20-21 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as¶ being anticipated by Gu et al. (US 2015/0206837 A1).
Regarding independent claim 1, Gu et al. teaches an integrated circuit (IC) package (500, para [0068], Fig. 5), comprising:
a substrate (501, para [0068]);
a bare die (502 1st die, para [0068] bare die means without package) mounted on the substrate (501, para [0068]), the bare die (502) including IC elements, a dielectric region (see the annotated figure below) at least partially encapsulating (506 dielectric layer, para [0068]) the IC elements, and an IC contact (see the annotated figure below) exposed through the dielectric region;
a conductive routing region (see the annotated figure below) including multiple conductive routing layers (see Fig. 5) formed over the bare die (502);
a conductive routing structure (508, 510 RDL layers, see in the conductive routing region) formed in the multiple conductive routing layers, wherein the conductive routing structure is conductively connected to the IC contact of the bare die (502); and
an inductive device (514 toroid inductor, para [0068]) formed in the conductive routing region, the inductive device (514) including at least one winding (para [0074]) formed in at least one conductive routing layer (RDL) of the multiple conductive routing layers.
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Regarding claim 2, Gu et al. teaches wherein (Fig. 5), the IC package comprises a chip-first package (500).
Regarding claim 3, Gu et al. teaches wherein (Fig. 5), the conductive routing region comprises a redistribution layer (RDL) region (508), wherein respective conductive routing layers of the multiple conductive routing layers comprise respective RDL layers.
Regarding claim 4, Gu et al. teaches wherein (Fig. 5), the conductive routing structure (see the annotated figure in claim 1) includes at least one conductive element (508) connecting the winding (para [0074]) of the inductive device (514) to the bare die (502).
Regarding claim 5, Gu et al. teaches wherein (Fig. 5), the conductive routing structure includes at least one conductive element (510) separate from the inductive device (514) and formed in a common conductive routing layer as a respective winding of the at least one winding (para [0074]).
Regarding claim 6, Gu et al. teaches wherein (Fig. 3), the inductive device (300, para [0053]) including at least one winding (302/304/306 formed windings, see para [0054]) comprises an inductor including a single winding (302a/304/306a).
Regarding claim 10, Gu et al. teaches wherein (Fig. 5), the IC package (500) includes a further bare die (504) mounted to the substrate (501); and
the inductive device (514) is connected between the bare die (502) and the further bare die (504).
Regarding claim 11, Gu et al. teaches wherein (Fig. 5), the conductive routing structure includes an external contact element (528) contactable by an external device (not shown, it’s inherent that the external contact element 528 formed for next level connections, such as stacked device and/or PCB or mother board); and
the inductive device (514) is connected between the bare die (502) and the external contact element (528).
Regarding independent claim 14, Gu et al. teaches a method of forming an integrated circuit (IC) package (500, para [0068], Fig. 5), comprising:
mounting a bare die (502, para [0068]) on a substrate (501, para [0068]), the bare die (502) including IC elements, a dielectric region (see the annotated figure below) at least partially encapsulating (506 dielectric layer, para [0068]) the IC elements, and an IC contact (see the annotated figure below) exposed through the dielectric region; and
forming a conductive routing region (see the annotated figure below) over the over the bare die (502), wherein the conductive routing region includes (a) a conductive routing structure (508, 510 RDL layers, see in the conductive routing region) conductively connected to the IC contact of the bare die (502), and (b) an inductive device (514 toroid inductor, para [0068]);
wherein the conductive routing region (see the annotated figure below) includes multiple conductive routing layers (508, 510 RDL layers);
wherein the conductive routing structure includes conductive elements (508) formed in respective conductive routing layers of the multiple conductive routing layers; and
wherein the inductive device (514) includes a winding formed in at least one conductive routing layer of the multiple conductive routing layers.
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Regarding claim 15, Gu et al. teaches wherein (Fig. 5), forming the conductive routing region comprises forming a redistribution layer (RDL) region (508) including multiple RDL layers (see Fig. 5).
Regarding claim 16, Gu et al. teaches wherein (Fig. 5), comprising forming a respective conductive element (510) of the conductive routing structure, separate from the winding (514), in a common conductive routing layer as the winding.
Regarding claim 17, Gu et al. teaches wherein (Fig. 5), the conductive routing structure connects the winding of the inductive device (514) to the bare die (502).
Regarding independent claim 20, Gu et al. teaches an integrated circuit (IC) package (500, para [0068], Fig. 5), comprising:
a substrate (501, para [0068]);
a first bare die (502, para [0068]) and a second bare die (504, para [0068]) mounted on the substrate (501);
a conductive routing region (see the annotated figure below) including a conductive routing layer stack (508/510) formed over the first bare die (502) and the second bare die (504);
a conductive routing structure comprising at least one first conductive element formed in the conductive routing layer stack (508/510); and
an inductive device (514 toroid inductor, para [0068]) connected between the first bare die (502) and the second bare die (504), the inductive device (514) including a winding comprising at least one second conductive element formed in the conductive routing layer stack (508/510).
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Regarding independent claim 21, Gu et al. teaches wherein (500, para [0068], Fig. 5), the conductive routing layer stack (508/510) comprises at least one redistribution layer (RDL) (508).
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
11. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
12. Claims 7-9, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Gu et al. (US 2015/0206837 A1) as applied to claim 1 above, and further in view of Andres et al. (US 2014/0266530 A1).
Regarding claim 7, Gu et al. teaches all of the limitations of claim 1 from which this claim depends.
Gu et al. is explicitly silent of disclosing wherein, the inductive device including at least one winding comprises a transformer including a first winding and a second winding magnetically coupled to the first winding.
Andres et al. teaches wherein (Figs. 1-2, 6), the inductive device including at least one winding comprises a transformer (para [0031]) including a first winding (204, see Fig. 2) and a second winding (206, see Fig. 2) magnetically coupled to the first winding (204).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Andres et al., and modify toroid inductor of Gu et al., in order to use in high density power electronic circuits requiring the use of multiple magnetic electrical components for a variety of purposes, including energy storage, signal isolation, signal filtering, energy transfer, and power splitting, as the demand for higher power density electrical components increases, it becomes more desirable to integrate two or more magnetic electrical components, such as transformers and inductors, into the same core or structure (para [0003]).
Regarding claim 8, Gu et al. and Andres et al. teach all of the limitations of claim 7 from which this claim depends.
The combination of Gu et al. (Fig. 5) and Andres et al. (Figs. 2, 6) teaches wherein:
the first winding (204) is formed in a first conductive routing layer of the multiple conductive routing layers; and
the second winding (206) is formed in a second conductive routing layer of the multiple conductive routing layers.
Regarding claim 9, Gu et al. and Andres et al. teach all of the limitations of claim 7 from which this claim depends.
The combination of Gu et al. and Andres et al. teaches wherein (500, para [0068], Fig. 5), wherein:
the IC package (500) includes a further bare die (504) mounted to the substrate (501);
the first winding (204) is conductively coupled to the bare die (502); and
the second winding (206) is conductively coupled to the further bare die (504).
Regarding claim 12, Gu et al. teaches all of the limitations of claim 1 from which this claim depends.
Gu et al. is explicitly silent of disclosing wherein, a respective winding of the at least one winding has a spiral shape.
Andres et al. teaches wherein (Fig. 6), a respective winding of the at least one winding (206) has a spiral shape.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Andres et al., and modify the toroid inductor of Gu et al. along with spiral winding, because of its well- known properties, reduced parasitic capacitance, achieve higher inductance values and better current handling capabilities which is essential for high-performance applications.
13. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Gu et al. (US 2015/0206837 A1) as applied to claim 1 above, and further in view of Zhang et al. (US 2019/0027303 A1).
Regarding claim 13, Gu et al. teaches all of the limitations of claim 1 from which this claim depends.
Gu et al. is explicitly silent of disclosing wherein, comprising:
a core comprising a magnetic paste or other material having a permeability greater than 1.0;
wherein the at least one winding extends around the core.
Zhang et al. teaches wherein (Fig. 1), comprising:
a core (100, para [0035]) comprising a magnetic paste or other material (ferrite, para [0035]) having a permeability greater than 1.0 (ranges 1400-15000, depending on elements inside the ferrite);
wherein the at least one winding (para [0036]) extends around the core (100).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Zhang et al., and modify the material of toroid inductor core of Gu et al. along with ferrite material, in order to provide a medium for storing, transferring or releasing electromagnetic energy (para [0002]).
14. Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gu et al. (US 2015/0206837 A1) as applied to claim 14 above, and further in view of Roy et al. (US 2014/0159850 A1) and Andres et al. (US 2014/0266530 A1).
Regarding claim 18, Gu et al. teaches all of the limitations of claim 14 from which this claim depends.
Gu et al. is explicitly silent of disclosing wherein, comprising forming an inductor core by:
forming an opening in the conductive routing region; and
depositing a core material in the opening;
wherein the winding extends around the inductor core.
Roy et al. teaches wherein (Fig. 1), comprising forming an inductor core (160) by:
forming an opening (para [0018]) in the conductive routing region (see Fig. 1); and
depositing a core material (magnetic material, para [0018]) in the opening;
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Roy et al., while forming the inductive material including winging, in order to manufacture a magnetic core for storing, transferring or releasing electromagnetic energy.
Gu et al. and Roy et al. are explicitly silent of disclosing wherein, the winding extends around the inductor core.
Andres et al. teaches wherein (Fig. 6), the winding (254) extends around the inductor core (230).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Andres et al., and modify the toroid inductor of Gu et al. and Roy et al. along with spiral winding around the core, because of its well-known properties, reduced parasitic capacitance, achieve higher inductance values and better current handling capabilities which is essential for high-performance applications.
Regarding claim 19, Gu et al. teaches all of the limitations of claim 18 from which this claim depends.
Gu et al. is explicitly silent of disclosing wherein, comprising forming the opening by a laser drilling process.
Roy et al. teaches wherein (Fig. 1), comprising forming the opening (openings drilled where the cores 160, 161 are formed, see para [0018]) by a laser drilling process.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Roy et al., and using drilling process in the routing/redistribution layer while forming the toroid inductor of Gu et al., because of its well-known/essential manufacturing process step for forming inductive cores.
Examiner’s Note
15. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
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17. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812