DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species I, with claims 1-6 indicated by Applicant to read thereon in the reply filed on 3/5/2026 is acknowledged. The traversal is on the ground(s) that the inventions/species are readily evaluated in one search without placing undue burden on the Examiner. This is not found persuasive because this proposed process shows different invention/species what would require a diversity field of search since their different classification have already been established. And It would require undue burdensome search to examine all species.
The requirement is still deemed proper and is therefore made FINAL.
Claims 7-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 3/5/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re claim 2, the phrase “wherein the substrate includes the cavity … and a region according to an outermost contour including the one or more semiconductor dies and the one or more dummy dies, the region being symmetrical with respect to a center point of the fan-out semiconductor package” is unclear and indefinite (e.g., which portion/region is considered as the outermost contour? where is the center point? And/or which point is considered as the center point etc.).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pan et al., US Pub. No. 2014/0131858A1.
Re claim 1, Pan et al. disclose a fan-out semiconductor package, comprising: a substrate including a cavity (e.g., fig. 1B, 2I, 3E); one or more semiconductor dies 121 within the cavity (e.g., fig. 1B, 2I, 3E), the one or more semiconductor dies including a plurality of connection terminals 127 at a bottom surface thereof (e.g., fig. 1B, 2F/I, 3D/E); one or more dummy dies inner parts of 122/123 (e.g, fig. 1B) or 208/207/123 etc. (fig. 2I) at a fan-out region within the cavity (e.g., fig. 1B, 2I, 3E), the one or more dummy dies including a plurality of through silicon vias (TSVs) 122 (e.g., fig. 1B, 2I, 3E); a filler 128 and/or part of 123 etc. (e.g., fig. 1B) filling an empty space within the cavity (e.g., fig. 1B, 2I, 3E); a lower redistribution layer 125 (e.g., fig. 1B, 2I, 3E) on bottom surfaces of the substrate, the one or more semiconductor dies, and the one or more dummy dies, the lower redistribution layer electrically connected to the plurality of connection terminals of the one or more semiconductor dies and at least some of the plurality of through silicon vias of the one or more dummy dies (e.g., fig. 1B, 2I, 3E); and an upper redistribution layer 124 (e.g., fig. 1B, 2I, 3E) on top surfaces of the substrate, the one or more semiconductor dies, and the one or more dummy dies, the upper redistribution layer electrically connected to at least some of the plurality of through silicon vias of the one or more dummy dies (e.g., fig. 1B, 2I, 3E), see figs. 1A-3E and pages 1-6 for more details.
Re claim 2, The fan-out semiconductor package of claim 1, wherein the substrate includes the cavity accommodating the one or more semiconductor dies and the one or more dummy dies (e.g., fig. 1B, 2I, 3E), and a region (e.g., as shown in fig. 1B, 2I, 3E) according to an outermost contour including the one or more semiconductor dies and the one or more dummy dies, the region being symmetrical with respect to a center point of the fan-out semiconductor package (e.g., with respect a point in the center of the chip 121 as shown fig. 1B, 2I, 3E).
Re claim 5. The fan-out semiconductor package of claim 2, wherein a planar area occupied by the one or more semiconductor dies and the one or more dummy dies is 90% or more of a total planar area of the cavity (e.g., less than 10% is the filler 128 etc. as shown in fig. 1B, 2I, 3E).
Re claim 6. The fan-out semiconductor package of claim 5, wherein the total planar area of the cavity is 80% or more of an area according to an outermost contour of the substrate (e.g., fig. 1B, 2I, 3E).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al., US Pub. No. 2014/0131858A1 in view of Applicant’s admitted prior art.
Pan et al. disclosed above; however, Pan et al. does not explicitly show the cavity has a quadrangle shape and a center point of the quadrangle shape coincides with the center point of the fan-out semiconductor package, the one or more semiconductor dies are at a central portion within the cavity and four dummy dies having a rectangular shape are at a periphery of the semiconductor die such that a long side of one of the four dummy dies and a short side of another of the four dummy dies face each side of the cavity (Re claim 3); or the cavity has a quadrangle shape and a center point of the quadrangle shape coincides with the center point of the fan-out semiconductor package, the one or more semiconductor dies are in the cavity to be adjacent to one side of the cavity, and the one or more dummy dies are in a remaining space within the cavity, the remaining space being an area of the cavity that is not occupied by the one or more semiconductor dies (Re claim 4).
Applicant’s admitted prior art teaches a fan-out semiconductor package comprise a cavity (fig. 1A-1B), wherein the cavity has a quadrangle shape and a center point of the quadrangle shape coincides with the center point of the fan-out semiconductor package, the one or more semiconductor dies 120 are at a central portion within the cavity and four dummy dies 140 having a rectangular shape are at a periphery of the semiconductor die such that a long side of one of the four dummy dies and a short side of another of the four dummy dies face each side of the cavity (figs. 1A-1B); or the cavity has a quadrangle shape and a center point of the quadrangle shape coincides with the center point of the fan-out semiconductor package, the one or more semiconductor dies 120 are in the cavity to be adjacent to one side of the cavity (fig. 1B), and the one or more dummy dies 140 are in a remaining space within the cavity (fig. B), the remaining space being an area of the cavity that is not occupied by the one or more semiconductor dies (fig. 1A-1B).
Therefore, the subject matter as a whole would have been obvious to one having ordinary skill in the art before the invention was made to use the fan-out semiconductor package configuration as taught by Applicants’ admitted prior art in the device of Pan et al. in order to suppress warpage in the fan-out region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACK S CHEN/Primary Examiner, Art Unit 2893
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