DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (2021/0289629).
Regarding claim 1, Lee (Figs. 15) discloses a semiconductor package 800B, comprising: a lower substrate 200 comprising a contact region (around #300) and a non-contact region (on the right and the left side of #300), wherein the contact region extends around the non-contact region (Fig. 15, [0080]); a first upper substrate 100 on the lower substrate 200 ([0046]); a lower device 400 on the first upper substrate 100 ([0066]); a plurality of first solder balls 180 between the first upper substrate 100 and the lower substrate 200 contact region ([0054]); a plurality of capacitors 300 between the first upper substrate 200 and the lower substrate 200 non-contact region ([0046]); and a plurality of support blocks 350b between the plurality of capacitors 300 and the lower substrate non-contact region 200 (see Fig. 20, [0100]).
Regarding claim 2, Lee (Fig. 15) discloses wherein the non-contact region (on the right and the left side of #300) comprises: a first non-contact region (on the right of #300); and a second non-contact region (on the left side of #300) adjacent to the first non-contact region.
Allowable Subject Matter
Claims 3-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose all the limitations recited in the claims 3, 6 and 8. Specifically, the prior art of record fails to disclose wherein the plurality of support blocks comprise: a first support block between the lower substrate first non-contact region and one of the plurality of capacitors, wherein the first support block comprises a recess that receives the one of the plurality of capacitors; and a second support block between the lower substrate second non-contact region and another one of the plurality of capacitors, wherein the second support block comprises a recess that receives the another one of the plurality of capacitors (claim 3); or wherein the lower device comprises: a low-temperature region on the first non-contact region; and a high-temperature region on the second non-contact region (claim 6); or further comprising a first underfill layer between the plurality of first solder balls and the plurality of support blocks, wherein the plurality of support blocks have a thermal expansion coefficient less than a thermal expansion coefficient of the first underfill layer (claim 8).
Claims 11-20 are allowed.
The following is an examiner's statement of reasons for allowance:
The prior art of record neither anticipates nor renders obvious all the limitations in the base claims 11 and 16. Specifically, the combination of a semiconductor package, comprising: a plurality of passive devices between the first upper substrate and the lower substrate non-contact region; a first underfill layer between the plurality of first solder balls; and a plurality of support blocks between the lower substrate non-contact region and the plurality of passive devices, wherein the plurality of support blocks have a thermal expansion coefficient less than a thermal expansion coefficient of the first underfill layer (claim 11); or the combination of the semiconductor package, comprising: a second upper substrate on the lower device and the first upper substrate; a plurality of second solder balls between the first and second upper substrates; and a second underfill layer between the lower device and the plurality of second solder balls, wherein the second underfill layer has a thermal expansion coefficient less than the thermal expansion coefficient of the first underfill layer (in claim 16).
The dependent claims being further limiting and definite are also allowable.
Conclusion
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/THERESA T DOAN/ Primary Examiner, Art Unit 2814