Prosecution Insights
Last updated: April 19, 2026
Application No. 18/352,311

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Jul 14, 2023
Examiner
JAHAN, BILKIS
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies Austria AG
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
788 granted / 892 resolved
+20.3% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
43 currently pending
Career history
935
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
51.4%
+11.4% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
14.3%
-25.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 892 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Attorney Docket Number: 1012-3583/2021P04588 US Filling Date: 07/14/23 Priority Date: 07/21/22 Inventor: Prechtl et al Examiner: Bilkis Jahan DETAILED ACTION In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant’s election without traverse of Species III, figure 3A, claims 1-4, 6-10 and 13-18 in the reply filed on 12/15/25 is acknowledged. Claims 5, 11-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Claim Objections Claims 1, 6, 9 and 12 are objected to because of the following informalities: 1, 6, 9 and 12 recites “neighbouring”. However, it should be “neighboring”. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4, 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Plumton (6,097,046). Regarding claim 1, Plumton discloses a semiconductor device (Figures 1, 14) comprising a Group Ill nitride transistor device 112, 1412 and a Schottky barrier diode 1450 integrated in a Group III nitride body 1408 (abstract), the semiconductor device comprising: a common drain 1422, 118/cathode finger arranged on the Group III nitride body 1408; two or more source contacts 112 (Fig. 1C) arranged on the Group Ill nitride body 1408 and spaced apart in a row (Fig. 1C), the row being spaced laterally apart from, and extending substantially parallel (parallel in cross section, Figs. 1b, 14) to, the common drain 118, 1422/cathode finger; a gate electrode 114 structure arranged on the Group Ill nitride body 1408; and one or more Schottky metal contacts 1452 arranged on the Group Ill nitride body 1408, at least one Schottky metal contact 1452 being arranged between and spaced apart from neighbouring ones of the source contacts 112 (Fig. 1c), wherein the gate electrode 114 (Fig. 1C) structure comprises a closed ring section for each source contact 112 (Fig. 1C, array) that laterally surrounds that source contact 112, wherein neighbouring closed ring sections are connected by a gate connection section 114, 1414. Regarding claim 4, Plumton discloses the semiconductor device of claim 1, wherein the one or more Schottky metal contacts 1452 is arranged on the Group III nitride body 1408 laterally between (diagonally between) the gate connection section 1414, 114 and the common drain 118, 1422/cathode finger. Regarding claim 7, Plumton discloses a semiconductor device, comprising a plurality of cells (Fig. 1C) that are electrically coupled in parallel (element 112 are in array), each cell comprising a drain finger 118, a source structure 112, and a gate structure 104, wherein one or more of the cells comprises the semiconductor device of claim 1 (Figs. 1, 14). Regarding claim 8, Plumton discloses the semiconductor device of claim 7, wherein one or more of the cells comprises a source structure 112 comprising an uninterrupted source finger 112. Allowable Subject Matter Claims 2-3 and 6 (after objection is overcome) are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Allowable Subject Matter Claims 9-17 and 18 (after objection is overcome) are allowed. The following is an examiner’s statement of reasons for allowance: The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed semiconductor device comprising a Group Ill nitride transistor device and a Schottky barrier diode integrated in a Group III nitride body, the semiconductor device comprising: each section forming a source contact to the Group Ill nitride body; and one or more Schottky metal contacts, at least one Schottky metal contact being arranged on the Group Ill nitride body between and spaced apart from neighbouring ones of the source contacts, wherein the ohmic layer further extends over and is electrically insulated from the gate electrode structure and extends onto the one or more Schottky metal contacts so as to electrically couple the two or more source contacts and the one or more Schottky contacts to one another in combination with all other limitations as recited in claim 9. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed method of fabricating a semiconductor device, the method comprising: forming a Schottky metal layer in the first opening to form a Schottky contact to the Group Ill nitride body; forming an ohmic metal layer in the second openings to form ohmic source contacts to the Group III nitride layer and further forming the ohmic metal layer on the insulation layer and on the Schottky metal layer in the first opening to electrically connect the Schottky contact and the source contacts in combination with all other limitations as recited in claim 15. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BILKIS . JAHAN Primary Examiner Art Unit 2817 /BILKIS JAHAN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jul 14, 2023
Application Filed
Dec 27, 2025
Non-Final Rejection — §102
Apr 08, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+10.5%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 892 resolved cases by this examiner. Grant probability derived from career allow rate.

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