DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on January 19, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 14 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Ozaki et al. (US 2015/0295074, hereinafter Ozaki).
An alternative interpretation of Ozaki, differing from the previous Office Action filed on 10/28/2025, has been applied.
Regarding claim 1, Ozaki discloses for a Group III nitride-based semiconductor device, comprising that
a multilayer Group III nitride-based structure (compound semiconductor stacked structure 202, Fig. 5, also see 202a-202e, Fig. 3A) comprising a first major surface (top surface of 202 or cap layer 202e, Fig. 5, 3A);
a source electrode (source electrode 205s, Fig. 5), a gate electrode (gate electrode 205g, Fig. 5) and a drain electrode (drain electrode 205d, Fig. 5) arranged on the first major surface (top surface of 202 or 202e, Fig. 5), wherein the gate electrode (205g, Fig. 5) is laterally arranged between the source electrode (205s, Fig. 5) and the drain electrode (205d, Fig. 5); and
a metallization structure (wiring 216s/216d, Fig. 5) arranged on the first major surface (top surface of 202 or 202e, Fig. 5), because the wiring 216s and 216d by Ozaki are arranged indirectly on the top surface of the compound semiconductor stacked structure 202 (Fig. 5), and
comprising an electrically insulating layer (porous electrical insulating film 209, Fig. 5) arranged on the source electrode (205s, Fig. 5), the gate electrode (205g, Fig. 5) and the drain electrode (205d, Fig. 5), because Applicants do not specifically claim that an electrically insulating layer is arranged directly on the source electrode, the gate electrode and the drain electrode, and the porous electrical insulating film by Ozaki is arranged indirectly on the source, drain and gate electrodes (Fig. 5) and a conductive redistribution structure (source pad 1226s/drain pad 1226d/gate pad 1226g, source lead 1232s/drain lead 1232d/gate lead 1232g, and wires 1235s/1235d/1235g) electrically connected to the source electrode (205s, Fig. 5), the gate electrode (205g, Fig. 5) and the drain electrode (205d, Fig. 5), because Applicants do not specifically claim what a conductive redistribution structure is made of, what it does, and/or how it looks like, each electrical pad, lead and wire of source, drain and gate electrodes by Ozaki are electrically connected to source electrode 205s, drain electrode 205d, and gate electrode 205g, respectively ([0070]), therefore, it can correspond to the conductive redistribution structure in the claimed invention,
wherein one or more cavities (cavity 213, Fig. 5) are located in the electrically insulating layer (209, Fig. 5), and are devoid of the source electrode, the gate electrode and the drain electrode, because as shown in the attached annotated illustration of Fig. 5 of Ozaki below, the cavity 213 (inside of the dotted box, Fig. 5 below) does not include the gate electrode 205g, but the cavity 213 is in contact with the catalyst film 207 encapsulating the gate electrode 205g; the Examiner notes that the Merriam-Webster dictionary defines a word “cavity” as “an unfilled space within a mass”, and therefore, a word or term “cavity” itself would not include any elements such as a source, drain, or gate electrode; the Examiner also notes that the claimed invention is directed to a final structure of a semiconductor device, not a method of manufacturing a semiconductor device, and therefore, in the final structure of the claimed semiconductor device, the claimed one or more cavities would inherently be devoid any electrodes, especially when Applicants do not specifically claim a shape, configuration or arrangement of the claimed one or more cavities.
PNG
media_image1.png
2475
3146
media_image1.png
Greyscale
Regarding claim 2, Ozaki further discloses for the Group III nitride-based semiconductor device of claim 1 that the one or more cavities (213, Fig. 5) are filled with a gas or a vacuum and have a dielectric constant that is lower than the dielectric constant of the electrically insulating layer, because the cavity 213 by Ozaki is formed by a decomposition process of the organic film 208 (Fig. 3K) using ultraviolet light irradiation (Fig. 3L, [0027]) and “components of the organic film vaporized by the decomposition are discharged outside the porous electrical insulating film via openings of the porous electrical insulating film” (emphasis added, [0027], Fig. 3L), since the cavity 213 where the organic film 208 has been removed remains unfilled after decomposition (Figs. 3-5), therefore, the cavity (or void) is formed in the space previously occupied by the organic layer, and such a cavity would inherently contains air or vacuum, depending on subsequent sealing conditions, as no material is present to occupy the void; the porous electrical insulating layer 209 by Ozaki is a porous silica formed by a spin-coating method ([0047]) and the dielectric constant of a porous silica is approximately 3.9 for dense silica and 2.1 with 27.4% porosity (Examiner’s search results) and the dielectric constant of air is approximately 1.0 and 1.0 by definition for vacuum, therefore, the dielectric constant of air or vacuum inside the cavity 213 is lower than the dielectric constant of the porous silica layer 209 by Ozaki.
Regarding claim 3, Ozaki further discloses for the Group III nitride-based semiconductor device of claim 1 that the one or more cavities (213, Fig. 5) are arranged laterally between the source electrode (205s, Fig. 5) and the gate electrode (205g, Fig. 5), because a lower left-side portion of the cavity is formed laterally between the source electrode 205s and the gate electrode 205g (Fig. 5) and/or laterally between the gate electrode (205g, Fig. 5) and the drain electrode (205d, Fig. 5), because the lower right-side portion of the cavity is formed between the gate electrode 205g and the drain electrode 205d (Fig. 5) and/or are positioned above the gate electrode (205g, Fig. 5) and/or have an elongate form having a length that extends substantially parallel to the gate electrode (205g, Fig. 5), because an upper portion of the cavity 213 by Ozaki is positioned above the gate electrode 205g, elongated laterally, and extended substantially parallel to the top surface of the gate electrode 205g (Fig. 5).
Regarding claim 14, Ozaki further discloses for the Group III nitride-based semiconductor device of claim 1 that the multilayer Group III nitride-based structure (202, Fig. 3A) comprises a Group III nitride channel layer (electron transit layer 202b, Fig. 3A) and a Group III nitride barrier layer (spacer layer 202c, Fig. 3A) arranged on the Group Ill nitride channel layer (202b, Fig. 3A) and forming a heterojunction therebetween capable of supporting a two-dimensional charge gas, because “two-dimensional electron gas (2DEG) exists in a vicinity of an upper surface of the electron transit layer 202b” ([0034]), and wherein the source electrode (205s, Fig. 5), the gate electrode (205g, Fig. 5) and the drain electrode (205d, Fig. 5) are arranged on or in the Group Ill nitride barrier layer (arranged on the stack 202, Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over by Ozaki et al. (US 2015/0295074, hereinafter Ozaki) in view of Ahn et al. (US 2006/0121658, hereinafter Ahn).
Regarding claim 4, Ozaki differs from the claimed invention by not showing that a field plate arranged on the first major surface between the gate electrode and the drain electrode, wherein the one or more cavities are arranged laterally between the field plate and the drain electrode and/or are positioned above the field plate.
However, Ahn discloses for a HEMT using a compound semiconductor that the HEMT device includes the pair of T-shaped gates 200, the source and drain contacts 130 on the left and right side of the T-shaped gates 200 (see attached and annotated Fig. 1I, below) that are provided on the active layer 110 and the substrate 100, and since the substrate 100 includes GaN substrate ([0010]), a composite layer of 100/110 by Ahn can correspond to the multilayer Group III nitride-based structure in the claimed invention; the T-shaped gate on the right side of Fig. 1I is arranged between the T-shaped gate on the left side of Fig. 1l and the source/drain contact 130 on the right side of Fig. 1I (i.e., the drain electrode in the claimed invention); Applicants do not specifically claim what the field plate is made of, what it looks like, and/or what it does, and the T-shaped gate 200 disclosed by Ahn is made of metal (a gate metal 200, [0044]) and controls electrical characteristics of an active layer such as an electric field in and adjacent the channel layer, and overall electrical and electronic performance of the HEMT device, consistent with the known function of a field plate in such devices, therefore, the T-shaped gate 100 would correspond to the field plate in the claimed invention; in this case, a lower portion of the T-shaped gate 100, adjacent to the source/drain contact 130 on the right side, defines a cavity that is arranged laterally between the T-shaped gate 200 and the source/drain contact 130 (see Fig. 1I below), and such a cavity would be remain (substantially) unfilled due to an upper portion of the T-shaped gate 200 shadowing the underlying device structure. Examiner notes that a word “cavity” can include a hole or recess with a small opening on one side, like a cavity of a human tooth or cavities present in a human body, therefore, it does not require a fully enclosed void.
PNG
media_image2.png
810
1429
media_image2.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a cavity filled with air can be formed laterally between a metallic field plate (or metallic conductive layer) and a drain electrode of the HEMT device, as disclosed by Ahn, in order to improve the overall performance of the HEMT device.
Claims 5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over by Ozaki et al. (US 2015/0295074, hereinafter Ozaki) in view of Ahn et al. (US 2006/0121658, hereinafter Ahn) as applied to claim 4 above, and further in view of LaRoche et al. (US 11,239,326; hereinafter LaRoche). The teachings of Ozaki in view of Ahn are discussed in claim 4 above.
Regarding claim 5, Ozaki in view of Ahn does not explicitly disclose that the metallization structure comprises a lateral gate redistribution structure that is electrically connected to the gate electrode by one or more gate vias and a lateral field plate redistribution structure that is electrically connected to the field plate by one or more field plate vias.
However, LaRoche discloses for a group III nitride-based semiconductor HEMT device that the device includes a plurality of conductive interconnects or vias (Fig. 2B), which corresponds to the metallization structure in the claimed invention, the gate electrode structure 141 includes the gate electrical contact structure 14GC, the gate metal layer 14a and the dielectric layer 14b, and since the gate metal layer 14a is electrically connected to the gate electrical contact structure 14GC, and therefore, the gate metal layer 14 by LaRoche can correspond to the lateral gate redistribution structure in the claimed invention; the field plate 23 by LaRoche is electrically connected to the field plate interconnect 27, and therefore, the field plate interconnect 27 by LaRoche can correspond to the lateral field plate redistribution structure in the claimed invention; one of ordinary skill in the art would readily recognize that additional conductive interconnects or vias may be provided to electrically connect the source, drain and gate electrodes of the HEMT device to external circuits such as a power supply or control circuitry, as conventionally practiced in the art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that additional conductive interconnects or vias would be provided to electrically connect the source, drain, gate electrodes and field plate to the external circuits, as disclosed by LaRoche, as conventionally practiced in the semiconductor industry.
Regarding claim 7, LaRoche further discloses that the lateral field plate redistribution structure (271 or 272, Fig. 2B) extends over and is vertically spaced apart from the gate electrode (14GC, Fig. 2B).
Regarding claim 8, LaRoche further discloses that the source electrode (source electrode 22, Fig. 2B) is electrically coupled to the lateral field plate redistribution structure (271 or 272, Fig. 2B) by one or more source conductive vias (electrically conductive etch stop layer 42ES, Fig. 3M), because the source electrode structure 22 by LaRoche includes source electrode “S” and the electrically conductive etch stop layers 42ES (Fig. 3M) and it is electrically connected to the field plate interconnect 27 by the copper layer 54a/54b (Figs. 2B, 3M).
Allowable Subject Matter
Claims 16-22 are allowed.
Claims 6, 9-13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed in January 19, 2025 have been fully considered but they are not persuasive, for the reasons discussed above, an alternate interpretation of Ozaki, different from the previous Office Action, in connection with the rejections of claim 1 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815