DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 12/17/2025.
Currently claims 1-20 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-17, in the reply filed on 12/17/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/14/2023 and 03/05/2024 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0109074 A1 (Pesic) and further in view of US 2006/0099724 A1 (Hsu).
Regarding claim 1, Pesic discloses, a memory cell comprising:
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a first electrode (302; first electrode; Fig. 3A; [0027]);
a second electrode (304; second electrode; Fig. 3A; [0027]); and
a memory element (306; ferroelectric layer; Fig. 3A; [0027]) disposed between the first electrode (302) and the second electrode (304), the memory element (306) comprising a spontaneously polarizable material (Fig. 3A; [0027]),
the first electrode (302), the second electrode (304), and the memory element (306) forming a memory capacitor (it makes a memory capacitor by definition),
But Pesic fails to teach explicitly, wherein at least one of the first electrode or the second electrode comprises: an electrically conductive electrode layer, and a functional layer comprising a semi-conductive material, wherein the functional layer is in direct physical contact with the memory element.
However, in analogous art, Hsu discloses, wherein at least one of the first electrode (as annotated on Fig. 6; [0033]) or the second electrode comprises:
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an electrically conductive electrode layer (BE; Fig. 6; bottom electrode; [0023]), and
a functional layer (buffer; Fig. 6; semiconductive metal oxide; [0033]) comprising a semi-conductive material, wherein the functional layer (buffer) is in direct physical contact (as evident in Fig. 6) with the memory element (CMR; memory film; Fig. 6; [0026]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pesic and Hsu before him/her, to modify the teachings of a memory cell using a ferroelectric layer as taught by Pesic and to include the teachings of a semiconductive buffer layer in the bottom or top electrode as taught by Hsu since semiconductive buffer layer protects the memory film by acting as an oxygen diffusion barrier between the memory film and the electrode ([0032]) and thereby protect its integrity. Absent this important teaching in Pesic, a person with ordinary skill in the art would be motivated to reach out to Hsu while forming a memory cell of Pesic.
Regarding claim 3, the combination of Pesic and Hsu teaches, the memory cell according to claim 1, wherein the semi-conductive material is a semi-conductive metal oxide ([0033]; Hsu Reference).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Pesic and Hsu as applied to claim 3 and further in view of US 2023/0380179 A1 (Lin).
Regarding claim 4, the combination of Pesic and Hsu teaches the semi-conductive metal oxide (Hsu Reference) but fails to teach explicitly, the memory cell according to claim 3, the metal oxide is a tungsten oxide.
However, in analogous art, Lin discloses, the metal oxide is a tungsten oxide ([0047]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pesic, Hsu and Lin before him/her, to modify the teachings of a memory cell using a semi-conductive metal oxide as a functional layer as taught by Pesic and Hsu and to include the teachings of metal oxide being a tungsten oxide as taught by Lin since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Pesic, a person with ordinary skill in the art would be motivated to reach out to Lin while forming a memory cell of Pesic.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Pesic and Hsu as applied to claim 1 and further in view of US 2019/0130956 A1 (Muller).
Regarding claim 6, the combination of Pesic and Hsu fails to teach explicitly, the memory cell according to claim 1, wherein the spontaneously polarizable material of the memory element is a remanent-polarizable material.
However, in analogous art, Muller discloses, the memory cell according to claim 1, wherein the spontaneously polarizable material of the memory element is a remanent-polarizable material ([0062]; Muller teaches that the remanent-polarizable layer may include any type of remanent-polarizable and/or spontaneously-polarizable material, e.g., a ferroelectric material, an anti-ferroelectric material, an anti-ferroelectric-like material; therefore, it is possible to interchange the materials without any significant change of memory cell characteristics).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pesic, Hsu and Muller before him/her, to modify the teachings of a memory cell using a semi-conductive metal oxide as a functional layer as taught by Pesic and Hsu and to include the teachings of spontaneously polarizable material of the memory element can be interchangeably used with remanent-polarizable material as taught by Muller since in MPEP 2143 (I) (B), it is stated that Simple substitution of one known element for another to obtain predictable results is obvious. Absent this important teaching in Pesic, a person with ordinary skill in the art would be motivated to reach out to Muller while forming a memory cell of Pesic.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Pesic and Hsu as applied to claim 1 and further in view of US 2023/0413550 A1 (Kong).
Regarding claim 13, the combination of Pesic and Hsu fails to teach explicitly, the memory cell according to claim 1, wherein the semi-conductive material is amorphous.
However, in analogous art, Kong discloses, the memory cell according to claim 1, wherein the semi-conductive material is amorphous ([0037]; Kong teaches that the charge trap material 138 may be formed of a semiconductive material (e.g., polycrystalline or amorphous semiconductor material, including at least one elemental semiconductor element and/or including at least one compound semiconductor material, such as conductive nanoparticles (e.g., ruthenium nanoparticles) and/or metal dots).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pesic, Hsu and Kong before him/her, to modify the teachings of a memory cell using a semi-conductive metal oxide as a functional layer as taught by Pesic and Hsu and to include the teachings of semi-conductive material of the memory element can be interchangeably used with amorphous material as taught by Kong since in MPEP 2143 (I) (B), it is stated that Simple substitution of one known element for another to obtain predictable results is obvious. Absent this important teaching in Pesic, a person with ordinary skill in the art would be motivated to reach out to Kong while forming a memory cell of Pesic.
Allowable Subject Matter
Claims 2, 5, 7-12 and 14-16 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 2, the closest prior art, US 2022/0109074 A1 (Pesic), in combination with US 2006/0099724 A1 (Hsu), US 2023/0380179 A1 (Lin) and US 2023/0413550 A1 (Kong), fails to disclose, “the memory cell according to claim 1, wherein an average grain width of the spontaneously polarizable material is greater than 20 nm”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 5, the closest prior art, US 2022/0109074 A1 (Pesic), in combination with US 2006/0099724 A1 (Hsu), US 2023/0380179 A1 (Lin) and US 2023/0413550 A1 (Kong), fails to disclose, “the memory cell according to claim 1, wherein the semi-conductive material is configured to store and release oxygen by application of an electric field via the first electrode and the second electrode”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 7, the closest prior art, US 2022/0109074 A1 (Pesic), in combination with US 2006/0099724 A1 (Hsu), US 2023/0380179 A1 (Lin) and US 2023/0413550 A1 (Kong), fails to disclose, “the memory cell according to claim 1, wherein the first electrode comprises a first functional layer and wherein the second electrode comprises a second functional layer, and wherein the first functional layer comprises a first oxygen concentration different from a second oxygen concentration of the second functional layer”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 8, the closest prior art, US 2022/0109074 A1 (Pesic), in combination with US 2006/0099724 A1 (Hsu), US 2023/0380179 A1 (Lin) and US 2023/0413550 A1 (Kong), fails to disclose, “the memory cell according to claim 1, wherein the semi-conductive material is configured to change its material properties as a function of an amount of oxygen incorporated therein”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 9, the closest prior art, US 2022/0109074 A1 (Pesic), in combination with US 2006/0099724 A1 (Hsu), US 2023/0380179 A1 (Lin) and US 2023/0413550 A1 (Kong), fails to disclose, “the memory cell according to claim 1, wherein the semi-conductive material is configured to change its material properties by application of an electric field via the first electrode and the second electrode”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 10, the closest prior art, US 2022/0109074 A1 (Pesic), in combination with US 2006/0099724 A1 (Hsu), US 2023/0380179 A1 (Lin) and US 2023/0413550 A1 (Kong), fails to disclose, “the memory cell according to claim 1, wherein the semi-conductive material is configured to change its material properties as a function of an amount of oxygen incorporated in the spontaneously polarizable material”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 14, the closest prior art, US 2022/0109074 A1 (Pesic), in combination with US 2006/0099724 A1 (Hsu), US 2023/0380179 A1 (Lin) and US 2023/0413550 A1 (Kong), fails to disclose, “the memory cell according to claim 1, wherein the spontaneously polarizable material is configured to change its material properties based on at least one of a transfer of oxygen from the functional layer or a transfer of oxygen to the functional layer”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 15, the closest prior art, US 2022/0109074 A1 (Pesic), in combination with US 2006/0099724 A1 (Hsu), US 2023/0380179 A1 (Lin) and US 2023/0413550 A1 (Kong), fails to disclose, “the memory cell according to claim 1, wherein the spontaneously polarizable material is configured to change its material properties as a function of an amount of oxygen incorporated in the semi-conductive material of the functional layer”, in combination with the additionally claimed features, as are claimed by the Applicant.
Claims 11-12 and 16 are also objected to due to their dependence on an objected base claim.
Claim 17 is allowed.
The following is the examiner’s statement of reasons of allowance.
Independent claim 17 is allowable because the closest prior art US Patent Pub # US 2022/0109074 A1 to Pesic teaches,
a memory cell comprising:
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a first electrode (302; first electrode; Fig. 3A; [0027]);
a second electrode (304; second electrode; Fig. 3A; [0027]); and
a memory element (306; ferroelectric layer; Fig. 3A; [0027]) disposed between the first electrode (302) and the second electrode (304), the memory element (306) comprising a spontaneously polarizable material (Fig. 3A; [0027]),
the first electrode (302), the second electrode (304), and the memory element (306) forming a memory capacitor (it makes a memory capacitor by definition),
Furthermore, US Patent Pub # US 2006/0099724 A1 to Hsu teaches, wherein at least one of the first electrode (as annotated on Fig. 6; [0033]) or the second electrode comprises:
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an electrically conductive electrode layer (BE; Fig. 6; bottom electrode; [0023]), and
a functional layer (buffer; Fig. 6; semiconductive metal oxide; [0033]) in direct physical contact (as evident in Fig. 6) with the memory element (CMR; memory film; Fig. 6; [0026]).
However, neither Pesic nor any cited prior art, appear to explicitly disclose, in context, wherein the functional layer is configured to store and release oxygen by application of an electric field via the first electrode and the second electrode.
Examiner’s Note: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by “wherein the functional layer is configured to store and release oxygen by application of an electric field via the first electrode and the second electrode”. Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, the claim is deemed patentable over the prior arts.
Specifically, the aforementioned ‘wherein the functional layer is configured to store and release oxygen by application of an electric field via the first electrode and the second electrode,’ is material to the inventive concept of the application at hand to fabricate a novel memory cell including a spontaneous-polarizable material whose polarization state may be changed in a controlled fashion to store data in the memory cell.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2021/0125656 A1 (Muller) - A memory cell arrangement is provided that may include a control circuit configured to supply a precondition signal and one of at least two write signals to a memory cell of the memory cell arrangement, the memory cell including a field-effect transistor structure and a remanent-polarizable layer, wherein the precondition signal is configured to bring the memory cell from an actual condition into a predefined condition, wherein the predefined condition is associated with a predefined threshold voltage of the field-effect transistor structure of the memory cell, and wherein the at least two write signals are configured to write the memory cell selectively into a first memory state or into a second memory state.
US 2021/0091097 A1 (Mennenga) – A memory cell is disclosed including a first control line and a second control line; a plurality of memory structures disposed between the first control line and the second control line, wherein each memory structure of the plurality of memory structures comprises a third control line, a first memory cell and a second memory cell; wherein, for each memory structure of the plurality of memory structures, the first memory cell and the second memory cell are coupled to each other by the third control line; wherein, for each memory structure of the plurality of memory structures, the first memory cell is coupled to the first control line and the second memory cell is coupled to the second control line.
US 2021/0082958 A1 (Mennenga) - A memory cell is disclosed including a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
02/06/2026