DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group-I (Claims 1-34) in the reply filed on 12/01/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Hirose et al. (US PGpub: 2010/0219785 A1),herein after Hirose, in view Li et al. (US PGpub: 2016/0218008 A1), herein after Li.
Regarding claim 1, Hirose teaches, in FIG. 5, 19 and 30, a power semiconductor device, comprising:
a semiconductor body coupled to a first load terminal at a first side and to a second load terminal at a second side that is opposite to the first side with respect to a vertical direction, wherein the semiconductor body comprises an active region configured to conduct a load current between the first load terminal (as annotated in the Figure) and the second load terminal (as annotated in the Figure);
at the first side and in the active region, a plurality of first trenches (60) extending in the semiconductor body along the vertical direction, wherein the first trenches are arranged adjacent to each other along a first lateral direction and extend along a second lateral direction (as in FIG), thereby laterally confining mesas of the semiconductor body exhibiting a respective stripe configuration, wherein at least some of the first trenches are control trenches housing a respective control trench electrode (62, Paragraph [0062]) for controlling the load current in first semiconductor channel structures formed in the respective adjacent mesa portion (60 along with other 57A controls the load current); and
at the first side and in the active region (59, 52, 65 makes the active region), a deep cross trench (as annotated in Figure) extending into the semiconductor body (58 and 52) along the vertical direction below bottoms of the first trenches (60) and traversing a region corresponding to lower vertical projections of portions of the mesas (as annotated in the Figure),
wherein:
the deep cross trench includes a deep cross trench electrode (57A) and a deep cross trench insulator (56) electrically insulating the deep cross trench electrode (57A) from the semiconductor body (as in Figure);
each of the control trenches (62, Paragraph [0062]) includes a control trench insulator (61) electrically insulating the control trench electrode (62) from the semiconductor body (as in Figure); and
Hirose does not explicitly teach thickness of the deep cross trench insulator amounts to at least 150% of an average thickness of the control trench insulators.
However, Li teaches deep trenches are 1.5 times or double or more in thickness as shown in Figure. Moreover, this thickness of the deep trenches or control trenches are subject to change depending on the functionality of the devices (FIG. 1A-1C and their description). Even in Hirose Fig 19, deep trenches are almost double or more compared to control trench thickness.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Hirose’s power semiconductor device with trench thickness as taught in Li so that the device functionality can be improved and the reliability of switching speed can be improved.
Regarding claim 2, Hirose teaches (in view of Li) the power semiconductor device of claim 1, wherein at least an upmost portion (top portion of control trench as in Figure) of the deep cross trench (as annotated in Figure) is made of an insulating material (56), the upmost portion vertically overlapping with at least an average upmost quarter of the first trenches (whether it is overlapping with at least an average upmost quarter or more or less of the first trenches, it is subject to manipulation. This overlapping can be changed as known to people skilled in the art in order to meet efficient device).
Regarding claim 3, Hirose teaches the power semiconductor device of claim 2, wherein the upmost portion (of the deep cross trench) vertically overlaps with at least the entire average vertical extension of the first trenches (as annotated in Figure. The top portion of control trenches overlaps partially with the top portions of first trenches as in Figure).
Regarding claim 4, Hirose teaches the power semiconductor device of claim 3, wherein the upmost portion (of the deep cross trench) vertically overlaps with at least the entire average vertical extension of the first trenches (as annotated in Figure. The top portion of control trenches overlaps partially with the top portions of first trenches as in Figure).
Regarding claim 5, Hirose teaches the power semiconductor device of claim 4, wherein the deep cross trench is devoid of any trench electrode (the insulating portion is devoid of any trench electrode).
Regarding claim 6, Hirose teaches the power semiconductor device of claim 1, further comprising first contacts (54) to establish an electrical connection between the first semiconductor channel structures and the first load terminal (54 electrically connects semiconductor channel with the load marked by R3 as shown in FIG. 5).
Regarding claim 7, Hirose teaches the power semiconductor device of claim 6, wherein the first trenches further comprise source trenches (60) including a respective source trench electrode electrically connected to the first load terminal, wherein each of the first contacts (as shown in FIG. 30) laterally overlaps with a respective one of the source trench electrodes (62) .
Regarding claim 8, Hirose teaches the power semiconductor device of claim 6, wherein the first contacts (54) are embodied as planar contacts (these contacts in 54 can be considered planar contacts).
Regarding claim 9, Hirose teaches the power semiconductor device of claim 1, wherein the mesas form a substantially horizontal portion (horizontal portion containing 54, 58) of the surface of the first side and are not equipped with a contact groove (they do not have contact grooves).
Regarding claim 10, Hirose teaches the power semiconductor device of claim 1, wherein the deep cross trench (as annotated in Figure) extends substantially perpendicularly with respect to the first trenches and the mesas (as shown in Figure).
Regarding claim 11, Hirose teaches (in view of Li) the power semiconductor device of claim 1, wherein the deep cross trench exhibits a total vertical extension within the range of 150% to 250% of the average total vertical extension of the first trenches, and/or wherein the deep cross trench exhibits a total lateral width within the range of 50% to 150% of the average total lateral width of the first trenches (deep trenches are 1.5 times or double or more in thickness as shown in Figure. Moreover, this thickness of the deep trenches or control trenches are subject to change depending on the functionality of the devices. Even in Hirose Fig 19, deep trenches are almost double or more compared to control trench thickness.).
Regarding claim 12, Hirose teaches the power semiconductor device of claim 1, wherein the deep cross trench includes a deep cross trench electrode,(57A) wherein the deep cross trench electrode (57A) is electrically connected with the control trench electrodes (62), the first load terminal (marked in Figure: 19), or another electrical potential.
Regarding claim 13, Hirose teaches the power semiconductor device of claim 12, further comprising an edge termination region surrounding the active region, wherein the deep cross trench at least partially extends into the edge termination region (52, low concentration region), and wherein electrical connection of the deep cross trench electrode is established in the edge termination region (deep cross trench is extended to Edge termination region 52).
Regarding claim 14, Hirose teaches the power semiconductor device of claim 1, further comprising additional deep cross trenches, wherein the deep cross trench and the additional deep cross trenches are arranged adjacent to each other along the second lateral direction (FIG. 30, where additional deep trench is arranged on 2nd lateral direction).
Regarding claim 15, Hirose teaches the power semiconductor device of claim 14, wherein the average distance between adjacent deep cross trenches is within the range of 50% to 200% of the average distance between adjacent first trenches (deep trenches are 1.5 times or double or more in thickness as shown in Figure. Moreover, this thickness of the deep trenches or control trenches are subject to change depending on the functionality of the devices. Even in Hirose Fig 19, deep trenches are almost double or more compared to control trench thickness).
Regarding claim 16, Hirose teaches the power semiconductor device of claim 1, wherein in the active region, the semiconductor body comprises a drift region of a first conductivity type (P-, region 58) and a barrier region of either the first conductivity type or a second conductivity type, and wherein the barrier region (52, n conductivity) couples at least some of the first semiconductor channel structures to the drift region (As in FIG. 30).
Regarding claim 17, Hirose teaches the power semiconductor device of claim 16, wherein the barrier region exhibits a greater dopant concentration as compared to the drift region (so, barrier region has greater doping concentration as it is n type and drift region has P- which mean lesser concentration) and/or a total vertical extension within the range of 30% to 150% of the total average vertical extension of the first trenches.
Regarding claim 18, Hirose teaches the power semiconductor device of claim 1, wherein the mesas include first type mesas and second type mesas (58 with P- conductivity), wherein the first type mesas comprise the first semiconductor channel structures controlled by the control trench electrodes (as annotated) , wherein at least one of the second type mesas (56 having N+ conductivity) is electrically connected to the first load terminal and not controlled by the control trench electrodes, and wherein the deep cross trench (55) is arranged adjacent to at least one second type mesa (as in FIG. 5).
Regarding claim 19, Hirose teaches, in FIG. 5, 19 and 30, a power semiconductor device, comprising:
a semiconductor body coupled to a first load terminal at a first side and to a second load terminal at a second side that is opposite to the first side with respect to a vertical direction, wherein the semiconductor body comprises an active region configured to conduct a load current between the first load terminal (as annotated in the Figure) and the second load terminal (as annotated in the Figure);
at the first side and in the active region, a plurality of first trenches (60) extending in the semiconductor body along the vertical direction, wherein the first trenches are arranged adjacent to each other along a first lateral direction and extend along a second lateral direction (as in FIG), thereby laterally confining mesas of the semiconductor body exhibiting a respective stripe configuration, wherein at least some of the first trenches are control trenches housing a respective control trench electrode (62, Paragraph [0062]) for controlling the load current in first semiconductor channel structures formed in the respective adjacent mesa portion (60 along with other 57A controls the load current); and
at the first side and in the active region (59, 52, 65 makes the active region), a deep cross trench (as annotated in Figure) extending into the semiconductor body (58 and 52) along the vertical direction below bottoms of the first trenches (60) and traversing a region corresponding to lower vertical projections of portions of the mesas (as annotated in the Figure),
wherein at least an upmost portion (top portion of control trench as in Figure) of the deep cross trench (as annotated in Figure) is made of an insulating material (56).
Hirose does not explicitly teach the upmost portion vertically overlapping with at least the average upmost quarter of the first trenches.
However, Li teaches whether it is overlapping with at least an average upmost quarter or more or less of the first trenches (FIG. 1A-1C and their description), it is subject to manipulation. This overlapping can be changed as known to people skilled in the art in order to meet efficient device .
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Hirose’s power semiconductor device with trench thickness as taught in Li so that the device functionality can be improved and the reliability of switching speed can be improved.
Regarding claim 20, Hirose teaches the power semiconductor device of claim 19, wherein the upmost portion (of the deep cross trench) vertically overlaps with at least the entire average vertical extension of the first trenches (as annotated in Figure. The top portion of control trenches overlaps partially with the top portions of first trenches as in Figure).
Regarding claim 21, Hirose teaches the power semiconductor device of claim 19, wherein the deep cross trench is devoid of any trench electrode (the insulating portion is devoid of any trench electrode).
Regarding claim 22, Hirose teaches the power semiconductor device of claim 19, further comprising first contacts to establish an electrical connection between the first semiconductor channel structures and the first load terminal.
Regarding claim 23, Hirose teaches the power semiconductor device of claim 22, wherein the first trenches further comprise source trenches including a respective source trench electrode electrically connected to the first load terminal, and wherein each of the first contacts laterally overlaps with a respective one of the source trench electrodes.
Regarding claim 24, Hirose teaches the power semiconductor device of claim 22, wherein the first contacts (54) are embodied as planar contacts (these contacts in 54 can be considered planar contacts).
Regarding claim 25, Hirose teaches the power semiconductor device of claim 19, wherein the mesas form a substantially horizontal portion (horizontal portion containing 54, 58) of the surface of the first side and are not equipped with a contact groove (they do not have contact grooves).
Regarding claim 26, Hirose teaches the power semiconductor device of claim 19, wherein the deep cross trench (as annotated in Figure) extends substantially perpendicularly with respect to the first trenches and the mesas (as shown in Figure).
Regarding claim 27, Hirose teaches (in view of Li) the power semiconductor device of claim 19, wherein the deep cross trench exhibits a total vertical extension within the range of 150% to 250% of the average total vertical extension of the first trenches, and/or wherein the deep cross trench exhibits a total lateral width within the range of 50% to 150% of the average total lateral width of the first trenches (deep trenches are 1.5 times or double or more in thickness as shown in Figure. Moreover, this thickness of the deep trenches or control trenches are subject to change depending on the functionality of the devices).
Regarding claim 28, Hirose teaches the power semiconductor device of claim 19, wherein the deep cross trench includes a deep cross trench electrode,(57A) wherein the deep cross trench electrode (57A) is electrically connected with the control trench electrodes (62), the first load terminal (marked in Figure: 19), or another electrical potential.
Regarding claim 29, Hirose teaches the power semiconductor device of claim 28, further comprising an edge termination region surrounding the active region, wherein the deep cross trench at least partially extends into the edge termination region (52, low concentration region), and wherein electrical connection of the deep cross trench electrode is established in the edge termination region (deep cross trench is extended to Edge termination region 52).
Regarding claim 30, Hirose teaches the power semiconductor device of claim 19, further comprising additional deep cross trenches, wherein the deep cross trench and the additional deep cross trenches are arranged adjacent to each other along the second lateral direction (FIG. 30, where additional deep trench is arranged on 2nd lateral direction).
Regarding claim 31, Hirose teaches (in view of Li) the power semiconductor device of claim 30, wherein the average distance between adjacent deep cross trenches is within the range of 50% to 200% of the average distance between adjacent first trenches (deep trenches are 1.5 times or double or more in thickness as shown in Figure. Moreover, this thickness of the deep trenches or control trenches are subject to change depending on the functionality of the devices. Even in Hirose Fig 19, deep trenches are almost double or more compared to control trench thickness).
Regarding claim 32, Hirose teaches the power semiconductor device of claim 19, wherein in the active region, the semiconductor body comprises a drift region of a first conductivity type (P-, region 58) and a barrier region of either the first conductivity type or a second conductivity type, and wherein the barrier region (52, n conductivity) couples at least some of the first semiconductor channel structures to the drift region (As in FIG. 30).
Regarding claim 33, Hirose teaches the power semiconductor device of claim 32, wherein the barrier region exhibits a greater dopant concentration as compared to the drift region (so, barrier region has greater doping concentration as it is n type and drift region has P- which mean lesser concentration) and/or a total vertical extension within the range of 30% to 150% of the total average vertical extension of the first trenches.
Regarding claim 34, Hirose teaches the power semiconductor device of claim 19, wherein the mesas include first type mesas and second type mesas (58 with P- conductivity), wherein the first type mesas comprise the first semiconductor channel structures controlled by the control trench electrodes (as annotated) , wherein at least one of the second type mesas (56 having N+ conductivity) is electrically connected to the first load terminal and not controlled by the control trench electrodes, and wherein the deep cross trench (55) is arranged adjacent to at least one second type mesa (as in FIG. 5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897