DETAILED ACTION
This correspondence is in response to the communications received February 2, 2026. Claims 1-14 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I structure claims 1-14 in the reply filed on April 1, 2026 is acknowledged. Claims 15-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II method of making a structure claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 1, 2026.
Related Prior Art
Wang et al. (US 2024/0107761) Fig. 5, shown below. The via/plate 202/206 electrically connects to regular word lines 502, “interconnect line 206 can be electrically connected to conductive layer 502.”, ¶ 0074. However, Wang does not explicitly disclose, “electrically conductive layers that are laterally spaced apart by a respective set of dielectric material portions”.
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Izumi et al. (US 2016/0322374) Fig. 12 to 13, shown below.
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 3A-3C and 9A-9C, a semiconductor structure, comprising:
an alternating stack of insulating layers (¶ 0145, “insulating layers 32”) and composite layers (“the composite layers (142, 242, 342, 442, 542, 46) comprise a respective set of electrically conductive layers 46 that are laterally spaced apart by a respective set of dielectric material portions (142, 242, 342, 442, 542)”, ¶ 0145, hereinafter referred to as ‘DMP’),
wherein each of the composite layers comprise a respective set of electrically conductive layers (46) that are laterally spaced apart by a respective set of dielectric material portions (DMP);
memory openings (49, ¶ 0145) vertically extending through portions of the alternating stack and laterally spaced from each of the dielectric material portions (49 spaced from laterally oriented DMP 142, 242, 342, etc.);
memory opening fill structures (58, ¶ 0127, in Figs. 4A-4F) located in the memory openings (in 49),
wherein vertically-extending interfaces between the electrically conductive layers (46) and the dielectric material portions (DMP) are laterally offset from a sidewall of a most proximal one of the memory opening fill structures (49 offset from laterally oriented DMP), and
wherein each of the memory opening fill structures (58) comprises a respective vertical semiconductor channel (¶ 0131, 60L) and a respective vertical stack of memory cells (“respective vertical stack of memory cells (such as portions of a memory material layer 54)”, ¶ 0145); and
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an integrated line-and-via structure (Figs. 9A-9C, shows, “integrated line-and-via structure (48, 84, 86)”, ¶ 0144) comprising a metallic plate portion (48, ¶ 0144) that laterally contacts a first electrically conductive layer (particular one of the plural 46, ¶ 0144) of the electrically conductive layers and further comprising a metallic via portion (86, ¶ 0144) that vertically extends through a subset of the dielectric material portions that overlies the metallic plate portion (portion of DMP above 48).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2022/0005830) in view of Chae et al. (US 8,786,007).
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Regarding claim 1, the prior art of Wu discloses in Fig. 26A-35C, a semiconductor structure (¶ 0093, “the 3D memory device 200 may also include oxide semiconductor (OS) materials as channel layers (or channel pillars) 222a, 222b and 222c.”), comprising:
an alternating stack of insulating layers (“dielectric layers 212”, ¶ 0093) and composite layers (this limitation is interpreted to be the “conductive lines 216”, ¶ 0093 and the portions of “dielectric isolations 232”, ¶ 0112, which are at the vertical level with 216, hereinafter referred to as ‘CL’),
wherein each of the composite layers (CL) comprise a respective set of electrically conductive layers (“conductive lines 216”, ¶ 0093) that are laterally spaced apart by a respective set of dielectric material portions (the portions of “dielectric isolations 232”, ¶ 0112, which are at the vertical level with 216);
memory openings (the discontinuities in stack of 212/CL, where “channel layers (or channel pillars) 222a, 222b and 222c.”, ¶ 0093, and “ferroelectric layer 220a”, ¶ 0093, are located, hereinafter referred to as ‘MO’) vertically extending through portions of the alternating stack (222/220 extend vertically through 212/CL) and laterally spaced from each of the dielectric material portions (MO shown spaced apart laterally from 232);
memory opening fill structures (“channel layers (or channel pillars) 222a, 222b and 222c.”, ¶ 0093, and “ferroelectric layer 220a”, ¶ 0093, hereinafter referred to as ‘MOFS’) located in the memory openings (MOFS located in MO),
wherein vertically-extending interfaces between the electrically conductive layers and the dielectric material portions are laterally offset from a sidewall of a most proximal one of the memory opening fill structures (in the cross sectional view of Fig. 26B, the vertical end faces of 216 are sandwiched between vertical surfaces of 232 and the MOFS), and
wherein each of the memory opening fill structures (MOFS) comprises a respective vertical semiconductor channel (“oxide semiconductor (OS) materials as channel layers (or channel pillars) 222a, 222b and 222c.”, ¶ 0093) and a respective vertical stack of memory cells (“the ferroelectric layer (e.g., 220a, 220b or 220c) may serve as a gate dielectric for each memory cell (e.g., 240a, 240b or 240c).”, ¶ 0093); and
an integrated line-and-via structure comprising a metallic plate portion (extension portions of 216 which form upper facing access points where vias 244 can contact each 216, hereinafter referred to as ‘MPP’) that laterally contacts (MPP is a lateral extension that electrically connects region of MPP to inner active regions of 216 which interact with the memory cell, but does not show MPP as separate and thus able to “contact” 216 as a separate element contacting another element. This deficiency will be addressed below in a combination rejection.) a first electrically conductive layer (one of the 216) of the electrically conductive layers (216) and further comprising a metallic via portion (“conductive contacts 244”, ¶ 0116) that vertically extends through a subset of the dielectric material portions that overlies the metallic plate portion (244 vertically extends through stack of overlying 212/216).
Wu does not disclose that the “metallic plate portion” is a separate element that contacts the “a first electrically conductive layer of the electrically conductive layers”, and therefore does not disclose the limitation of, “an integrated line-and-via structure comprising a metallic plate portion that laterally contacts a first electrically conductive layer of the electrically conductive layers”.
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Chae discloses in Figs. 5, 8-13G, an integrated line-and-via structure comprising a metallic plate portion (“metal layer patterns 142”, col. 11, lines 57-58) that laterally contacts (direct contact between 142 and 122) a first electrically conductive layer (“gate electrodes 122”, col. 11, line 67) of the electrically conductive layers (plural 122, shown). The purpose of the structures disclosed being,
“Embodiments of the inventive concept provide three-dimensional nonvolatile memory devices capable of reducing the resistance of gate electrodes, and methods for fabricating the same.
Embodiments of the inventive concept also provide three-dimensional nonvolatile memory devices capable of preventing process defects, and methods for fabricating the same.”, col. 1, lines 54-60.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “an integrated line-and-via structure comprising a metallic plate portion that laterally contacts a first electrically conductive layer of the electrically conductive layers”, as disclosed by Chae in the system of Wu, for the purpose of reforming the contact region with a process that is more conducive to ideally forming the contact region with reduced process defects and contact resistance . (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2022/0005830) in view of Chae et al. (US 8,786,007) in view of Wang et al. (US 2024/0107761).
Regarding claim 4, the prior art of Wu et al. disclose the semiconductor structure of Claim 1, however Wu does not disclose, “wherein the integrated line-and-via structure comprises a homogeneous metallic material portion that extends continuously from a volume within the metallic plate portion to a volume within the metallic via portion without a material junction therein.”
Wang discloses in Figs. 7I through 7P, wherein the integrated line-and-via structure (the ‘line’ portion being “an interconnect line 743 is formed by depositing a conductive layer through opening 736 to fill lateral recess 740.”, ¶ 0117, and ‘via’ portion being “vertical contact 742”, ¶ 0118) comprises a homogeneous metallic material portion (both portions 743 and 742 are the same metal as shown in the progression of steps from Figs. 7N to 7P) that extends continuously from a volume within the metallic plate portion (740 in Fig. 7N) to a volume within the metallic via portion (736, Fig. 7N) without a material junction therein (continuous material deposited to form regions 743 and 742).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the integrated line-and-via structure comprises a homogeneous metallic material portion that extends continuously from a volume within the metallic plate portion to a volume within the metallic via portion without a material junction therein”, as disclosed by Wang in the system of Wu, for the purpose of forming a via and metal line that have significantly less intrinsic contact resistance . (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 8 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/240,560 (reference application), which is published as Kubo et al. (US 2024/0179904). Although the claims at issue are not identical, they are not patentably distinct from each other because the parent application contains each of the instant application’s claimed limitations.
Claim limitation(s) of the instant application
Claim limitation(s) of the ‘560 co-pending application
8. A semiconductor structure, comprising:
A. an alternating stack of A1. insulating layers and A2. electrically conductive layers;
B. memory openings vertically extending through the alternating stack;
C. memory opening fill structures located in the memory openings and comprising a respective C1. vertical semiconductor channel and a respective C2. vertical stack of memory cells;
D. a pair of backside trench fill structures laterally contacting the alternating stack and laterally spaced apart from each other by the alternating stack;
E. a pair of dielectric barrier structures vertically extending through the alternating stack;
F. a vertical stack of dielectric material plates located at levels of a subset of the electrically conductive layers and F1. contacting each of the pair of dielectric barrier structures; and
G. an integrated line-and-via structure that is a unitary structure comprising a first electrically conductive layer of the electrically conductive layers and further comprising a metallic via portion that vertically extends through each of the dielectric material plates that overlie the first electrically conductive layer.
1. A semiconductor structure, comprising:
A. an alternating stack of A1. insulating layers and A2. electrically conductive layers;
B. memory openings vertically extending through the alternating stack;
C. memory opening fill structures located in the memory openings and comprising a respective C1. vertical stack of memory elements and a respective C2. vertical semiconductor channel;
F. a vertical stack of dielectric material plates located at levels of a subset of the electrically conductive layers;
E. a dielectric barrier structure vertically extending through the alternating stack and F1. [the dielectric barrier structure] laterally separating the dielectric material plates from the electrically conductive layers; and
~G. a first vertically-extending conductive via portion that is in electrical contact with a first electrically conductive layer of the electrically conductive layers, and that vertically extends through each of the dielectric material plates that overlie the first electrically conductive layer.
9. The semiconductor structure of Claim 8, wherein the integrated line-and-via structure comprises a homogeneous metallic material portion that extends continuously from a volume within the first electrically conductive layer to a volume within the metallic via portion without a material junction therein.
N/A
10. The semiconductor structure of Claim 8, wherein:
the metallic via portion is laterally surrounded by a tubular dielectric liner; and
the tubular dielectric liner is laterally surrounded by each of the dielectric material plates that overlie the first electrically conductive layer.
N/A
11. The semiconductor structure of Claim 10, wherein an annular bottom surface of the tubular dielectric liner contacts an annular horizontal surface segment of the first electrically conductive layer.
N/A
12. The semiconductor structure of Claim 8, wherein each of the pair of dielectric barrier structures is laterally spaced from the pair of backside trench fill structures, and is in direct contact with each insulating layer within the alternating stack.
N/A
13. The semiconductor structure of Claim 12, wherein:
interfaces between the alternating stack and the pair of dielectric barrier structures laterally extend along a first horizontal direction; and
the pair of dielectric barrier structures laterally extends along the first horizontal direction, and is laterally spaced apart from each other along a second horizontal direction that is perpendicular to the first horizontal direction.
N/A.
14. The semiconductor structure of Claim 8, wherein a subset of the memory opening fill structures is located within a rectangular area having a lateral extent along a first horizontal direction that is the same as a lateral extent of the pair of dielectric barrier structures along the first horizontal direction, and having a lateral extent along a second horizontal direction that is the same as a lateral distance between a proximal one of the pair of dielectric barrier structures and a proximal one of the pair of backside trench fill structures.
N/A.
Allowable Subject Matter
Claims 2, 3, 5, 6, 7 and 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 3 has been objected to, due to dependence upon claim 2. Claim 11 has been objected to, due to dependence upon claim 10. Claim 13 has been objected to, due to dependence upon claim 12.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
Prosecution Insights