DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 14, 2023, August 31, 2023, February 16, 2024, June 17, 2025, November 17, 2025 is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-11) in the reply filed on November 20, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 2018/0097009).
Claim 1, Zhang discloses (Fig. 17B annotated below, and Fig. 13B, 16A-16B, 18) a semiconductor structure, comprising: an alternating stack (32/46, alternating stack, Para [0143]) of insulating layers (32, insulating layers, Para [0141]) and electrically conductive layers (46, electrically conductive layers, Para [0141]); memory openings (opening where 55 is formed, hereinafter “opening”) vertically extending through the alternating stack (opening vertically extends through 32/46); memory opening fill structures (55, memory stack structure, Para [0118]) located in the memory openings (55 is located in opening) and comprising a respective vertical semiconductor channel (601/602, multiple semiconductor channel layers, Para [0120]) and a respective vertical stack of memory cells (50, memory film, Para [0120]); a vertical stack of dielectric material plates (Fig. 13B, 72, dielectric isolation structure, under broadest reasonable interpretation (BRI) is a stack of dielectric plates, Para [0140]) located at levels of a subset of the electrically conductive layers (72 is located at a subset of 46s); and an integrated line-and-via structure (1st/2nd/plate/via, hereinafter “structure”) that is a unitary structure (structure is unitary) comprising a first electrically conductive layer (1st which is a 46B) and a second electrically conductive layer (2nd which is a 46B) of the electrically conductive layers (46s), a metallic plate portion (plate is 46B, metallic fill material layer, Para [0134]) vertically connecting the first electrically conductive layer and the second electrically conductive layer (plate connects 1st and 2nd), and a metallic via portion (via which is formed of metallic fill material 46B) that vertically extends through each of the dielectric material plates that overlie the first electrically conductive layer (46B would extend through 72 that overlie with 1st , where 72 is not labeled in Fig. 17B)
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Claim 2, Zhang discloses (Fig. 17B annotated above, and Fig. 13B, 16A-16B, 18) the semiconductor structure of Claim 1, further comprising a pair (pair of backside shown in Fig. 16B) of backside trench fill structures (Fig. 16A, 44/76, backside blocking dielectric layer/backside contact via structure, Para [0146], hereinafter “backside”) laterally contacting the alternating stack (backside contacts 32/46 as shown in Fig. 16A) and laterally spaced apart from each other by the alternating stack (Fig. 16B shows multiple backside which are laterally spaced apart from each other). Claim 3, Zhang discloses (Fig. 17B annotated above, and Fig. 13B, 16A-16B, 18) the semiconductor structure of Claim 2, wherein each of the pair of backside trench fill structures (pair of backside shown in Fig. 16B) comprises a dielectric trench fill material portion (44, backside blocking dielectric layer, Para [0145]) that contacts a respective sidewall of the alternating stack (as can be seen in Figs. 16A and 16B, respective 44 would contact sidewall of respective 32/46).
Claim 6, Zhang discloses (Fig. 17B annotated above, and Fig. 13B, 16A-16B, 18) the semiconductor structure of Claim 1, wherein the metallic plate portion (plate) comprises sidewalls (left and right sidewalls of plate) that contact sidewalls of one of the insulating layers (left and right sidewalls of plate contact sidewalls of 32s). Claim 8, Zhang discloses (Fig. 17B annotated above, and Fig. 13B, 16A-16B, 18) the semiconductor structure of Claim 1, wherein the integrated line-and-via structure (structure) comprises a homogeneous metallic material portion that extends continuously through the first electrically conductive layer, the metallic plate portion, the second electrically conductive layer, and the metallic via portion without a material junction therein (1st, 2nd, plate, and via are all 46B material layer which can be tungsten continuously, Para [0134]).
Claim(s) 1-2 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 2018/0097009).
Claim 1, Zhang discloses (Fig. 17B annotated below, and Fig. 13B, 16A-16B, 18) a semiconductor structure, comprising: an alternating stack (32/46, alternating stack, Para [0143]) of insulating layers (32, insulating layers, Para [0141]) and electrically conductive layers (46, electrically conductive layers, Para [0141]); memory openings (opening where 55 is formed, hereinafter “opening”) vertically extending through the alternating stack (opening vertically extends through 32/46); memory opening fill structures (55, memory stack structure, Para [0118]) located in the memory openings (55 is located in opening) and comprising a respective vertical semiconductor channel (601/602, multiple semiconductor channel layers, Para [0120]) and a respective vertical stack of memory cells (50, memory film, Para [0120]); a vertical stack of dielectric material plates (Fig. 13B, 72, dielectric isolation structure, under broadest reasonable interpretation (BRI) is a stack of dielectric plates, Para [0140]) located at levels of a subset of the electrically conductive layers (72 is located at a subset of 46s); and an integrated line-and-via structure (1st/2nd/plate/via, hereinafter “structure”) that is a unitary structure (structure is unitary) comprising a first electrically conductive layer (1st which is a 46B) and a second electrically conductive layer (2nd which is a 46B) of the electrically conductive layers (46s), a metallic plate portion (plate is 46B, metallic fill material layer, Para [0134]) vertically connecting the first electrically conductive layer and the second electrically conductive layer (plate connects 1st and 2nd), and a metallic via portion (via which is formed of metallic fill material 46B) that vertically extends through each of the dielectric material plates that overlie the first electrically conductive layer (46B would extend through 72 that overlie with 1st , where 72 is not labeled in Fig. 17B)
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Claim 2 (Alternately), Zhang discloses (Fig. 17B annotated above, and Fig. 13B, 16A-16B, 18) the semiconductor structure of Claim 1, further comprising a pair (pair of backside2 shown in Fig. 16B) of backside trench fill structures (Fig. 16A, 74/76, spacer/backside contact via structure, Para [0140], [0146],) laterally contacting the alternating stack (backside2 contacts 32/46 through 74 shown in Fig. 16A) and laterally spaced apart from each other by the alternating stack (Fig. 16B shows multiple backside2 which are laterally spaced apart from each other). Claim 4, Zhang discloses (Fig. 17B annotated above, and Fig. 13B, 16A-16B, 18) the semiconductor structure of Claim 2 (Alternately), further comprising a pair (pair of 44 shown in Fig. 16B) of dielectric barrier structures (44, backside blocking dielectric layer, Para [0140]) vertically extending through the alternating stack (44 vertically extends through 32/46 as shown in Fig. 16A) and laterally spaced from the pair of backside trench fill structures (44s are shown to be laterally spaced from pair of backside2 as shown in Fig. 16B).
Allowable Subject Matter
Claims 5, 7, and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Zhang (US 2018/0097009), Maekura (US 2024/0179905), Wang (US 2021/0384124), Kai (US 2020/0235120), Furihata (US 2017/0179154), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 5, the vertical stack of dielectric material plates is in direct contact with each of the pair of dielectric barrier structures…
Regarding Claim 7, wherein a vertical interface between the metallic plate portion and the one of the insulating layers is laterally offset from a bottom periphery of the metallic via portion by a uniform lateral offset distance.
Regarding Claim 9 (from which claims 10-11 depend), wherein the metallic via portion is laterally surrounded by a tubular dielectric liner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Maekura (US 2024/0179905) discloses (Fig. 28A) a metal plate 148 contacting electrically conductive layers 461 and 462, but Maekura does not qualify as prior art.
Wang (US 2021/0384124) discloses (Fig. 4E) a contact via 416 inside a insulator region 450 contacting a electrically conductive layer 430 with a portion 420. Wang does not disclose a metal plate connecting two electrically conductive layers of a stack.
Kai (US 2020/0235120) discloses (Fig. 12C) a moat trench 179 filled with contacts 279. Kai does not disclose a metal plate connecting two electrically conductive layers of a stack.
Furihata (US 2017/0179154) discloses (Fig. 16A) discloses memory level via region 400 with via structures 488 through a dielectric fill material 430. Furihata does not disclose a metal plate connecting two electrically conductive layers of a stack.
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/G.G.R/Examiner, Art Unit 2812