Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 6 recited the limitation of “a first peripheral circuit chip comprising at least one of (1) a low low voltage device that comprises an input/output (I/O) circuit and/or a high voltage device that comprises at least one of a row decoder, a column decoder, a word line driver, and a bit line driver, and (2) a low voltage device comprising a page buffer or a logic device, and/or a controller” is therefore rendered indefinite. It is unclear how a low low voltage device comprises a high voltage device?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2023/0005543).
As for claims 1 and 6, Yang et al. disclose in Fig 13 and the related text a peripheral circuit assembly, comprising:
a first peripheral circuit chip (lower portion of 102) comprising at least one of (1) a low low voltage device 2322 that comprises an input/output (I/O) circuit and/or a high voltage device that comprises at least one of a row decoder, a column decoder, a word line driver, and a bit line driver, and (2) a low voltage device comprising a page buffer or a logic device, and/or a controller; and
a second peripheral circuit chip 104 located on a (lower) side of the first peripheral circuit chip opposite a memory array (upper portion of 102) along a first (vertical) direction and comprising another high voltage device 2308,
wherein one of the first peripheral circuit chip and the second peripheral circuit chip comprises a comprise at least one of the low low voltage device 2320 and wherein the first peripheral circuit chip or the second peripheral circuit chip further comprises the controller (one of transistor 2322, [0236]); and
the memory array chip (upper portion of 102) in bonding connection with at least one of the first peripheral circuit chip PW1 and the second peripheral circuit chip PW2 along the first direction (Fig. 23A).
As for claims 2 and 3, Yang et al. disclose the peripheral circuit assembly of claim 2, wherein the first peripheral circuit chip comprises the low low voltage device 2322, the controller (one of transistor 2322), and the low voltage device 2322; and the second peripheral circuit chip comprises the high voltage device 2308 and the low voltage device 2310.
As for claim 4, Yang et al. disclose the peripheral circuit assembly of claim 3, wherein the controller (one of 2322) is located on a side of the low low voltage device 2322 and the low voltage device 2320 along a second (horizontal) direction perpendicular to the first direction (Fig. 23).
As for claim 7, Yang et al. disclose the memory system of claim 6, wherein at least one of the first peripheral circuit chip or the second peripheral circuit chip further comprises the low voltage device 2310 [0233], and the memory array chip CW comprises a stack structure comprising a core region (right side region) and a connection region (left side region) that is located on at least a side of the core region (Fig. 23), and wherein the low voltage device 2310 is disposed corresponding to the core region (Fig. 23), and the high voltage device 2308 is disposed corresponding to the connection region (Fig. 3).
As for claim 8, Yang et al. disclose the memory system of claim 6, wherein the side of the first peripheral circuit chip along the first direction is a first side, wherein the first peripheral circuit chip is in bonding connection with a side of the memory array chip (Fig. 23), and the second peripheral circuit chip is in bonding connection with a side of the first peripheral circuit chip far away from the memory array chip (Fig. 23).
As for claim 9, Yang et al. disclose the memory system of claim 8, wherein the first peripheral circuit chip comprises:
a first substrate 1002;
the low low voltage device 2322 and the controller (one of 2322) each comprising a transistor (Fig. 23A [0236]) that is at least partially located in the first substrate (Fig. 23A);
a first trench isolation structure (formed both side of transistor 2322/2320) disposed in the first substrate and surrounding an active region of the transistor;
a first interconnection layer (insulating layer and via form in 102) covering a side of the first substrate and the transistor facing the memory array chip (Fig. 23A), wherein the transistor is connected with the memory array chip through the first interconnection layer (Fig. 23A); and
a first connection structure (via form in 102/104) connected with the second peripheral circuit chip at one end and connected with the memory array chip CW through the first substrate and the first interconnection layer at the other end (Fig. 23A).
As for claim 10, Yang et al. disclose the memory system of claim 9, wherein the first interconnection layer comprises: a first insulation layer; and a first interconnection structure located in the first insulation layer (Fig. 23A), wherein the first interconnection structure is connected with the transistor at one end, and connected with the first connection structure or the memory array chip CW at the other end (Fig. 23A).
As for claim 11, Yang et al. disclose the memory system of claim 8, wherein the second peripheral circuit chip 104 comprises: a second substrate 1004; the high voltage device 2308 comprising a transistor that is at least partially located in the second substrate (Fig. 23A);
a second trench isolation structure (form both side of transistor 2308/2310, Fig. 23A) disposed in the second substrate and surrounding an active region of the transistor (Fig. 23A); and
a second interconnection layer 2312 covering a side of the second substrate and the transistor facing the first peripheral circuit chip (Fig. 23A), wherein the transistor 2308 is (electrically/thermally) connected with the first peripheral circuit chip through the second interconnection layer (Fig. 23A).
As for claim 12, Yang et al. disclose the memory system of claim 8, wherein the memory array chip CW comprises:
a semiconductor layer 106 provided with a pad structure 2332 on a side away from the first peripheral circuit chip (Fig. 23A);
a third insulation layer disposed on a side of the semiconductor layer facing the first peripheral circuit chip (Fig. 23A), wherein a stack structure 206 is disposed in the third insulation layer (Fig. 23A);
a third interconnection layer 2324 disposed on a side of the third insulation layer facing the first peripheral circuit chip (Fig. 3), wherein the stack structure is (electrically/thermally) connected with the first peripheral circuit chip through the third interconnection layer (Fig. 23A); and
a second connection structure 2328 (electrically/thermally) connected with the pad structure at one end and (electrically/thermally) connected with the first peripheral circuit chip through the semiconductor layer, the third insulation layer and the third interconnection layer sequentially at the other end (Fig. 23A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Oh et al. (US 2021/0383874).
As for claim 5, Yang et al. disclose the peripheral circuit assembly of claim 1, wherein the first peripheral circuit chip comprises the low low voltage device 2322, the high voltage device, the low voltage device 2320, and the controller (one of 2322).
Yang et al. do not disclose the first peripheral circuit chip comprises the high voltage device.
Oh et al. teach in Fig. 5 and the related text the first peripheral circuit chip LW2 comprises the high voltage device [0085].
Yang et al. and Oh et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang et a. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Yang et al. to include the first peripheral circuit chip comprises the high voltage device as taught by Oh et al., in order to perform an operation of the device (Oh et al. [0003]).
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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