Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-12) in the reply filed on 03/25/2026 is acknowledged.
Claims 13-19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/25/2026.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a third peripheral circuit chip must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2022/0122932).
As for claims 1 and 6, Oh et al. disclose in Figs. 1-3 and the related text a peripheral circuit assembly, comprising:
a first peripheral circuit chip PW1; and
a second peripheral circuit chip PW2 located on a side of the first peripheral circuit chip along a first (vertical) direction, wherein one of the first peripheral circuit chip PW1 and the second peripheral circuit chip PW2 comprises a low low voltage device 132/TR1 ([0056] and [0063]), and the other one of the first peripheral circuit chip PW1 and the second peripheral circuit chip PW2 comprises a high voltage device 131/TR2 ([0059]-[0063]), and the first peripheral circuit chip PW1 or the second peripheral circuit chip PW2 further comprises a controller [0032]; and
a memory array chip CW in bonding connection with at least one of the first peripheral circuit chip PW1 and the second peripheral circuit chip PW2 along the first direction (Fig. 3, [0037]).
As for claim 2, Oh et al. disclose the peripheral circuit assembly of claim 1, wherein at least one of the first peripheral circuit chip PW1 or the second peripheral circuit chip PW2 further comprises a low voltage device TR1 (Fig. 3).
As for claim 7, Oh et al. disclose the memory system of claim 6, wherein at least one of the first peripheral circuit chip PW1 or the second peripheral circuit chip PW2 further comprises a low voltage device TR1 [0063], and the memory array chip CW comprises a stack structure comprising a core region CR and a connection region SR that is located on at least a side of the core region (Fig. 3), wherein the low voltage device TR1 is disposed corresponding to the core region (Fig. 3), and the high voltage device TR2 is disposed corresponding to the connection region SR (Fig. 3).
As for claim 8, Oh et al. disclose the memory system of claim 6, wherein the first peripheral circuit chip PW1 is in bonding connection with a side of the memory array chip CW, and the second peripheral circuit chip PW2 is in bonding connection with a side of the first peripheral circuit chip far away from the memory array chip (Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. in view of Oh et al. (US 2021/0383874).
As for claim 3, Oh et al. disclose the peripheral circuit assembly of claim 2, wherein the first peripheral circuit chip PW1 comprises the low low voltage device (left TR1, claim does not clearly device the different between low low voltage device and low voltage device therefore Oh et al. still disclose TR1 as the low voltage device), the controller [0032] and the low voltage device (middle/right TR1), and the second peripheral circuit chip comprises the high voltage device TR2.
Oh et al. do not disclose the second peripheral circuit chip comprises the low voltage device.
Oh et al. teach in Fig. 5 and the related text a second peripheral circuit chip LW2 comprises a low and high voltage devices [0085].
Oh et al. and Oh et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oh et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Oh et al. to include the limitations as taught by Oh et al., in order to perform an operation of the device (Oh et al. [0003]).
As for claim 4, Oh et al. disclose the peripheral circuit assembly of claim 3, wherein the controller (right TR1 or [0032]) is located on a side of the low low voltage device (left TR1) and the low voltage device (middle TR1) along a second (horizontal) direction perpendicular to the first direction (Fig. 3).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. in view of Fastow et al. (US 2019/0043836).
As for claim 5, Oh et al. disclose the peripheral circuit assembly of claim 1, except wherein the peripheral circuit assembly further comprises a third peripheral circuit chip that comprises a low voltage device.
Fastow et al. teach in Fig. 1-3B and the related text a circuit assembly further comprises a third peripheral circuit chip 282C/282D that comprises a low voltage device ([0030] AND [0062]).
Oh et al. and Fastow et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oh et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Oh et al. to include the limitations as taught by Fastow et al., in order to reduce cost (Fastow et al.: [0030]).
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. in view of Liu (US 2020/0328176).
As for claim 9, Oh et al. disclose the memory system of claim 8, wherein the first peripheral circuit chip comprises:
a first substrate 12;
the low low voltage device (left TR1) and the controller (right TR1) each comprising a transistor TR1 [0063] that is at least partially located in the first substrate (Fig. 3);
a first interconnection layer (lower layer of PW1) covering a side of the first substrate and the transistor facing the memory array chip (Fig. 3), wherein the transistor TR1 is connected with the memory array chip CW through the first interconnection layer (Fig. 3); and
a first connection structure (upper layer of PW2) connected with the second peripheral circuit chip at one end (Fig. 3), and connected with the memory array chip CW through the first substrate and the first interconnection layer at the other end (Fig. 3).
Oh et al. do not disclose a first trench isolation structure disposed in the first substrate and surrounding an active region of the transistor; and the first connection structure connected with the memory array chip CW through the first substrate and the first interconnection layer at the other end.
Liu teaches in Fig. 7A and the related text a first trench isolation structure disposed in the first substrate and surrounding an active region of the transistor 736 [0068]; and a first connection structure 714 connected with the memory array chip 702 through the first substrate 766 and the first interconnection layer 738 at the other end.
Oh et al. and Liu are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oh et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Oh et al. to include the limitations as taught by Liu, in order to isolated active regions of the device and improve interconnections.
As for claim 10, Oh et al. disclose the memory system of claim 9, wherein the first interconnection layer comprises: a first insulation layer (lower layer of PW1); and a first interconnection structure (lower layer PW1) located in the first insulation layer (Fig. 3), wherein the first interconnection structure is connected with the transistor at one end, and connected with the first connection structure or the memory array chip CW at the other end (Fig. 3).
As for claim 11, Oh et al. disclose the memory system of claim 8, wherein the second peripheral circuit chip PW2 comprises: a second substrate 14; the high voltage device 132 comprising a transistor TR2 that is at least partially located in the second substrate (Fig. 3);
a second trench isolation structure disposed in the second substrate and surrounding an active region of the transistor; and
a second interconnection layer (upper layer of PW2) covering a side of the second substrate and the transistor facing the first peripheral circuit chip (Fig. 3), wherein the transistor TR2 is connected with the first peripheral circuit chip PW1 through the second interconnection layer (Fig. 3).
Oh et al. do not disclose a second trench isolation structure disposed in the second substrate and surrounding an active region of the transistor.
Liu teaches in Fig. 7A and the related text a second trench isolation structure disposed in a second substrate 766 and surrounding an active region of the transistor 736 [0068].
Oh et al. and Liu are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oh et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Oh et al. to include the limitations as taught by Liu, in order to isolated active regions of the device.
As for claim 12, Oh et al. disclose the memory system of claim 8, wherein the memory array chip CW comprises:
a semiconductor layer 10 provided with a pad structure PAD1 on a side far away from the first peripheral circuit chip (Fig. 3);
a third insulation layer (upper layer of CW) disposed on a side of the semiconductor layer facing the first peripheral circuit chip (Fig. 3), wherein a stack structure 20/22 is disposed in the third insulation layer (Fig. 3); a third interconnection layer CNT12/M11/CNT13 disposed on a side of the third insulation layer facing the first peripheral circuit chip (Fig. 3), wherein the stack structure is connected with the first peripheral circuit chip through the third interconnection layer (Fig. 3); and
Oh et al. do not disclose a second connection structure connected with the pad structure at one end, and connected with the first peripheral circuit chip through the semiconductor layer, the third insulation layer and the third interconnection layer sequentially at the other end.
Liu teaches in Fig. 7A and the related text a second connection structure 762 connected with the pad structure 746 at one end, and connected with the first peripheral circuit chip 704/706 through the semiconductor layer758, the third insulation layer (insulating layer of 748, [0079]) and the third interconnection layer 748 sequentially at the other end (Fig. 7A).
Oh et al. and Liu are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oh et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Oh et al. to include the limitations as taught by Liu, in order to improve external connections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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