Prosecution Insights
Last updated: July 17, 2026
Application No. 18/352,822

SYSTEM AND METHOD FOR BACK SIDE SIGNAL ROUTING

Non-Final OA §DP
Filed
Jul 14, 2023
Priority
Apr 14, 2021 — divisional of 11/423,204 +1 more
Examiner
MEMULA, SURESH
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
812 granted / 926 resolved
+19.7% vs TC avg
Minimal -0% lift
Without
With
+-0.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
12 currently pending
Career history
942
Total Applications
across all art units

Statute-Specific Performance

§101
9.9%
-30.1% vs TC avg
§103
26.9%
-13.1% vs TC avg
§102
51.0%
+11.0% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 926 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 and 16 of U.S. Patent No. 11,748,546 (Conflicting patent ‘546) and unpatentable over claim 12 of U.S. Patent No. 11,423,204 (“Conflicting patent ‘204”). Although the claims at issue are not identical, they are not patentably distinct from each other because each of the conflicting patent’s claims (i.e., ‘546’s claims 15 and 16, and ‘204’s claim 12) anticipate instant claims 18-20. Allowable Subject Matter Claims 1-10, 11-17, and 18-20 would be allowed if the nonstatutory double patenting rejections above are overcome. Claims 1-10, 11-17, and 18-20 would be allowable because the prior art of record does not teach or suggest a system having all the combinations of elements as required by and recited in claims 1, 11, or 18, particularly including, among other things, the following: In claim 1, a cell on the substrate having a first pin on the first side or the second side, and a second pin on the second side; a first signal routing to route a first ground and power signal track on the second side; a second signal routing to route a second ground and power signal track on the second side; and a third signal routing connected to the second pin to route a first clock trunk signal on the second side, wherein the third signal routing is between the first signal routing and the second signal routing. In claim 11, a cell on the substrate having a first pin on the second side and a second pin on the second side; a first signal routing to route a first ground and power signal track on the second side; a second signal routing to route a second ground and power signal track on the second side; and a third signal routing to route a first feedthrough wire on the second side, wherein the third signal routing is between the first signal routing and the second signal routing. In claim 18, a first cell on the substrate having a first pin on the first side and a second pin on the second side; a second cell on the substrate having a third pin on the first side and a fourth pin on the second side; and a first signal routing connected to the second pin on the second side and connected to the fourth pin on the second side to facilitate connection of a second signal routing on the first side to a third signal routing on the first side. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SURESH MEMULA/Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Jul 14, 2023
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
87%
With Interview (-0.3%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 926 resolved cases by this examiner. Grant probability derived from career allowance rate.

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