FR DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 6/23/2026. Claims 11 and 20 have been amended. No new claims have been added or canceled. Claims 1-10 were withdrawn. Currently, claims 11-20 are pending.
Due to an antecedent basis error in the previous Office Action, the 35 USC 112(b) rejection of claim 12 is withdrawn.
Response to Arguments
Applicant argues neither Li nor Weber teach or suggest the claim amendments added into claim 1, e.g., wherein the gate structure penetrates through the stop layer to contact a surface of the substrate. Examiner agrees. However, the new limitation necessitated further search and consideration, and a new prior art Chetlur et al. (US 20180342500) has been found. Chetler anticipates claim 1 as described below.
Therefore, the rejection of independent claims 1 and 20 are rejected in view of Chetlur et al. (US 20180342500). As a result, the rejection of claims 11-20 is maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chetlur et al. (US 20180342500).
Regarding claim 11, Chetlur teaches, in Fig. 2, a semiconductor device ([0077]), comprising:
a base (132/134, [0077]);
a stop layer (102, [0067], [0086], under broadest reasonable interpretation, 102 is a stop layer because it is a drain layer that has different doping from 134 and stops 134 from contacting 104, and it is configured to act as a stop layer if desired as shown in Fig. 1) located on a (top) side of the base (132/134);
a semiconductor layer (104/106, [0086]) located on a (top) side of the stop layer (102) facing away from the base (132/134); and
a gate structure (108/110, [0069]) extending in the semiconductor layer (104/106) and penetrating through the stop layer (102),
wherein the gate structure (108/110) penetrates through the stop layer (102) to contact a (side) surface of the base (132/134).
Regarding claim 15, Chetlur further teaches, in Fig. 2, that the gate structure (108/110) comprises a gate oxidization layer (110, [0069]) extending in the semiconductor layer (104/106) along a first (vertical) direction and penetrating through the stop layer (102), and a gate layer (108) located on a side of the gate oxidization layer (left surface of the right portion of 110) facing away from the semiconductor layer (104/106).
Regarding claim 16, Chetlur further teaches that the stop layer (102) comprises a drain ([0082]).
Regarding claim 17, Chetlur further teaches, in Fig. 2, that the semiconductor layer (104/106) comprises a source (106, [0086]) that is located on a (top) side of the semiconductor layer (104/106) facing away from the base (132/134) (see Fig. 2).
Regarding claim 19, Chetler teaches the limitations of claim 11. Chetler further teaches that the stop layer (102) comprises at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, or silicon germanium ([0003], “silicon bulk layer”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chetlur et al. (US 20180342500) in view of Imam et al. (US 20240096987).
Regarding claim 12, Chetler teaches the limitations of claim 1. Chetler does not explicitly teach that the gate structure comprises a first substructure extending in the semiconductor layer along a first direction, a second substructure extending in the stop layer along the first direction, and a third substructure and a fourth substructure that extend in the stop layer along a second direction, the first direction intersecting the second direction; and an end of each of the first substructure is connected with an end of the third substructure, an end of the third substructure facing away from the first substructure is connected with an end of the second substructure, and an end of the second substructure facing away from the third substructure is connected with an end of the fourth substructure.
In a similar field of endeavor, Imam teaches, in Fig. 1, that the gate structure (200, [0018]) comprises a first substructure (230, [0021]) extending in the semiconductor layer (106, [0023]) along a first direction (z-direction), a second substructure (212, [0023]) extending in the stop layer (101/102/104, [0018]) along the first direction (z-direction), and a third substructure (222, [0022]) and a fourth substructure (214, [0022]) that extend in the stop layer (101/102/104) along a second direction (x-direction), the first direction (z-direction) intersecting the second direction (x-direction); and
an end (bottom surface) of each of the first substructure (230) is connected with an end (top left) of the third substructure (222), an end (bottom surface) of the third substructure (222) facing away from the first substructure (230) is connected with an end (top left) of the second substructure (212), and an end (bottom part) of the second substructure (212) facing away from the third substructure (222) is connected with an end (bottom surface) of the fourth substructure (214), in order to modify the electric field profile around, and especially at the bottom of, the trench gate structure ([0007]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the gate structure of Chetler with the gate structure of Imam, in order to modify the electric field profile around, and especially at the bottom of, the trench gate structure ([0007]).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chetlur et al. (US 20180342500) in view of Wang et al. (CN 102169896 A, citations made hereinafter to the English machine translation attached to the Office Action mailed on 3/27/2026), cited by Applicant in the Information Disclosure Statement filed on 1/14/2025.
Regarding claim 13, Chetler teaches the limitations of claim 11. Chetler does not explicitly teach a spacing portion, wherein the spacing portion extends in the semiconductor layer and the stop layer along a first direction, the gate structure covers a part of sidewall and a part of bottom of the spacing portion, and the bottom of the spacing portion is an end of the spacing portion close to the base.
In a similar field of endeavor, Wang teaches, in Fig. 9, a spacing portion (310, [0040]), wherein the spacing portion extends in the semiconductor layer (303/304, [0036]) and the stop layer (301/302, [0036]) along a first direction (vertical direction) (see Fig. 9), the gate structure (307/308, [0037]) covers a part of sidewall and a part of bottom (bottom portion in layers 301/302) of the spacing portion (310) (see Fig. 9), and the bottom (bottom portion in layers 301/302) of the spacing portion is an end of the spacing portion close to the base (312, [0041]), in order to reduce the parasitic capacitance between the gate and drain ([0007)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Chetler with the spacing portion of Wang, in order to reduce the parasitic capacitance between the gate and drain ([0007)].
Regarding claim 14, Chetler in view of Wang teaches the limitations of claim 13. Wang further teaches, in Fig. 9, that the spacing portion (310) comprises a first (top) spacing sub-portion penetrating through the semiconductor layer (303/304), and a second (bottom) spacing sub-portion extending in the stop layer (301/302) along the first direction (vertical direction); and
a dimension (width) of an (top) end of the second (bottom) spacing sub-portion close to the first (top) spacing sub-portion in a second direction (horizontal direction) is greater than a dimension (width) of an (bottom) end of the (top) first spacing sub-portion close to the second spacing sub-portion in the second direction (horizontal), and the second (horizontal) direction intersects the first (vertical) direction.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chetlur et al. (US 20180342500) in view of Weber (US 20230238427).
Regarding claim 18, Chetler teaches the limitations of claim 11. Chetler does not teach an isolation structure, wherein the isolation structure penetrates through the semiconductor layer and the stop layer.
In a similar field of endeavor, Weber teaches, an isolation structure (21, [0040]), wherein the isolation structure penetrates through the semiconductor layer (12/13, [0060]) and the stop layer (11/32, [0060]) (see Fig. 3), in order to “reduce bipolar degradation” ([0040], [0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Chetler with the isolation structure of Weber, in order to reduce bipolar degradation ([0040], [0045]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chetlur et al. (US 20180342500) in view of Kim et al. (US 20190057756).
Regarding claim 20, Chetlur teaches, in Fig. 2, a semiconductor device ([0077]), comprising:
a base (132/134, [0077]);
a stop layer (102, [0067], [0086], under broadest reasonable interpretation, 102 is a stop layer because it is a drain layer that has different doping from 134 and stops 134 from contacting 104, and it is configured to act as a stop layer if desired as shown in Fig. 1) located on a (top) side of the base (132/134);
a semiconductor layer (104/106, [0086]) located on a (top) side of the stop layer (102) facing away from the base (132/134); and
a gate structure (108/110, [0069]) extending in the semiconductor layer (104/106) and penetrating through the stop layer (102),
wherein the gate structure (108/110) penetrates through the stop layer (102) to contact a (side) surface of the base (132/134).
Chetlur does not explicitly teach a periphery device bonded to the memory array; and a controller connected with the memory.
In a similar field of endeavor, Kim teaches, in Fig. 1, a periphery device (104) bonded to the memory array (102) ([0036]); and a controller ([0049]) connected with the memory, in order to have a 3D memory architecture that includes a memory array and “peripheral devices for controlling signals to and from the memory array” ([0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the memory array of Chetler with connecting to the periphery device and controller of Kim, in order to have a 3D memory architecture that includes a memory array and peripheral devices for controlling signals to and from the memory array ([0004]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is (703)756-4644. The examiner can normally be reached Monday - Friday 11:30-8:30 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
