DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II (claims 11-20) in the reply filed on February 11, 2026, is acknowledged.
Claims 1-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 12 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 12 recites the limitation “each of the first substructure” in line 6 of the claim. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination with regard to the prior art, the limitation “an end of each of the first substructure” will be treated as “an end of the first substructure”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11, 15, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. (US 20230387008).
Regarding claim 11, Li teaches, in Fig. 13, a semiconductor device ([0022]), comprising:
a base (1, [0044]);
a stop layer (141, [0066]) located on a (top) side of the base (1) (see Fig. 13);
a semiconductor layer (142, [0044], [0067]) located on a (top) side of the stop layer (141) facing away from the base (1) (see Fig. 13); and
a gate structure (132/133, [0069]) extending in the semiconductor layer (142) and penetrating through the stop layer (141) (see Fig. 13).
Regarding claim 15, Li further teaches, in Fig. 13, that the gate structure (132/133) comprises a gate oxidization layer (132, [0069]) extending in the semiconductor layer (142) along a first (vertical) direction and penetrating through the stop layer (141), and a gate layer (133, [0069]) located on a side of the gate oxidization layer (132) facing away from the semiconductor layer (142) (see Fig. 9, [0054], how because d2 is less than d1, the part of the gate layer at the top part of 141 is located on the left side of the right gate oxidization layer 132 facing away from layer 142).
Regarding claim 19, Li further teaches that the stop layer (141) comprises at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, or silicon germanium ([0044], “silicon substrate”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Weber (US 20230238427) in view of Li et al. (US 20230387008).
Regarding claim 11, Weber teaches, in Fig. 3, a semiconductor device ([0011]), comprising:
a stop layer (11/32/31, [0060]);
a semiconductor layer (12/13, [0060]) located on a (top) side of the stop layer (11/32/31); and
a gate structure (14/15, [0061]) extending in the semiconductor layer (12/13) and penetrating through the stop layer (11/32/31) (see Fig. 3).
Weber does not explicitly teach a base underneath the stop layer.
In a similar field of endeavor, Li teaches, in Fig. 13, a base (1, [0044]) underneath the stop layer (141, [0066]), because ion implantation of the substrate to form the stop layer enables the gate trench to be widened after it is initially formed, which increases the cross-sectional area of the bottom of the gate trench and reduces the resistance of the gate ([0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device structure of Weber with the base of Li, because ion implantation of the substrate to form the stop layer enables the gate trench to be widened after it is initially formed, which increases the cross-sectional area of the bottom of the gate trench and reduces the resistance of the gate ([0044]).
Regarding claim 16, Weber in view of Li teaches the limitations of claim 11. Weber further teaches, in Fig. 3, that the stop layer (11/32/31) comprises a drain (31) ([0060]).
Regarding claim 17, Weber in view of Li teaches the limitations of claim 11. Weber further teaches, in Fig. 3, that the semiconductor layer (12/13) comprises a source (13) that is located on a side of the semiconductor layer facing away from the base ([0060]).
Regarding claim 18, Weber in view of Li teaches the limitations of claim 11. Weber further teaches, in Fig. 3, an isolation structure (21, [0040]), wherein the isolation structure penetrates through the semiconductor layer (12/13) and the stop layer (11/32/31) (see Fig. 3).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20230387008) in view of Imam et al. (US 20240096987).
Regarding claim 12, Li teaches the limitations of claim 1. Li does not explicitly teach that the gate structure comprises a first substructure extending in the semiconductor layer along a first direction, a second substructure extending in the stop layer along the first direction, and a third substructure and a fourth substructure that extend in the stop layer along a second direction, the first direction intersecting the second direction; and an end of each of the first substructure is connected with an end of the third substructure, an end of the third substructure facing away from the first substructure is connected with an end of the second substructure, and an end of the second substructure facing away from the third substructure is connected with an end of the fourth substructure.
In a similar field of endeavor, Imam teaches, in Fig. 1, that the gate structure (200, [0018]) comprises a first substructure (230, [0021]) extending in the semiconductor layer (106, [0023]) along a first direction (z-direction), a second substructure (212, [0023]) extending in the stop layer (101/102/104, [0018]) along the first direction (z-direction), and a third substructure (222, [0022]) and a fourth substructure (214, [0022]) that extend in the stop layer (101/102/104) along a second direction (x-direction), the first direction (z-direction) intersecting the second direction (x-direction); and
an end (bottom surface) of each of the first substructure (230) is connected with an end (top left) of the third substructure (222), an end (bottom surface) of the third substructure (222) facing away from the first substructure (230) is connected with an end (top left) of the second substructure (212), and an end (bottom part) of the second substructure (212) facing away from the third substructure (222) is connected with an end (bottom surface) of the fourth substructure (214), in order to modify the electric field profile around, and especially at the bottom of, the trench gate structure ([0007]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the gate structure of Li with the gate structure of Imam, in order to modify the electric field profile around, and especially at the bottom of, the trench gate structure ([0007]).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Weber (US 20230238427) in view of Li et al. (US 20230387008), and further in view of Wang et al. (CN 102169896 A, citations made hereinafter to the attached English machine translation), cited by Applicant in the Information Disclosure Statement filed on 1/14/2025.
Regarding claim 13, Weber in view of Li teaches the limitations of claim 11. Weber in view of Li does not explicitly teach a spacing portion, wherein the spacing portion extends in the semiconductor layer and the stop layer along a first direction, the gate structure covers a part of sidewall and a part of bottom of the spacing portion, and the bottom of the spacing portion is an end of the spacing portion close to the base.
In a similar field of endeavor, Wang teaches, in Fig. 9, a spacing portion (310, [0040]), wherein the spacing portion extends in the semiconductor layer (303/304, [0036]) and the stop layer (301/302, [0036]) along a first direction (vertical direction) (see Fig. 9), the gate structure (307/308, [0037]) covers a part of sidewall and a part of bottom (bottom portion in layers 301/302) of the spacing portion (310) (see Fig. 9), and the bottom (bottom portion in layers 301/302) of the spacing portion is an end of the spacing portion close to the base (312, [0041]), in order to reduce the parasitic capacitance between the gate and drain ([0007)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Weber in view of Li with the spacing portion of Wang, in order to reduce the parasitic capacitance between the gate and drain ([0007)].
Regarding claim 14, Weber in view of Li and Wang teaches the limitations of claim 13. Wang further teaches, in Fig. 9, that the spacing portion (310) comprises a first (top) spacing sub-portion penetrating through the semiconductor layer (303/304), and a second (bottom) spacing sub-portion extending in the stop layer (301/302) along the first direction (vertical direction); and
a dimension (width) of an (top) end of the second (bottom) spacing sub-portion close to the first (top) spacing sub-portion in a second direction (horizontal direction) is greater than a dimension (width) of an (bottom) end of the (top) first spacing sub-portion close to the second spacing sub-portion in the second direction (horizontal), and the second (horizontal) direction intersects the first (vertical) direction.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20230387008) in view of Kim et al. (US 20190057756).
Regarding claim 20, Li teaches, in Fig. 13, a memory system, comprising:
a memory including a memory array comprising a semiconductor device ([0022], [0032]), wherein the semiconductor device comprises:
a base (1, [0044]);
a stop layer (141, [0066]) located on a (top) side of the base (1) (see Fig. 13);
a semiconductor layer (142, [0044], [0067]) located on a (top) side of the stop layer (141) facing away from the base (1) (see Fig. 13); and
a gate structure (132/133, [0069]) extending in the semiconductor layer (142) and penetrating through the stop layer (141) (see Fig. 13).
Li does not explicitly teach a periphery device bonded to the memory array; and a controller connected with the memory.
In a similar field of endeavor, Kim teaches, in Fig. 1, a periphery device (104) bonded to the memory array (102) ([0036]); and a controller ([0049]) connected with the memory, in order to have a 3D memory architecture that includes a memory array and “peripheral devices for controlling signals to and from the memory array” ([0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the memory array of Li with connecting to the periphery device and controller of Kim, in order to have a 3D memory architecture that includes a memory array and peripheral devices for controlling signals to and from the memory array ([0004]).
Conclusion
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893