DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. Applicant’s amendment to the claims, filed on July 21st, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
3. Applicant’s arguments/remarks, see pgs. 7-9, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant’s arguments/remarks, pgs. 7-9, regarding the newly amended limitations to at least the independent claims:
The Examiner notes that a new combination of prior art is presented in light of the amendments such that arguments directed solely to the previously presented combination of prior art are now moot.
Note by the Examiner
4. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 11, 13, and 17-20 are rejected under 35 U.S.C. 103 as obvious over Sung (US 2025/0287568 A1), hereinafter as S1, in view of Mine et al. (US 2019/0237470 A1), hereinafter as M1
6. Regarding Claim 11, S1 discloses a semiconductor device (see in particular Figs. 1A-2K and [0038] “semiconductor device”), comprising:
a plurality of semiconductor pillars (elements 120, see [0039] “oxide semiconductor pillars 120”) arranged in an array (see Fig. 1) along a first direction (element D1) and a second direction (element D2), first ends (bottom end) of the plurality of semiconductor pillars arranged along the first direction being connected with each other (connected to each other through element 111, see Fig. 1D and [0048]);
a first gate insulation layer (element 125, see [0056] “gate dielectric layer 125”) located on first sidewalls (right sidewalls) of the semiconductor pillars and extending along the second direction (see Fig. 1 the gate insulation layer extends along the oxide semiconductor pillars in the second D2 direction); and
first gates (first one of the elements 124 see [0056] “The tapered vertical word line 124 may be referred to as a tapered vertical gate”) located on a surface (right surface) of the first gate insulation layer and extending along the second direction (see Fig. 1B),
wherein surfaces of a plurality of the first gates close to the first ends are substantially flush (see Figs. 1A-B),
wherein the first direction, the second direction and a third direction (element D3) intersect each other (see Fig. 1A),
wherein the third direction is an extending direction of each of the semiconductor pillars (see Fig. 1A), and
wherein each of the first gates has a respective thickness in the first direction that is along the third direction (see Fig. 1A, 1D and [0043] The elements 124 are part of the array that are all formed above element 111 to element 126 which have a D3 third direction thickness; also see Figs. 2E-F and [0079] each of the elements 124 are formed through the exact same process).
S1 does not disclose wherein each of the first gates has a respective thickness in the first direction that is consistent along the third direction
M1 discloses wherein each of the first gates has a respective thickness in the first direction that is consistent along the third direction (see Figs. 4H1-2 and [0091] “A gate electrode material is deposited over substrate 302. For example, approximately 5 nm to about 30 nm of titanium nitride, or other similar conductive material may be deposited … Other conductive materials and/or thicknesses may be used for gate electrodes 408” Gate electrode element 408 has a lateral thickness consistent along the vertical direction).
The rectangular shaped gates with a consistent thickness as taught by M1 is incorporated as the shape of the gates of S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of M1 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gate shape and lateral thickness in the vertical direction for another in a similar memory device for which the gate thickness is disclosed to be adjustable to obtain predictable results (see M1 Figs. 4H1-2 and [0091]).
7. Regarding Claim 13, S1, M1 disclose the semiconductor device of claim 11, wherein cross-section shapes of the first gates on a plane perpendicular to the second direction are rectangular (see S1 Fig. 1B).
8. Regarding Claim 17, S1, M1 disclose the semiconductor device of claim 11, wherein the first gates comprise a gate blocking layer (see S1 [0055] “The tapered vertical word line 124 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof” Selected as titanium nitride for the gate blocking layer) and a gate metal layer (see S1 [0055] selected as tungsten for the gate metal layer), the gate blocking layer being located between the surface of the first gate insulation layer and the gate metal layer (see S1 Figs. 1A-B and [0055]).
9. Regarding Claim 18, S1, M1 disclose the semiconductor device of claim 17, wherein a material of the gate blocking layer includes titanium nitride (see S1 [0055]), and a material of the gate metal layer includes tungsten (see S1 [0055]).
10. Regarding Claim 19, S1, M1 disclose the semiconductor device of claim 14, wherein sizes of the first gates in the third direction are the same as a size of the conductive layer in the third direction (see S1 Fig. 1A, 1D and [0043] The elements 124 are part of the array that are all formed above element 111 to element 126 which have a consistent D3 third direction thickness; also see S1 Figs. 2E-F and [0079] each of the elements 124 are formed through the exact same process).
11. Regarding Claim 20, S1 discloses a memory system (see [0039] “memory elements 130”), comprising:
a semiconductor device (see in particular Figs. 1A-2K and [0038] “semiconductor device”), comprising:
a plurality of semiconductor pillars (elements 120, see [0039] “oxide semiconductor pillars 120”) arranged in an array (see Fig. 1) along a first direction (element D1) and a second direction (element D2), first ends (bottom end) of the plurality of semiconductor pillars arranged along the first direction being connected with each other (connected to each other through element 111, see Fig. 1D and [0048]);
a first gate insulation layer (element 125, see [0056] “gate dielectric layer 125”) located on first sidewalls (right sidewalls) of the semiconductor pillars and extending along the second direction (see Fig. 1 the gate insulation layer extends along the oxide semiconductor pillars in the second D2 direction); and
first gates (first one of the elements 124 see [0056] “The tapered vertical word line 124 may be referred to as a tapered vertical gate”) located on a surface (right surface) of the first gate insulation layer and extending along the second direction (see Fig. 1B),
wherein surfaces of a plurality of the first gates close to the first ends are substantially flush (see Figs. 1A-B),
wherein the first direction, the second direction and a third direction (element D3) intersect each other (see Fig. 1A),
wherein the third direction is an extending direction of each of the semiconductor pillars (see Fig. 1A); and
wherein each of the first gates has a respective thickness in the first direction that is along the third direction (see Fig. 1A, 1D and [0043] The elements 124 are part of the array that are all formed above element 111 to element 126 which have a D3 third direction thickness; also see Figs. 2E-F and [0079] each of the elements 124 are formed through the exact same process); and
a memory controller (elements TR, see [0043] “vertical channel transistor TR”; see Figs. 1A-D element TR having a channel layer of element 121 electrically connected to the memory elements 130 such that turning the transistor on and off controls the memory elements) coupled to the semiconductor device and configured to control the semiconductor device (see Figs. 1A-D and [0040] “semiconductor device 100 may include a Dynamic Random Access Memory (DRAM)”).
S1 does not disclose wherein each of the first gates has a respective thickness in the first direction that is consistent along the third direction
M1 discloses wherein each of the first gates has a respective thickness in the first direction that is consistent along the third direction (see Figs. 4H1-2 and [0091] “A gate electrode material is deposited over substrate 302. For example, approximately 5 nm to about 30 nm of titanium nitride, or other similar conductive material may be deposited … Other conductive materials and/or thicknesses may be used for gate electrodes 408” Gate electrode element 408 has a lateral thickness consistent along the vertical direction).
The rectangular shaped gates with a consistent thickness as taught by M1 is incorporated as the shape of the gates of S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of M1 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gate shape and lateral thickness in the vertical direction for another in a similar memory device for which the gate thickness is disclosed to be adjustable to obtain predictable results (see M1 Figs. 4H1-2 and [0091]).
12. Claims 11 and 14-16 are rejected under 35 U.S.C. 103 as obvious over Sung (US 2025/0287568 A1), hereinafter as S1, in view of Mine et al. (US 2019/0237470 A1), hereinafter as M1
13. Regarding Claim 11, S1 discloses a semiconductor device (see in particular Figs. 1A-2K and [0038] “semiconductor device” selected as the embodiment of Figs. 15A-D for which differences are primarily discussed in [0191-0225] while similarities and same element descriptions may not be repeated), comprising:
a plurality of semiconductor pillars (elements 120, see [0197] “oxide semiconductor pillars 120”) arranged in an array (see Fig. 15A-D) along a first direction (element D1) and a second direction (element D2), first ends (bottom end) of the plurality of semiconductor pillars arranged along the first direction being connected with each other (connected to each other through element 111, see Fig. 15C and [0048]);
a first gate insulation layer (element 125, see [0197] “gate dielectric layer 125”) located on first sidewalls (right sidewalls) of the semiconductor pillars and extending along the second direction (see Fig. 15C the gate insulation layer extends along the oxide semiconductor pillars in the second D2 direction); and
first gates (first one of the elements 124S see [0197] “main gate 124S”) located on a surface (right surface) of the first gate insulation layer and extending along the second direction (see Fig. 15A,C),
wherein surfaces of a plurality of the first gates close to the first ends are substantially flush (see Figs. 15A,C),
wherein the first direction, the second direction and a third direction (element D3) intersect each other (see Figs. 15A,C),
wherein the third direction is an extending direction of each of the semiconductor pillars (see Figs. 15A,C), and
wherein each of the first gates has a respective thickness in the first direction that is along the third direction (see Fig. 1A, 1D and [0043] The elements 124 are part of the array that are all formed above element 111 to element 126 which have a D3 third direction thickness; also see Figs. 2E-F and [0079] each of the elements 124 are formed through the exact same process)
S1 does not disclose wherein each of the first gates has a respective thickness in the first direction that is consistent along the third direction
M1 discloses wherein each of the first gates has a respective thickness in the first direction that is consistent along the third direction (see Figs. 4H1-2 and [0091] “A gate electrode material is deposited over substrate 302. For example, approximately 5 nm to about 30 nm of titanium nitride, or other similar conductive material may be deposited … Other conductive materials and/or thicknesses may be used for gate electrodes 408” Gate electrode element 408 has a lateral thickness consistent along the vertical direction).
The rectangular shaped gates with a consistent thickness as taught by M1 is incorporated as the shape of the gates of S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of M1 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gate shape and lateral thickness in the vertical direction for another in a similar memory device for which the gate thickness is disclosed to be adjustable to obtain predictable results (see M1 Figs. 4H1-2 and [0091]).
14. Regarding Claim 14, S1, M1 disclose the semiconductor device of claim 11, wherein the semiconductor device further comprises (see S1):
a second gate insulation layer (element 125 on left sidewalls of element 120) located on second sidewalls (left sidewalls) of the semiconductor pillars and extending along the second direction (see Figs. 15A,C), the first sidewalls and the second sidewalls being opposite sidewalls in the first direction (see Figs. 15A,C); and
a conductive layer (element 124G on a left side surface of the left side element 125) located on a surface of the second gate insulation layer and extending along the second direction (see Figs. 15A,C), wherein the conductive layer serves as a back gate configured to reduce interference between adjacent ones of the first gates (see [0218] “shield gate 124G may function to block off the interference between the neighboring vertical channel transistors TR. The shield gate 124G may be referred to as a back gate, a shield word line, a common gate, or a shield line”;
Note, the limitations directed towards how the conductive layer “serves” to do or “configured to” do are directed towards functional limitations, see MPEP 2173.05(g), because the limitations recite a feature “by what it does rather than by what it is” and “A functional limitation is often used in association with an element, ingredient, or step of a process to define a particular capability or purpose that is served by the recited element, ingredient or step. In Innova/Pure Water Inc. v. Safari Water Filtration Sys. Inc., 381 F.3d 1111, 1117-20, 72 USPQ2d 1001, 1006-08 (Fed. Cir. 2004)”. The prior art discloses the claimed structure which are capable of performing the claimed function such that the claimed limitations do not distinguish from the prior art).
15. Regarding Claim 15, S1, M1 disclose the semiconductor device of claim 14, wherein the second gate insulation layer, the conductive layer and the second gate insulation layer are sequentially disposed along the first direction between adjacent ones of the semiconductor pillars in the first direction (see S1 Fig. 15B,C).
16. Regarding Claim 16, S1, M1 disclose the semiconductor device of claim 14, wherein a material of the conductive layer includes titanium nitride (see S1 [0216] “The shield gate 124G may include a metal, a metal nitride, or a combination thereof. The main gate 124S may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof” and [0214] “The main gate 124S may include a metal, a metal nitride, or a combination thereof. The main gate 124S may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof.” The described metal, metal nitride, or combination for element 124 includes titanium nitride).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Primary Examiner, Art Unit 2818
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