DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Invention II, identified as encompassing claims 11-20 is acknowledged.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Objections
4. Claims 11-20 are objected to because of the following informalities:
5. Claim 11 recites in lines 9-11 “wherein surfaces of a plurality of the first gates close to the first ends are substantially flush, the first direction, the second direction and a third direction intersect each other, and the third direction is an extending direction of each of the semiconductor pillars” which should be changed to along the lines of “wherein surfaces of a plurality of the first gates close to the first ends are substantially flush;[[,]] the first direction, the second direction and a third direction intersect each other, and the third direction is an extending direction of each of the semiconductor pillars” to address the minor informalities.
6. Claim 20 recites in lines 10-13 “wherein surfaces of a plurality of the first gates close to the first ends are substantially flush, the first direction, the second direction and a third direction intersect each other, and the third direction is an extending direction of each of the semiconductor pillars;” which should be changed to along the lines of “wherein surfaces of a plurality of the first gates close to the first ends are substantially flush;[[,]] the first direction, the second direction and a third direction intersect each other, and the third direction is an extending direction of each of the semiconductor pillars;” to address the minor informalities.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 11-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sung (US 2025/0287568 A1), hereinafter as S1
8. Regarding Claim 11, S1 discloses a semiconductor device (see in particular Figs. 1A-2K and [0038] “semiconductor device”), comprising:
a plurality of semiconductor pillars (elements 120, see [0039] “oxide semiconductor pillars 120”) arranged in an array (see Fig. 1) along a first direction (element D1) and a second direction (element D2), first ends (bottom end) of the plurality of semiconductor pillars arranged along the first direction being connected with each other (connected to each other through element 111, see Fig. 1D and [0048]);
a first gate insulation layer (element 125, see [0056] “gate dielectric layer 125”) located on first sidewalls (right sidewalls) of the semiconductor pillars and extending along the second direction (see Fig. 1 the gate insulation layer extends along the oxide semiconductor pillars in the second D2 direction); and
first gates (first one of the elements 124 see [0056] “The tapered vertical word line 124 may be referred to as a tapered vertical gate”) located on a surface (right surface) of the first gate insulation layer and extending along the second direction (see Fig. 1B),
wherein surfaces of a plurality of the first gates close to the first ends are substantially flush (see Figs. 1A-B), the first direction, the second direction and a third direction (element D3) intersect each other (see Fig. 1A), and the third direction is an extending direction of each of the semiconductor pillars (see Fig. 1A).
9. Regarding Claim 12, S1 discloses the semiconductor device of claim 11, wherein thicknesses of the first gates in the first direction are consistent along the third direction (see Fig. 1A, 1D and [0043] The elements 124 are part of the array that are all formed above element 111 to element 126 which have a consistent D3 third direction thickness; also see Figs. 2E-F and [0079] each of the elements 124 are formed through the exact same process).
10. Regarding Claim 13, S1 discloses the semiconductor device of claim 11, wherein cross-section shapes of the first gates on a plane perpendicular to the second direction are rectangular (see Fig. 1B).
11. Regarding Claim 14, S1 discloses the semiconductor device of claim 11, wherein the semiconductor device further comprises:
a second gate insulation layer (element 125 on left sidewalls of element 120) located on second sidewalls (left sidewalls) of the semiconductor pillars and extending along the second direction (see Fig. 1B), the first sidewalls and the second sidewalls being opposite sidewalls in the first direction (see Fig. 1B); and
a conductive layer (element 124 on a left side surface of the left side element 125) located on a surface of the second gate insulation layer and extending along the second direction (see Fig. 1B).
12. Regarding Claim 15, S1 discloses the semiconductor device of claim 14, wherein the second gate insulation layer, the conductive layer and the second gate insulation layer are sequentially disposed along the first direction between adjacent ones of the semiconductor pillars in the first direction (see Fig. 1B).
13. Regarding Claim 16, S1 discloses the semiconductor device of claim 14, wherein a material of the conductive layer includes titanium nitride (see [0055] “word line 124 may include tantalum nitride (TaN), titanium nitride (TiN)”).
14. Regarding Claim 17, S1 discloses the semiconductor device of claim 11, wherein the first gates comprise a gate blocking layer (see [0055] “The tapered vertical word line 124 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof” Selected as titanium nitride for the gate blocking layer) and a gate metal layer (see [0055] selected as tungsten for the gate metal layer), the gate blocking layer being located between the surface of the first gate insulation layer and the gate metal layer (see Figs. 1A-B and [0055]).
15. Regarding Claim 18, S1 discloses the semiconductor device of claim 17, wherein a material of the gate blocking layer includes titanium nitride (see [0055]), and a material of the gate metal layer includes tungsten (see [0055]).
16. Regarding Claim 19, S1 discloses the semiconductor device of claim 14, wherein sizes of the first gates in the third direction are the same as a size of the conductive layer in the third direction (see Fig. 1A, 1D and [0043] The elements 124 are part of the array that are all formed above element 111 to element 126 which have a consistent D3 third direction thickness; also see Figs. 2E-F and [0079] each of the elements 124 are formed through the exact same process).
17. Regarding Claim 20, S1 discloses a memory system (see [0039] “memory elements 130”), comprising:
a semiconductor device (see in particular Figs. 1A-2K and [0038] “semiconductor device”), comprising:
a plurality of semiconductor pillars (elements 120, see [0039] “oxide semiconductor pillars 120”) arranged in an array (see Fig. 1) along a first direction (element D1) and a second direction (element D2), first ends (bottom end) of the plurality of semiconductor pillars arranged along the first direction being connected with each other (connected to each other through element 111, see Fig. 1D and [0048]);
a first gate insulation layer (element 125, see [0056] “gate dielectric layer 125”) located on first sidewalls (right sidewalls) of the semiconductor pillars and extending along the second direction (see Fig. 1 the gate insulation layer extends along the oxide semiconductor pillars in the second D2 direction); and
first gates (first one of the elements 124 see [0056] “The tapered vertical word line 124 may be referred to as a tapered vertical gate”) located on a surface (right surface) of the first gate insulation layer and extending along the second direction (see Fig. 1B),
wherein surfaces of a plurality of the first gates close to the first ends are substantially flush (see Figs. 1A-B), the first direction, the second direction and a third direction (element D3) intersect each other (see Fig. 1A), and the third direction is an extending direction of each of the semiconductor pillars (see Fig. 1A); and
a memory controller (elements TR, see [0043] “vertical channel transistor TR”; see Figs. 1A-D element TR having a channel layer of element 121 electrically connected to the memory elements 130 such that turning the transistor on and off controls the memory elements) coupled to the semiconductor device and configured to control the semiconductor device (see Figs. 1A-D and [0040] “semiconductor device 100 may include a Dynamic Random Access Memory (DRAM)”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818