DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Evaluating whether a claim is eligible subject matter under 35 U.S.C. 101 adheres to the following eligibility analysis procedure:
Step 1: The examiner determines whether then claim belongs to a statutory category. See MPEP § 2016(III).
Step 2A, prong 1: The examiner evaluates whether the claim recites a judicial exception. As explained in MPEP § 2106.04(II), a claim “recites” a judicial exception when the judicial exception is “set forth” or “described” in the claim.
Step 2A, prong 2: The examiner evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception. This evaluation is performed by:
identifying whether there are any additional elements recited in the claim beyond the judicial exception, and
evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application.
Step 2B: The examiner evaluates whether the claim provides an inventive concept, also referred to as “significantly more”. This evaluation is performed by:
identifying whether there are any additional elements recited in the claim beyond the judicial exception, and
evaluating those additional elements individually and in combination to determine whether they amount to significantly more.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1:
The claim language reads: “A system configured for determining information for specimens, comprising:
a computer system configured for generating a sampling plan for only out-of-specification detection of a characteristic of specimens in a metrology process; and
a metrology subsystem configured for generating output for the specimens by performing the metrology process on the specimens with the generated sampling plan;
wherein the computer system is further configured for determining the characteristic of the specimens based on the generated output and detecting if the characteristic of one or more of the specimens is out-of-specification based on the determined characteristic of the specimens”
Under Step 1 of the analysis, claim 1 is an apparatus (machine) claim.
Under Step 2A, prong 1, claim 1 recites at least one judicial exception as it sets forth abstract ideas, namely generating a sampling plan in claim element (i) and determining the characteristic in claim element (iii), that constitute mental processes that are merely data observations, evaluations, and/or judgements which could be performed mentally and/or with the aid of pen and paper in order to determine out-of-specification specimens. The examiner respectfully points out that a combination of abstract ideas is itself an abstract idea. See MPEP §2106.5(I).
Under Step 2A, prong 2, claim 1 recites two additional elements, namely a computer system in claim element (i) and a metrology subsystem in claim element (ii). However, neither of these additional elements integrate the claimed invention into a practical application:
The limitation computer system is merely general-purpose computing hardware configured to perform the recited mental processes via generic computer operations. See Bilski, 561 U.S., Alice Corp. v. CLS Bank Int’l, 573 U.S. 208, and MPEP §2106(I).
The limitation metrology subsystem is used for merely taking the abstract idea of generating a sampling plan and applying said sampling plan using generic hardware within the art. Furthermore, the metrology subsystem implementing the sampling plan serves as a necessary data gathering step for further elements of the claimed invention.
Under Step 2B, the two aforementioned additional elements, a computer system and metrology subsystem, do not amount to significantly more since they are general-purpose computing hardware configured to perform generic computer operations and equipment necessary for essential data gathering and extra-solution activity, respectively.
Furthermore, regarding the dependent claims, claims 2-18 are also rejected as they merely further expand upon the insufficient additional elements of claim 1 and do not recite any further additional elements that integrate the claimed invention into a practical application or amount to significantly more.
Regarding claim 19:
The claim language reads: “A non-transitory computer-readable medium, storing program instructions executable on a computer system for performing a computer-implemented method for determining information for a specimen, wherein the computer-implemented method comprises:
generating a sampling plan for only out-of-specification detection of a characteristic of specimens in a metrology process;
generating output for the specimens by performing the metrology process on the specimens with the generated sampling plan;
determining the characteristic of the specimens based on the generated output; and
detecting if the characteristic of one or more of the specimens is out-of-specification based on the determined characteristic of the specimens.”
Under Step 1 of the analysis, claim 19 is an apparatus (machine) claim.
Under Step 2A, prong 1, claim 1 recites at least one judicial exception as it sets forth limitations, namely in claim elements (i)-(iv), that constitute mental processes that are merely data observations, evaluations, and/or judgements which could be performed mentally and/or with the aid of pen and paper in order to determine out-of-specification specimens.
Under Step 2A, prong 2, claim 1 recites one additional element, namely a non-transitory computer-readable medium in the claim preamble. However, this additional element does not integrate the claimed invention into a practical application as it is merely a generic computer hardware element configured with instructions to be executed on a general-purpose computer. See Bilski, 561 U.S., Alice Corp. v. CLS Bank Int’l, 573 U.S. 208, and MPEP §2106(I).
Under Step 2B, the aforementioned additional element, a non-transitory computer-readable medium, does not amount to significantly more because it is merely a generic computer hardware element configured with instructions to be executed on a general-purpose computer and therefore does not amount to significantly more.
Regarding claim 20:
The claim language reads: “A computer-implemented method for determining information for a specimen, comprising:
generating a sampling plan for only out-of-specification detection of a characteristic of specimens in a metrology process;
generating output for the specimens by performing the metrology process on the specimens with a metrology subsystem and the generated sampling plan;
determining the characteristic of the specimens based on the generated output; and
detecting if the characteristic of one or more of the specimens is out-of-specification based on the determined characteristic of the specimens, wherein generating the sampling plan, said determining, and said detecting are performed by a computer system coupled to the metrology subsystem.”
Under Step 1, claim 1 is method (process) claim.
Under Step 2A, prong 1, claim 1 recites at least one judicial exception as it sets forth limitations, namely in claim elements (i)-(iv), that constitute mental processes that are merely data observations, evaluations, and/or judgements which could be performed mentally and/or with the aid of pen and paper in order to determine out-of-specification specimens.
Under Step 2A, prong 2, claim 1 recites two additional elements, namely “performing the metrology process on the specimens with a metrology subsystem” in claim element (ii) and “…are performed by a computer system coupled to the metrology subsystem.” in claim element (iv). However, neither of these limitations integrate the claimed computer-implemented method into a practical application:
The limitation “performing the metrology process on the specimens with a metrology subsystem” is a necessary data gathering step for performing the other steps in the computer-implemented method.
The limitation “…are performed by a computer system coupled to the metrology subsystem.” recites a general-purpose computer system to perform the claimed computer-implemented method via generic computer functions. See Bilski, 561 U.S., Alice Corp. v. CLS Bank Int’l, 573 U.S. 208, and MPEP §2106(I).
Under Step 2B, the two aforementioned additional elements, “performing the metrology process on the specimens with a metrology subsystem” and “…are performed by a computer system coupled to the metrology subsystem.” do not amount to significantly more because they are merely a necessary data gathering step and a general-purpose computer intended to perform general-purpose computer operations, respectively.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. In particular, it is unclear what it means for a sampling plan to be not configured for feedback control.
Claim 4 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. In particular, it is unclear what qualifies as a density required to enable feedback control of the characteristic.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-6, 11, 13, and 18-20 are rejected under 35 U.S.C. 102(a)(1-2) as being anticipated by Hosoya et al. (US 20030109952 A1, hereinafter Hosoya).
Regarding claim 1, the examiner respectfully points out that Hosoya teaches a system configured for determining information for specimens (Abstract — “…a wafer inspection and sampling system…”), comprising:
A computer system (Abstract — “…a wafer inspection and sampling system…”; one with ordinary skill in the art would understand this system to use computers, see [0066]) configured for generating a sampling plan for only out-of-specification detection of a characteristic of specimens in a metrology process ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on)”; the subsequent inspection is only for defects using the first inspection results as a plan); and
A metrology subsystem ([0003] — “…conventional optical microscopes, scanning electron microscopes (SEMs)…”) configured for generating output for the specimens by performing the metrology process on the specimens with the generated sampling plan ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on)”; the subsequent inspection is only for defects using the first inspection results as a plan);
Wherein the computer system is further configured for determining the characteristic of the specimens based on the generated output and detecting if the characteristic of one or more of the specimens is out-of-specification based on the determined characteristic of the specimens ([0003] — “…the defects are subjected to a detailed review subsequent to the initial inspection…in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; the identification of the type of the defect indicates the specific nature of the wafer being out-of-specification).
Regarding claim 5, the examiner respectfully points out that Hosoya further teaches wherein the sampling plan is configured for generating the output for each of the specimens in a lot ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection…”; the first inspection is performed on each wafer (a lot of wafers is disclosed) to identify all of the specimens to be examined by the metrology subsystem in the subsequent inspection)
Regarding claim 6, the examiner respectfully points out that Hosoya further teaches wherein the sampling plan is configured for generating the output for a subset of the specimens in a lot ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection…; the first wafer inspected in the subsequent inspection constitutes a subset).
Regarding claim 11, the examiner respectfully points out that Hosoya further teaches performing lot sampling ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all…”; the first inspection is performed on each wafer (a lot of wafers is disclosed)), specimen sampling ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all…”; the first inspection is performed on each specimen in a lot), and within-specimen sampling ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection…”; defects on individual specimens are inspected in the subsequent inspection) and distributing a predetermined metrology budget to maximize detection of out of specification specimens ([0004] — “Ideally, a detailed inspection of all defects detected on all semiconductor wafers coming off the production line is made… However, such a brute force approach is not feasible or practical due to the large numbers of wafers that are produced and the large numbers of defects per wafer that can occur.”; the infeasibility of the brute force approach discloses a known metrology time constraint on inspecting every defect on every wafer); ([0004] --— “…the review task is limited to a small population of defects selected from among all of the detected defects. The smaller population of defects are then subjected to further detailed review to gain an understanding of the manufacturing process and to detect process variations, albeit a less accurate understanding.”; lot sampling and specimen sampling are performed in the first inspection; within-specimen sampling is performed in the subsequent inspection; the subsequent inspection is performed on a subset of the total detected defects to maximize understanding of the causes of defects despite the constraints of the metrology time budget).
Regarding claim 13, the examiner respectfully points out that Hosoya further teaches wherein the sampling plan comprises information for one or more selected lots ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection…”; the subsequent inspection uses information from the first inspection as a plan), one or more selected specimens within the one or more selected lots ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all…”; the locations of the defects on the specimens are used in generating the sampling plan), one or more locations on the one or more selected specimens ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all…”; the locations of the defects on the specimens are used in generating the sampling plan), and one or more metrology subsystem settings for generating the output at the one or more locations ([0003] — “…conventional optical microscopes, scanning electron microscopes (SEMs), and the like…”; choice of metrology tool is a subsystem setting), wherein the computer system is further configured for sending the information in the sampling plan to the metrology subsystem ([0003] — "…the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like…)”; that the metrology subsystem performs the subsequent inspection means it received the information in the sampling plan from the computer system), and wherein generating the output with the generated sampling plan is based on the information from the computer system ([0003] — "…the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like…)”; the sampling plan containing information from the computer system is used to generate output in the subsequent inspection).
Regarding claim 18:
The examiner respectfully points out that Hosoya further teaches wherein the metrology subsystem is further configured as a light-based metrology subsystem ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like…”).
Regarding claim 19:
The examiner respectfully points out that Hosoya teaches a non-transitory computer-readable medium (Claim 1 — “…a computer usable medium having computer readable program code…”), storing program instruction executable on a computer system for performing a computer implemented method (Claim 1 — “…a computer usable medium having computer readable program code…”) for determining information for a specimen, wherein the computer-implemented method comprises:
generating a sampling plan for only out-of-specification detection of a characteristic of specimens in a metrology process ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on)”; the subsequent inspection is only for defects using the first inspection results as a plan);
generating output for the specimens by performing the metrology process on the specimens with the generated sampling plan ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on)”; the subsequent inspection is only for defects using the first inspection results as a plan);
determining the characteristic of the specimens based on the generated output ([0003] — “…the defects are subjected to a detailed review subsequent to the initial inspection…in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”); and
detecting if the characteristic of one or more of the specimens is out of specification based on the determined characteristic of the specimens ([0003] — “…the defects are subjected to a detailed review subsequent to the initial inspection…in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; the identification of the type of the defect indicates the specific nature of the wafer being out-of-specification).
Regarding claim 20:
The examiner respectfully points out that Hosoya teaches a computer-implemented method (Claim 1 — “…a computer usable medium having computer readable program code…”) for determining information for a specimen, comprising:
generating a sampling plan for only out of specification detection of a characteristic of specimens in a metrology process ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on)”; the subsequent inspection is only for defects using the first inspection results as a plan);
generating output for the specimens by performing the metrology process on the specimens with a metrology subsystem and the generated sampling plan ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on)”; the subsequent inspection is only for defects using the first inspection results as a plan);
determining the characteristic of the specimens based on the generated output ([0003] — “…the defects are subjected to a detailed review subsequent to the initial inspection…in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”); and
detecting if the characteristic of one or more of the specimens is out of specification based on the determined characteristic of the specimens ([0003] — “…the defects are subjected to a detailed review subsequent to the initial inspection…in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; the identification of the type of the defect indicates the specific nature of the wafer being out-of-specification), wherein generating the sampling plan, said determining, and said detecting are performed by a computer system coupled to the metrology subsystem (Abstract — “…a wafer inspection and sampling system…”; one with ordinary skill in the art would understand this system to use computers, see [0066]; furthermore, the computer system is coupled to the metrology subsystem as it generates output using the sampling plan generated by the computer system, see [0003]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4, 10, 12, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hosoya in view of Roy et al. (US 20210165399 A1, hereinafter Roy).
Regarding claim 2:
The examiner notes that Hosoya teaches the system of claim 1 but fails to teach the characteristic being overlay of one or more first patterned features formed on the specimen to one or more second patterned features formed on the specimen.
The examiner respectfully points out that Roy teaches determining an overlay of one or more first patterned features on a specimen to one or more second patterned features formed on a specimen ([0073] — “…it is desirable to inspect substrates to measure properties of patterned structures, such as overlay errors between subsequent layers…”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to inspect a specimen to determine an overlay of one or more first patterned features formed on the specimen to one or more second patterned features formed on the specimen in combination with the teachings of Hosoya in order to better understand the physical structure of wafer manufacturing defects.
Regarding claim 3:
While rejected under 35 U.S.C. 112(b), this claim is being considered under 35 U.S.C. 103 for the purpose of compact prosecution.
The examiner respectfully notes that according to the applicant’s provided specification, a sampling plan “not configured” for feedback control may be understood to be, within the broadest reasonable interpretation, one that is sufficiently sparse in its number of measurement points (Page 17, lines 12-14 — “In particular, the sampling plan for only out-of-specification monitoring is substantially sparse compared to metrology sampling needed for feedback control”; Page 17, lines 17-18 — “…the sampling plans generated as described herein may be configured to have only one or two measurement points for each wafer…”; Page 17, lines 18-21 — “In this manner, the embodiments described herein may be configured for detecting out-of-specification wafers by performing metrology on a handful of points on each wafer.”).
Hosoya discloses performing feedback control of the characteristic ([0003] — “…how to adjust the processes accordingly to avoid such defects.”) but fails to disclose a sampling plan that is not configured for feedback control of the characteristic.
The examiner respectfully points out that Roy teaches the use of a sparse sampling plan to improve metrology time ([0079] — “Sparse measurements [are] used to limit metrology time, with dense measurements [being] performed less frequently as they require more metrology time…measurements using a sparse sampling layout are performed to produce sparse ADI [data] (e.g. <=200 points per wafer).”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to use a sparse sampling plan as taught by Roy (including when doing so would preclude feedback control) in order to improve metrology time.
Regarding claim 4:
While rejected under 35 U.S.C. 112(b), this claim is being considered under 35 U.S.C. 103 for the purpose of compact prosecution.
The examiner respectfully notes that according to the applicant’s provided specification, a sampling plan with a density “less than a density required to enable” feedback control may be understood to be, within the broadest reasonable interpretation, one that is sufficiently sparse in its number of measurement points (Page 17, lines 12-14 — “In particular, the sampling plan for only out-of-specification monitoring is substantially sparse compared to metrology sampling needed for feedback control”; Page 17, lines 17-18 — “…the sampling plans generated as described herein may be configured to have only one or two measurement points for each wafer…”; Page 17, lines 18-21 — “In this manner, the embodiments described herein may be configured for detecting out-of-specification wafers by performing metrology on a handful of points on each wafer.”).
Hosoya discloses performing feedback control of the characteristic ([0003] — “…how to adjust the processes accordingly to avoid such defects.”) but fails to disclose a sampling plan with a density less than a density required to enable feedback control of the characteristic.
The examiner respectfully points out that Roy teaches the use of a sparse sampling plan to improve metrology time ([0079] — “Sparse measurements [are] used to limit metrology time, with dense measurements [being] performed less frequently as they require more metrology time…measurements using a sparse sampling layout are performed to produce sparse ADI [data] (e.g. <=200 points per wafer).”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to use a sparse sampling plan as taught by Roy (including when doing so would preclude enabling feedback control of the characteristic) in order to improve metrology time.
Regarding claim 10:
Hosoya teaches determining a within-specimen sampling plan ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection…”; a sampling plan is generated from the results of the first inspection to inspect defects within specimens) and metrology subsystem settings ([0019] — “defects are sampled based on statistical techniques to produce a sampling of the defects, which are then subject to subsequent detailed review… any of a number of known statistical techniques are appropriate for sampling defects.”; choosing a particular appropriate statistical technique constitutes determining a metrology subsystem setting) based on constraints on metrology budget and metrology subsystem throughput ([0004] — “Ideally, a detailed inspection of all defects detected on all semiconductor wafers coming off the production line is made… However, such a brute force approach is not feasible or practical due to the large numbers of wafers that are produced and the large numbers of defects per wafer that can occur. Consequently, in practice, the review task is limited to a small population of defects…”; the brute-force approach being infeasible due to the large number of specimens discloses metrology time budget and throughput constraints in generating a sampling plan from the results of the first inspection). However, Hosoya fails to teach wherein generating the sampling plan comprises determining a frequency of lot sampling, a frequency of within-lot sampling, or metrology subsystem settings based on constraints on metrology budget and metrology subsystem throughput.
Roy teaches determining a frequency of lot sampling ([0011] — “…dense overlay measurements can practically be performed only once in several lots…”; the determination is made based on budget and throughput constraints, see [0008] — “Corrections that require such a denser metrology sampling cannot be done frequently without adversely affecting throughput.”) and a frequency of within-lot sampling ([0195] — “For alignment, only few wafers per lot are required to have spatially dense measurements…”; the determination is based on budget and throughput constraints, see [0010] — “…only small number of alignment marks can be measured (˜40) during exposure without impacting throughput. High-order alignment control requires denser alignment layout and impacts throughput.”) based on constraints on metrology budget and metrology subsystem throughput. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to determine lot sampling and within-lot sampling frequencies as taught by Roy with the teachings of Hosoya to improve metrology time when inspecting overlay and alignment defects.
Regarding claim 12:
The examiner respectfully points out that Hosoya teaches wherein generating the sampling plan comprises optimizing metrology subsystem settings to maximize detection of out-of-specification specimens at a predetermined metrology subsystem throughput ([0004] — “Ideally, a detailed inspection of all defects detected on all semiconductor wafers coming off the production line is made in order to provide as complete an understanding as possible of the manufacturing process. However, such a brute force approach is not feasible or practical due to the large numbers of wafers that are produced and the large numbers of defects per wafer that can occur. Consequently, in practice, the review task is limited to a small population of defects selected from among all of the detected defects.”; the size of this defect subset is a metrology subsystem setting chosen to maximize defect detection despite the metrology time budget; a time budget may be algebraically transformed into a throughput budget via dimensional analysis). However, Hosoya fails to teach optimizing sampling frequency for the same purpose.
Roy teaches optimizing sampling frequency to maximize detection of out-of-specification specimens at a predetermined metrology subsystem throughput ([0011] — “…dense overlay measurements can practically be performed only once in several lots…”; the frequency is chosen based on budget and throughput constraints, see [0008] — “Corrections that require such a denser metrology sampling cannot be done frequently without adversely affecting throughput.”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to co-optimize sampling frequency as taught by Roy with metrology subsystem settings as taught by Hosoya to further improve out-of-specification detection and metrology budget usage.
Regarding claim 14:
The examiner respectfully points out that Hosoya teaches using a sampling plan suitable for feedback control ([0003] — “This additional detailed information…” — from the subsequent inspection — “…facilitates an understanding of the causes of the defects, to detect that the process is changing, how the process is changing, and how to adjust the processes accordingly to avoid such defects.”) and wherein the computer system is further configured for determining a correction process for the at least one of the specimens based on the generated output ([0003] — “…how the process is changing, and how to adjust the processes accordingly to avoid such defects.”). However, Hosoya fails to teach configuring the metrology subsystem for generating additional output for at least one of the specimens with a different sampling plan.
Roy teaches performing a high-density sampling plan (i.e. the recited “additional metrology process”) ([0079] — “Etch (ETC) 410 is followed by after-etch inspection (AEI) overlay measurements that are dense and sparse 412, and hyper-dense 414.”) for performing feedback control ([0083] — “hyper-dense after-etch 414 measurements are performed…. hyper-dense data 424 (e.g. 10,000 points per wafer) is used for further modelling of fingerprints associated with individual exposure fields, for example to enable Corrections Per Exposure (CPE) of the overlay fingerprint.”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to generate additional output on at least one specimen using a hyper-dense sampling plan suitable for feedback control as taught by Roy after performing a first inspection process as taught by Hosoya (the plan taught by Roy may use the results of the first generated output from Hosoya to determine which specimens require a hyper-dense inspection), wherein the computer system therein uses the additional generated output for determining a correction process, in order to better understand the physical nature of defects and improve the manufacturing process.
Regarding claim 15:
The examiner respectfully points out that Hosoya teaches wherein the computer system is further configured for selecting at least one of the one or more of the specimens detected to be out of specification ([0003] — "An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection…”; that the first inspection is used for generating the sampling plan for the subsequent inspection, which is performed only on wafers with defects. means the computer system is configured for selecting specimens). However, Hosoya fails to teach performing a metrology process with a denser sampling plan than the generated sampling plan.
Roy teaches performing a metrology with a hyper-dense sampling plan ([0083] — “hyper-dense after-etch 414 measurements are performed…. hyper-dense data 424 (e.g. 10,000 points per wafer) is used for further modelling of fingerprints associated with individual exposure fields, for example to enable Corrections Per Exposure (CPE) of the overlay fingerprint.”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to perform a hyper-dense metrology process as taught by Roy on a selected out-of-specification specimen as taught by Hosoya in order to better understand the structure of the defects.
Regarding claim 16:
The examiner respectfully points out that Hosoya further teaches wherein the computer system is further configured for determining a correction process for the at least one of the one or more of the specimens based on the out generated with the denser sampling plan ([0003] — “…how the process is changing, and how to adjust the processes accordingly to avoid such defects.”). It would have been obvious to further correct the wafer manufacturing process using the hyper-dense generated output.
Regarding claim 17:
The examiner respectfully points out that the hyper-dense sampling plan taught by Roy used in the metrology process performed with a denser sampling plan than the generated sampling plan is configured for feedback control of the characteristic (([0083] — “hyper-dense after-etch 414 measurements are performed…. hyper-dense data 424 (e.g. 10,000 points per wafer) is used for further modelling of fingerprints associated with individual exposure fields, for example to enable Corrections Per Exposure (CPE) of the overlay fingerprint.”)).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hosoya.
The examiner respectfully notes that according to the applicant’s provided specification, generating the sampling plan “to match out-of-specification criteria for the specimens” by selecting a number and coordinates of locations at which to generate output may be understood to be, within the broadest reasonable interpretation, selecting a number of sampling points adhering to some statistical criteria chosen by the user (Page 18, lines 20-24 — “For example, the number and location of the metrology points (i.e., the sampling plan) may be selected to match the out-of-specification criteria used on a given layer and device in a manufacturing process. In this way, the number of out-of-specification wafers that can be detected and fixed is maximized with the smallest throughput hit.”; Page 18-19, lines 26-7 — “The user (e.g., a device manufacturer) may use a statistic such as absolute value of the mean + 3*standard deviation of the measured overlay for wafer quality control. For each layer and device, a threshold is defined on the statistic beyond which a wafer or lot would be considered out-of-specification… the computer system may use one of the existing sampling optimization methods to generate multiple relatively sparse sampling plans… The sampling plan that tracks the original statistic the best can be selected as the sampling plan for out-of-specification detection.”).
The examiner respectfully points out that Hosoya further teaches wherein generating the sampling plan comprises selecting a number and coordinates of locations at which the metrology subsystem generates output in the metrology process ([0004] — “in practice, the review task is limited to a small population of defects selected from among all of the detected defects. The smaller population of defects are then subjected to further detailed review to gain an understanding of the manufacturing process and to detect process variations”; taking a subset of defects in generating the sampling plan from the results of the first inspection includes selecting a number of defects and their coordinates, see [0003] — “The initial inspection can only identify that defects exist, the number of defects, their locations on the wafer, etc.”), but fails to disclose wherein this is done to match out-of-specification criteria for the specimens in [0003] or [0004].
Hosoya separately contemplates selecting locations to match out-of-specification criteria for the specimens ([0011] — “The defects are sampled based on statistical criteria to produce sampled defects.”; a subset of points is taken to generate a sampling plan from the results of the first inspection based on statistical criteria, see [0019] — “In accordance with embodiments of the invention, semiconductor wafer defects are sampled based on statistical techniques to produce a sampling of the defects, which are then subject to subsequent detailed review. In an illustrative embodiment of the invention, statistical criteria such as a reliability and allowable error are used as the basis for sampling.”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to select a number and coordinates of locations at which the metrology subsystem generates output as taught by Hosoya in [0003] and [0004] adhering to a statistical criteria to match out-of-specification criteria for the specimens as taught by Hosoya in [0011] and [0019] to improve metrology time and/or improve out-of-specification detection.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hosoya in view of Park et al. (US 20090043527 A1, hereinafter Park).
Regarding claim 8:
The examiner respectfully notes that according to the applicant’s provided specification, “determining a metric based on the generated output and a predetermined statistical process control metric that separates in-specification specimens from out-of-specification specimens” may be understood to be, within the broadest reasonable interpretation, determining a threshold metric by computing a preselected statistical quantity such as mean and/or standard deviation (Page 19, lines 9-21 — “In some embodiments, the computer system is configured for determining a metric based on the generated output and a predetermined statistical process control (SPC) metric that separates in-specification specimens from out-of-specification specimens… More specifically, users may measure multiple overlay points per wafer and calculate mean and standard deviation of these measurements. A statistic such as absolute value of mean + 3*standard deviation is an example of such a metric… The computer system may define a threshold on this metric to separate in-specification wafers from out-of-specification wafers…”).
Hosoya fails to teach determining a metric based on the generated output and a predetermined statistical process control metric that separates in-specification specimens from out-of-specification specimens.
The examiner respectfully points out that Park teaches determining a threshold metric based on the generated output and a predetermined statistical process control metric ([0058] — “…the mean and standard deviation of the distribution of the values of the attribute may be determined for the population of defects…”; the predetermined statistical process control metric is standard deviation computed from the defect data) that separates in-specification specimens from out-of-specification specimens ([0058] — “…thresholds [may] correspond to the values of the attribute that are two standard deviations from the mean. Therefore, in this example, defects that have values of the attribute that are between thresholds [may] be determined to have attributes that are normal, while defects that have values of the attribute that are not between the thresholds may be determined to have attributes that are abnormal from the attribute of the population.”; the severity of the detected defects further informs whether a specific wafer is out-of-specification or not). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to determine a metric as taught by Park in the metrology system taught by Hosoya to improve out-of-specification detection recall.
Regarding claim 9, the examiner respectfully points out that Park teaches wherein the computer system is further configured for determining a threshold for the determined metric ([0058] — “…thresholds [may] correspond to the values of the attribute that are two standard deviations from the mean…) that separates the in-specification specimens from the out-of-specification specimens ([0058] — “…defects that have values of the attribute that are not between the thresholds may be determined to have attributes that are abnormal from the attribute of the population.”; the severity of the detected defects further informs whether a specific wafer is out-of-specification or not).
Prior Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
Ikeda et al. (US 20090192743 A1), Sampling Estimating Method, Sampling Inspection Estimating Apparatus, and Computer Readable Medium Storing Sampling Inspection Estimating Program
Chen et al., Optimum sampling for track PEB CD Integrated Metrology, 2009 IEEE International Conference on Automation Science and Engineering, Bangalore, India, 2009, pp. 439-442, doi: 10.1109/COASE.2009.5234083
Norman et al. (US 20220120698 A1), Methods and Apparatus for Detecting Defects in Semiconductor Systems
Lin et al. (US 20130176558 A1), Detecting Method for Forming Semiconductor Device
Koek et al. (US 20200340953 A1), Subsurface Inspection Method and System
Plemmons et al. (US 20050024632 A1), Detection of a Wafer Edge Using Collimated Light
Ishikawa, Akio (US 20060245635 A1), Appearance Inspection Apparatus and Appearance Inspection Method
Tian et al. (US 20090319214 A1), Optical Metrology System Optimized with Design Goals
Groger, Philip (US 20220137607 A1), Method of Manufacturing a Semiconductor Device and Process Control System for a Semiconductor Manufacturing Assembly
Lo et al. (US 20190384185 A1), Integrated Circuit Overlay Test Patterns and Method Thereof
Zhu et al. (US 20140107828 A1), Method and System for Wafer Quality Predictive Modeling Based On Multi-Source Information with Heterogeneous Relatedness
The examiner made use of these sources to better understand the art and contextualize the claimed invention therein.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN JAMES STEAR whose telephone number is (571)272-8334. The examiner can normally be reached 8:00-6:00 EST/EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arleen Vazquez can be reached at (571) 272-2619. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN JAMES STEAR/Examiner, Art Unit 2857
/ARLEEN M VAZQUEZ/Supervisory Patent Examiner, Art Unit 2857