DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, 3-4, 7, 10-13, and 19-20 have been amended and claims 14-17 have been canceled. Claims 1-13 and 18-20 are pending.
Response to Arguments
35 USC 101
The examiner has considered the arguments filed by the applicant regarding claim rejections under 35 USC 101 and finds them persuasive. Accordingly, the rejections for claims 1-13 and 18-20 under 35 USC 101 have been withdrawn.
35 USC 112(b)
The examiner has considered the arguments filed by the applicant regarding claim rejections under 35 USC 112(b) and finds them persuasive. Accordingly, the rejections for claims 3-4 under 35 USC 112(b) have been withdrawn. However, the applicant’s amendments to the claims necessitate novel consideration under 35 USC 112(b). The new grounds for rejection are presented below, see Claim Rejections — 35 USC 112(b).
35 USC 102(a)(1-2)
The examiner has considered the arguments filed by the applicant regarding claim rejections under 35 USC 102 and finds them persuasive. Accordingly, the rejections for claims 1, 5-6, 11, 13, and 18-20 under 35 USC 102 have been withdrawn.
35 USC 103
The examiner has considered the arguments filed by the applicant regarding claim rejections under 35 USC 103 and finds them persuasive. Accordingly, the rejections for claims 2-4, 10, and 12 have been withdrawn. However, the applicant’s amendments to the claims necessitate novel consideration under 35 USC 103 in view of further consideration of Hosoya et al. (US 20030109952 A1) and newly found prior art. The new grounds for rejection are presented below, see Claim Rejections — 35 USC 103.
Claim Rejections - 35 USC § 112
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-13 and 18-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 19-20
Claims 1 and 19-20 all include the limitation “wherein said selecting is performed independently of inspection results for the specimens” in the first claim element. It is unclear what it means for “selecting”, a verb, to be independent of a noun, “inspection results for the specimens”.
Claims 2-13 and 18 are also rejected by virtue of their dependence from claim 1.
Claim Rejections - 35 USC § 103
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7, 10-13, and 18-20 are rejected under 35 USC 103 as being unpatentable over Hosoya et al. (US 20030109952 A1, hereinafter Hosoya) in view of Cekli et al. (US 20190137892 A1, hereinafter Cekli), Tian et al. (US 20090319214 A1, hereinafter Tian), and Roy et al. (US 20210165399 A1, hereinafter Roy).
Claims 1 and 19-20
Hosoya discloses a system (Abstract — “…a wafer inspection and sampling system…”) and a corresponding non-transitory computer-readable medium (Claim 1 — “…a computer usable medium having computer readable program code…”), storing program instruction executable on a computer system for performing a corresponding computer implemented method (Claim 1 — “…a computer usable medium having computer readable program code…”), configured for determining information for specimens, comprising: a computer system (Abstract — “…a wafer inspection and sampling system…”; this system would use computers, see [0066]) configured for generating a sampling plan for only out of specification detection of a characteristic of specimens in a metrology process ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; the subsequent inspection is only for defects using the first inspection results as a plan), wherein generating the sampling plan comprises selecting locations on the specimens at which the metrology process is performed ([0004] — “Consequently, in practice, the review task is limited to a small population of defects selected from among all of the detected defects. The smaller population of defects are then subjected to further detailed review to gain an understanding of the manufacturing process and to detect process variations, albeit a less accurate understanding.”; the selected locations are at the detected defects), wherein said selecting is performed independently of inspection results for the specimens ([0004] — “Consequently, in practice, the review task is limited to a small population of defects selected from among all of the detected defects. The smaller population of defects are then subjected to further detailed review to gain an understanding of the manufacturing process and to detect process variations, albeit a less accurate understanding.”; the selection is performed independently of inspection results for the specimens because the inspection only for defects has yet to be performed); and a metrology subsystem ([0003] — “…conventional optical microscopes, scanning electron microscopes (SEMs)…”) configured for generating output for the specimens by performing the metrology process on the specimens with the generated sampling plan ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; the subsequent inspection is only for defects using the first inspection results as a plan); wherein the computer system is further configured for: determining the characteristic of the specimens based on the generated output ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”); detecting if the characteristic of one or more of the specimens is out of specification based on the determined characteristic of the specimens ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; the identification of the type of the defect indicates the specific nature of the wafer being out of specification); selecting at least one of the one or more of the specimens detected to be out of specification ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection…”; that the first inspection is used for generating the sampling plan for the subsequent inspection, which is performed only on wafers with defects, means the computer system is configured for selecting specimens); and determining a correction process for the at least one of the one or more of the specimens based on the output generated with the denser sampling plan ([0003] — “This additional detailed information facilitates an understanding of the causes of the defects, to detect that the process is changing, how the process is changing, and how to adjust the processes accordingly to avoid such defects.”).
Hosoya fails to disclose wherein selecting the locations comprises selecting fewer than ten of the locations on each of the specimens; wherein the metrology subsystem comprises at least an energy source and a detector, wherein the energy source is configured to generate energy that is directed to the specimens, and wherein the detector is configured to detect energy from the specimens and to generate the output responsive to the detected energy; selecting at least one of the one or more of the specimens detected to be out of specification for which the metrology process is performed with a denser sampling plan than the generated sampling plan (Hosoya teaches selecting at least one of the one or more of the specimens to be out of specification but not for which the metrology process is performed with a denser sampling plan than the generated sampling plan), wherein the denser sampling plan is configured for feedback control of the characteristic; and wherein the system performs the correction process on the at least one of the one or more of the specimens with a fabrication process tool.
Cekli discloses wherein selecting the locations comprises selecting fewer than ten of the locations on each of the specimens ([0081] — “In a simple example, the set of measurement locations may comprise more than 20 locations, for example 28 locations, while the preliminary selection of measurement locations comprises fewer than 10 locations, for example 8 locations.”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to select fewer than ten of the locations on each of the specimens as disclosed by Cekli in the system disclosed by Hosoya in order to improve processing time.
Hosoya and Cekli still fail to disclose wherein the metrology subsystem comprises at least an energy source and a detector, wherein the energy source is configured to generate energy that is directed to the specimens, and wherein the detector is configured to detect energy from the specimens and to generate the output responsive to the detected energy; selecting at least one of the one or more of the specimens detected to be out of specification for which the metrology process is performed with a denser sampling plan than the generated sampling plan, wherein the denser sampling plan is configured for feedback control of the characteristic; and wherein the system performs the correction process on the at least one of the one or more of the specimens with a fabrication process tool.
Tian discloses a metrology system which comprises at least an energy source and a detector (Fig. 1A — Metrology Beam Source 41 is an energy source and Metrology Beam Receiver 51 is a detector), wherein the energy source is configured to generate energy that is directed to the specimens (Fig. 1A — Illumination Beam 43 shows generated energy from the energy source directed to the specimens, Target Structure 59), and wherein the detector is configured to detect energy from the specimens and to generate the output responsive to the detected energy (Fig. 1A — The detector (Metrology Beam Receiver 51) detects energy (Detection Beam 49) from the specimens (Target Structure 59) and generates the output responsive to the detected energy (Diffraction Signal 57)). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to use the metrology system disclosed by Tian as the metrology subsystem in the system disclosed by Hosoya and Cekli to take advantage of the high precision of beam-based metrology.
Hosoya, Cekli, and Tian still fail to disclose selecting at least one of the one or more of the specimens detected to be out of specification for which the metrology process is performed with a denser sampling plan than the generated sampling plan, wherein the denser sampling plan is configured for feedback control of the characteristic; and wherein the system performs the correction process on the at least one of the one or more of the specimens with a fabrication process tool.
Roy discloses a metrology process performed with a dense sampling plan ([0083] — “Dense after-develop 408 or hyper-dense after-etch 414 measurements are performed. These measurements are typically not performed for every lot, because of the additionally required metrology effort. The dense data 418 (e.g. 2,000 point[s] per wafer) or hyper-dense data 424 (e.g. 10,000 points per wafer) is used for further modelling of fingerprints associated with individual exposure fields, for example to enable Corrections Per Exposure (CPE) of the overlay fingerprint.”), wherein the denser sampling plan is configured for feedback control of a characteristic ([0083] — “The dense data 418 (e.g. 2,000 point[s] per wafer) or hyper-dense data 424 (e.g. 10,000 points per wafer) is used for further modelling of fingerprints associated with individual exposure fields, for example to enable Corrections Per Exposure (CPE) of the overlay fingerprint.”); and wherein the system performs a correction process on specimens with a fabrication process tool ([0080] — “The sparse model result (process fingerprint) 428 is averaged over lots (for example using an Exponentially Weighted Moving Average) to reduce the impact of lot-to-lot variation and as such can be used, either directly or via a correction optimization step (OPT) 426, to provide stable corrections that can be applied to the exposure 404 of the next lot(s).”; correcting exposure on specimens with a lithographic apparatus (see Fig. 1) constitutes performing a correction process on specimens with a fabrication process tool). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to perform the metrology process with the denser sampling plan configured for feedback control of the characteristic disclosed by Roy on the selected at least one of the one or more of the specimens detected to be out of specification disclosed by Hosoya and have the system perform the correction process on specimens with a fabrication process tool further disclosed by Roy in order to better understand the structure of the defects and improve production quality of the specimens.
Claim 2
Hosoya fails to disclose the characteristic being overlay of one or more first patterned features formed on the specimen to one or more second patterned features formed on the specimen.
Roy discloses the characteristic being overlay of one or more first patterned features formed on the specimen to one or more second patterned features formed on the specimen ([0073] — “In order for the substrates W exposed by the lithographic apparatus LA to be exposed correctly and consistently, it is desirable to inspect substrates to measure properties of patterned structures, such as overlay errors between subsequent layers…”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to include the characteristic being overlay of one or more first patterned features formed on the specimen to one or more second patterned features formed on the specimen disclosed by Roy in the system disclosed by Hosoya, Cekli, Tian, and Roy in order to better understand the physical structure of wafer manufacturing defects.
Claim 3
Per the applicant’s specification, a sampling plan with only one or two measurement points for each wafer (or a subset of wafers) does not have enough metrology points to perform overlay feedback control (Specification, Page 17, lines 14-19 — “More specifically, the proposed substantially sparse sampling plans for only out of specification detection do not have enough metrology points to perform overlay feedback control based on metrology results generated at the metrology points. For example, the sampling plans generated as described herein may be configured to have only one or two measurement points for each wafer (or a subset of wafers) in each lot.”).
Hosoya fails to disclose wherein the sampling plan is not configured for the feedback control of the characteristic by only having one or two of the selected locations for each of the specimens or a subset of the specimens in a lot.
Cekli discloses a sampling plan not configured for the feedback control of the characteristic by only having one or two of the selected locations for each of the specimens or a subset of the specimens in a lot ([0081] — “In a simple example, the set of measurement locations may comprise more than 20 locations, for example 28 locations, while the preliminary selection of measurement locations comprises fewer than 10 locations, for example 8 locations.”; the range discloses the case where there are only one or two selected locations, which would preclude feedback control). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to use a sampling plan not configured for the feedback control of the characteristic by only having one or two of the selected locations disclosed by Cekli in the system disclosed by Hosoya, Cekli, Tian, and Roy in order to improve metrology time.
Claim 4
Per the applicant’s specification, a sampling plan with only one or two measurement points for each wafer (or a subset of wafers) does not have enough metrology points to perform overlay feedback control (Specification, Page 17, lines 14-19 — “More specifically, the proposed substantially sparse sampling plans for only out of specification detection do not have enough metrology points to perform overlay feedback control based on metrology results generated at the metrology points. For example, the sampling plans generated as described herein may be configured to have only one or two measurement points for each wafer (or a subset of wafers) in each lot.”).
Hosoya fails to disclose wherein a density of the sampling plan is less than a density required to enable the feedback control of the characteristic by only having one or two of the selected locations for each of the specimens or a subset of the specimens in a lot.
Cekli discloses a density of a sampling plan being less than a density required to enable the feedback control of the characteristic by only having one or two of the selected locations for each of the specimens or a subset of the specimens in a lot ([0081] — “In a simple example, the set of measurement locations may comprise more than 20 locations, for example 28 locations, while the preliminary selection of measurement locations comprises fewer than 10 locations, for example 8 locations.”; the range discloses the case where there are only one or two selected locations, which would preclude feedback control). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to use a sampling plan with a density less than a density required to enable the feedback control of the characteristic by only having one or two of the selected locations disclosed by Cekli in the system disclosed by Hosoya, Cekli, Tian, and Roy in order to improve metrology time.
Claim 5
Hosoya discloses wherein the sampling plan is configured for generating the output for each of the specimens in a lot ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all…”; the first inspection is performed on each wafer (a lot of wafers is disclosed) to identify all of the specimens to be examined by the metrology subsystem in the subsequent inspection).
Claim 6
Hosoya discloses wherein the sampling plan is configured for generating the output for a subset of the specimens in a lot ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; the first wafer inspected in the subsequent inspection constitutes a subset).
Claim 7
Hosoya discloses wherein generating the sampling plan further comprises selecting a number and coordinates of the locations at which the metrology subsystem generates the output in the metrology process ([0004] — “Consequently, in practice, the review task is limited to a small population of defects selected from among all of the detected defects. The smaller population of defects are then subjected to further detailed review to gain an understanding of the manufacturing process and to detect process variations, albeit a less accurate understanding.”; taking a subset of defects in generating the sampling plan from the results of the first inspection includes selecting a number of defects and their coordinates, see [0003] — “The initial inspection can only identify that defects exist, the number of defects, their locations on the wafer, etc., but generally cannot identify the kinds of defects.”).
Hosoya fails to disclose wherein this is done to match out of specification criteria for the specimens in [0003] or [0004].
Hosoya separately contemplates selecting locations to match out of specification criteria for the specimens ([0011] — “The defects are sampled based on statistical criteria to produce sampled defects.”; a subset of points is taken to generate a sampling plan from the results of the first inspection based on statistical criteria, see [0019] — “In an illustrative embodiment of the invention, statistical criteria such as a reliability and allowable error are used as the basis for sampling.”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to include wherein generating the sampling plan further comprises selecting a number and coordinates of the locations at which the metrology subsystem generates output as disclosed by Hosoya in [0003] and [0004] adhering to a statistical criteria to match out of specification criteria for the specimens as disclosed by Hosoya in [0011] and [0019] to improve metrology time and/or improve out of specification detection.
Claim 10
Hosoya discloses wherein generating the sampling plan further comprises determining within-specimen sampling plans ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection…”; a sampling plan is generated from the results of the first inspection to inspect defects within specimens) and metrology subsystem settings ([0019] — “In accordance with embodiments of the invention, semiconductor wafer defects are sampled based on statistical techniques to produce a sampling of the defects, which are then subject to subsequent detailed review… However, it will be readily apparent from the following discussion that any of a number of known statistical techniques are appropriate for sampling defects.”; choosing a particular appropriate statistical technique constitutes determining a metrology subsystem setting) based on constraints on metrology budget and metrology subsystem throughput ([0004] — “Ideally, a detailed inspection of all defects detected on all semiconductor wafers coming off the production line is made in order to provide as complete an understanding as possible of the manufacturing process. However, such a brute force approach is not feasible or practical due to the large numbers of wafers that are produced and the large numbers of defects per wafer that can occur. Consequently, in practice, the review task is limited to a small population of defects selected from among all of the detected defects.”; the brute-force approach being infeasible due to the large number of specimens discloses metrology time budget and throughout constraints in generating a sampling plan from the results of the first inspection).
Hosoya fails to disclose wherein generating the sampling plan further comprises determining a frequency of lot sampling and a frequency of within-lot sampling based on constraints on metrology budget and metrology subsystem throughput.
Roy discloses determining a frequency of lot sampling ([0011] — “For overlay control, dense overlay measurements can practically be performed only once in several lots (known as higher-order parameter update) to update the high-order correction.”) and a frequency of within-lot sampling ([0195] — “For alignment, only few wafers per lot are required to have spatially dense measurements, while all wafers receive different control recipes determined based on different high-order parameters.”) based on constraints on metrology budget and metrology subsystem throughput ([0008] — “Corrections that require such a denser metrology sampling cannot be done frequently without adversely affecting throughput.”; this discloses constraints on metrology budget and metrology subsystem throughput). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to include wherein generating the sampling plan further comprises determining a frequency of lot sampling and within-lot sampling based on constraints on metrology budget and metrology subsystem throughput as disclosed by Roy with determining within-specimen sampling plans and metrology subsystem settings based on constraints on metrology budget and metrology subsystem throughput as disclosed by Hosoya to improve metrology time when inspecting overlay and alignment defects.
Claim 11
Hosoya discloses wherein generating the sampling plan further comprises distributing a predetermined metrology budget ([0004] — “Ideally, a detailed inspection of all defects detected on all semiconductor wafers coming off the production line is made in order to provide as complete an understanding as possible of the manufacturing process. However, such a brute force approach is not feasible or practical due to the large numbers of wafers that are produced and the large numbers of defects per wafer that can occur.”; the infeasibility of the brute force approach discloses a known metrology time constraint on inspecting every defect on every wafer) between lot sampling ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all.”; the first inspection is performed on each wafer (a lot of wafers id disclosed)), specimen sampling ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all.”; the first inspection is performed on each specimen in a lot), and within-specimen sampling ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; defects on individual specimens are inspected in the subsequent inspection) to maximize detection of out of specification specimens ([0004] — “Consequently, in practice, the review task is limited to a small population of defects selected from among all of the detected defects. The smaller population of defects are then subjected to further detailed review to gain an understanding of the manufacturing process and to detect process variations, albeit a less accurate understanding.”; the subsequent inspection is performed on a subset of the total detected defects to maximize understanding of the causes of defects despite the constraints of the metrology time budget).
Claim 12
Hosoya discloses wherein generating the sampling plan further comprises optimizing metrology subsystem settings to maximize detection of out of specification specimens at a predetermined metrology subsystem throughput ([0004] — “Ideally, a detailed inspection of all defects detected on all semiconductor wafers coming off the production line is made in order to provide as complete an understanding as possible of the manufacturing process. However, such a brute force approach is not feasible or practical due to the large numbers of wafers that are produced and the large numbers of defects per wafer that can occur. Consequently, in practice, the review task is limited to a small population of defects selected from among all of the detected defects.”; the size of this defect subset is a metrology subsystem setting chosen to maximize defect detection despite the metrology time budget; a time budget may be algebraically transformed into a throughput budget via dimensional analysis).
Hosoya fails to disclose wherein generating the sampling plan further comprises co-optimizing sampling frequency and metrology subsystem settings to maximize detection of out of specification specimens at a predetermined metrology subsystem throughput.
Roy discloses wherein generating the sampling plan further comprises optimizing sampling frequency to maximize detection of out of specification specimens at a predetermined metrology subsystem throughput ([0011] — “For overlay control, dense overlay measurements can practically be performed only once in several lots (known as higher-order parameter update) to update the high-order correction.”; the frequency is chosen to maximize detection of out of specification specimens based on metrology subsystem throughput, see [0008] — “Corrections that require such a denser metrology sampling cannot be done frequently without adversely affecting throughput.”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to co-optimize sampling frequency as disclosed by Roy with metrology subsystem settings as disclosed by Hosoya to maximize detection of out of specification specimens at a predetermined metrology subsystem throughput in order to further improve out of specification detection and metrology budget usage.
Claim 13
Hosoya discloses wherein the sampling plan comprises information for one or more selected lots ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all. A variety of inspection tools are available for making such inspections… Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; the subsequent inspection uses information from the first inspection as a plan), one or more selected specimens within the one or more selected lots ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all.”; the locations of the defects on the specimens are used in generating the sampling plan), one or more of the locations on the one or more selected specimens ([0003] — “An initial inspection of each wafer is made to detect that there are defects at all.”; the locations of the defects on the specimens are used in generating the sampling plan), and one or more metrology subsystem settings for generating the output at the one or more of the locations ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; choice of metrology tool is a subsystem setting), wherein the computer system is further configured for sending the information in the sampling plan to the metrology subsystem ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; that the metrology subsystem performs the subsequent inspection means it received the information in the sampling plan from the computer system), and wherein generating the output with the generated sampling plan is based on the information from the computer system ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”; the sampling plan containing information from the computer system is used to generate output in the subsequent inspection).
Claim 18
Hosoya discloses wherein the metrology subsystem is further configured as a light-based metrology subsystem ([0003] — “Consequently, the defects are subjected to a detailed review subsequent to the initial inspection using technologies including conventional optical microscopes, scanning electron microscopes (SEMs), and the like in order to determine the specific kinds of defects (e.g., shorts, disconnections, and so on).”).
Claims 8-9 are rejected under 35 USC 103 as being unpatentable over Hosoya, Cekli, Tian, and Roy in view of Park et al. (US 20090043527 A1, hereinafter Park).
Claim 8
Hosoya fails to disclose determining a metric based on the generated output and a predetermined statistical process control metric that separates in specification specimens from out of specification specimens.
Park discloses determining a metric based on the generated output and a predetermined statistical process control metric ([0058] — “For example, the mean and standard deviation of the distribution of the values of the attribute may be determined for the population of defects, and thresholds 24 shown in FIG. 3 may correspond to the values of the attribute that are two standard deviations from the mean.”) that separates in specification specimens from out of specification specimens ([0058] — “For example, the mean and standard deviation of the distribution of the values of the attribute may be determined for the population of defects, and thresholds 24 shown in FIG. 3 may correspond to the values of the attribute that are two standard deviations from the mean. Therefore, in this example, defects that have values of the attribute that are between thresholds 24 may be determined to have attributes that are normal, while defects that have values of the attribute that are not between the thresholds may be determined to have attributes that are abnormal from the attribute of the population.”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to determine a metric as disclosed by Park in the metrology system disclosed by Hosoya, Cekli, Tian, and Roy to improve out of specification detection recall.
Claim 9
Park already discloses wherein the computer system is further configured for determining a threshold for the determined metric ([0058] — “For example, the mean and standard deviation of the distribution of the values of the attribute may be determined for the population of defects, and thresholds 24 shown in FIG. 3 may correspond to the values of the attribute that are two standard deviations from the mean.”) that separates the in specification specimens from the out of specification specimens ([0058] — “Therefore, in this example, defects that have values of the attribute that are between thresholds 24 may be determined to have attributes that are normal, while defects that have values of the attribute that are not between the thresholds may be determined to have attributes that are abnormal from the attribute of the population.”; the severity of the detected defect further informs whether a specific wafer is out of specification or not).
Prior Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
Gao et al. (US 20040156540 A1), Automatic Supervised Classifier Setup Tool for Semiconductor Defects
Horai et al. (US 20040101099 A1), Surface Inspection Method and Surface Inspection Apparatus
Buhl et al. (US 20190250516 A1), Process Control Method for Lithography Processed Semiconductor Devices
Davis, Matthew (US 20160111307 A1), Integrated Substrate Defect Detection Using Precision Coating
Vukkadala et al. (US 20160163033 A1), Predicting and Controlling Critical Dimension Issues and Pattern Defectivity in Wafers Using Interferometry
The examiner used the above prior art to better contextualize the claimed invention within the current state of the art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN JAMES STEAR whose telephone number is (571)272-8334. The examiner can normally be reached 7:30-5:30 EST/EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arleen Vazquez can be reached at (571) 272-2619. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN JAMES STEAR/Examiner, Art Unit 2857
/ARLEEN M VAZQUEZ/Supervisory Patent Examiner, Art Unit 2857
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