Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The substitute specification filed 3/20/2026 has been entered because it conforms to 37 CFR 1.125(b) and (c).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (US 20200243375 A1).
Regarding claim 1, Kang discloses a semiconductor integrated circuit device (Fig. 12A) comprising:
a semiconductor substrate (110; [0016]: “silicon”);
an isolation region (116);
an active region (118) defined by the isolation region in the semiconductor substrate, the active region including at least one contact region (SC/DC: there are two SN and one DC for each 118; See annotated figure); and
a word line (120) including a main gate (See annotated figure) and a pass gate (See annotated figure), the main gate formed on the active region (120 is overlapping 118) and the pass gate positioned away from the main gate (away in the X direction) and positioned in the isolation region (120 overlapping 116),
wherein the contact region is positioned at one side of the main gate (each of SC and DC are aside 120 in the XY plane), and sidewalls of the main gate comprises a first recessed portion (See annotated figure) configured to surround the contact region (partially surround, consistent with “surround” in relation to Fig. 8 of Applicant’s disclosure) while maintain a first distance (Fig. 12B: TS1) between the sidewall of the main gate and the contact region (between in the Y direction), and
wherein a width of the pass gate (width W1as measured in the X direction, See annotated Fig. 12A) is wider (Note: “wider” is shown because W1 fully overlaps width W2 and extends beyond it each way in the X direction) than a width of the main gate (width W2 as measured in the X direction, See annotated Fig. 12A), and the width of the pass gate is substantially uniform (The width is measured along the X direction from the dashed reference lines, which are parallel to each other. Thus, the width is “substantially uniform” when measured at these parallel reference lines.).
Illustrated below are marked and annotated figures of Fig. 12A and Fig. 12B of Kang.
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Regarding claim 2, Kang discloses the semiconductor integrated circuit device of claim 1 (Fig. 12A), wherein the contact region comprises a storage node contact (SC; [0136]: “storage contacts SC may each connect a lower electrode SN of a capacitor”).
Regarding claim 4, Kang discloses the semiconductor integrated circuit device of claim 1 (Fig. 12A), wherein the contact region in the active region comprises a plurality of regions (SC/DC: there are two SN and one DC for each 118; See annotated figure), one of the contact regions is a storage node contact (SC) at a first side of the main gate (a side in the Y direction) and another of the contact regions is a bit line contact (DC) at a second side of the main gate (the opposing side in the Y direction).
Regarding claim 5, Kang discloses the semiconductor integrated circuit device of claim 4 (Fig. 12A),
wherein the first recessed portion is positioned at the first side of the main gate (a side in the Y direction),
the main gate further comprises a second recessed portion (See annotated figure) formed at the second side of the main gate across from the first recessed portion, and a second distance (Fig. 12B: TS1) is formed between the main gate and the bit line contact (between in the Y direction).
Regarding independent claim 6, Kang discloses a semiconductor integrated circuit device (Fig. 12A) comprising:
an isolation region (116);
a plurality of active regions (118) defined by the isolation region,
each of the active regions including a first junction region (SC) electrically connected with a storage node contact ([0136]: “storage contacts SC may each connect a lower electrode SN of a capacitor”) and a second junction region (DC) electrically connected with a bit line contact ([0135]: “Each of the plurality of bit lines BL may be connected to each of the plurality of active regions 118 via a direct contact DC”);
a plurality of word lines (120), each of the plurality of word lines including a first gate (120 overlapping 118; See annotated figure) and a second gate (120 overlapping 116; See annotated figure), the first gate positioned between the first junction region and the second junction region (between in the Y direction) and the second gate positioned on the isolation region (on in the Z direction),
wherein the first gate comprises a first recessed portion positioned (See annotated figure) at a first sidewall of the first gate adjacent to the storage node contact (120 is adjacent to SC in the Y direction) and a second recessed portion (See annotated figure) across from the first recessed portion (across in the Y direction) and positioned at a second sidewall of the first gate adjacent to the bit line contact (120 is adjacent to DC in the Y direction), and
wherein a width of the second gate (width W1as measured in the X direction, See annotated Fig. 12A) is wider (Note: “wider” is shown because W1 fully overlaps width W2 and extends beyond it each way in the X direction) than a width of the first gate (width W2 as measured in the X direction, See annotated Fig. 12A), and the width of the second gate is substantially uniform (The width is measured along the X direction from the dashed reference lines, which are parallel to each other. Thus, the width is “substantially uniform” when measured at these parallel reference lines.).
Regarding claim 7, Kang discloses the semiconductor integrated circuit device of claim 6 (Fig. 12A), wherein the first sidewall of the first gate is configured to surround the storage node contact (partially surround, consistent with “surround” in relation to Fig. 8 of Applicant’s disclosure) along at least one of horizontal, vertical and diagonal directions (along the Y direction which is a horizontal direction) within a first distance (Fig. 12B: TS1).
Regarding claim 9, Kang discloses the semiconductor integrated circuit device of claim 6 (Fig. 12B), wherein the second sidewall of the first gate including the second recessed portion is spaced apart from the bit line contact by a second distance (TS1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to claim 1 above, and further in view of Chang (US 20190006368 A1).
Regarding claim 3, Kang discloses the semiconductor integrated circuit device of claim 1 (Fig. 12B), wherein the first distance is a maximum distance for inducing charge coupling between the word line and the contact region (The first distance TS1 is separating two conductive features with a dielectric 122, thus this feature is electrically equivalent to a capacitor. Therefore, the distance TS1 must necessarily be a maximum charge coupling distance for at least some set of electrical conditions, i.e., voltages applied to 120 and SC/DC. See additional remarks below.).
Further regarding claim 3, Kang discloses the word line, the contact region, and the first distance. However, Kang is silent regarding the claimed characteristic of the first distance “wherein the first distance is a maximum distance for inducing charge coupling between the word line and the contact region”.
Chang teaches a charge coupling characteristic ([0046]: “there may be charge accumulation and parasitic capacitance between the secondary gate electrode 52 (passing gate) and the active area 12”) between word lines (52) and contact regions (12). This teaching reasonably applies to the main gate of Kang because in each situation there is a word line and a contact region electrically equivalent to a capacitor. Thus, Chang teaches the first distance of Kang inherently is “a maximum distance for inducing charge coupling between the word line and the contact region”. Therefore, the claimed characteristic of the first distance would have been obvious to one of ordinary skill in the art before the effective filing date because it is a characteristic inherent to the prior art. MPEP 2112 (III).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to claim 7 above, and further in view of Chang.
Regarding claim 8, Kang discloses the semiconductor integrated circuit device of claim 7 (Fig. 12B), wherein the first distance is a maximum distance for inducing charge coupling between the first gate and the storage node contact (The first distance TS1 is separating two conductive features with a dielectric 122, thus this feature is electrically equivalent to a capacitor. Therefore, the distance TS1 must necessarily be a maximum charge coupling distance for at least some set of electrical conditions, i.e., voltages applied to 120 and SC/DC. See additional remarks below.).
Further regarding claim 8, Kang discloses the first gate, the storage node contact, and the first distance. However, Kang is silent regarding the claimed characteristic of the first distance “wherein the first distance is a maximum distance for inducing charge coupling between the first gate and the storage node contact”.
Chang teaches a charge coupling characteristic ([0046]: “there may be charge accumulation and parasitic capacitance between the secondary gate electrode 52 (passing gate) and the active area 12”) between word lines (52) and storage node contact (12). This teaching reasonably applies to the first gate of Kang because in each situation there is a word line and a storage node contact electrically equivalent to a capacitor. Thus, Chang teaches the first distance of Kang inherently is “a maximum distance for inducing charge coupling between the first gate and the storage node contact”. Therefore, the claimed characteristic of the first distance would have been obvious to one of ordinary skill in the art before the effective filing date because it is a characteristic inherent to the prior art. MPEP 2112 (III).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to claim 9 above, and further in view of Chang.
Regarding claim 10, Kang discloses the semiconductor integrated circuit device of claim 9, wherein the second distance is a minimum distance for preventing charge coupling (The second distance TS1 is separating two conductive features with a dielectric 122, thus this feature is electrically equivalent to a capacitor. Therefore, the distance TS1 must necessarily be a minimum distance for preventing charge coupling for at least some set of electrical conditions, i.e., voltages applied to 120 and SC/DC. See additional remarks below.).
Further regarding claim 10, Kang discloses the first gate, the storage node contact, and the first distance. However, Kang is silent regarding the claimed characteristic of the first distance “wherein the first distance is a maximum distance for inducing charge coupling between the first gate and the storage node contact”.
Chang teaches a charge coupling characteristic ([0046]: “there may be charge accumulation and parasitic capacitance between the secondary gate electrode 52 (passing gate) and the active area 12”) between word lines (52) and a contact (12). This teaching reasonably applies to the first gate and second distance of Kang because in each situation there is a word line and a contact electrically equivalent to a capacitor. Thus, Chang teaches the second distance of Kang inherently is “a minimum distance for preventing charge coupling”. Therefore, the claimed characteristic of the second distance would have been obvious to one of ordinary skill in the art before the effective filing date because it is a characteristic inherent to the prior art. MPEP 2112 (III).
Response to Arguments
Applicant's arguments filed 3/20/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended independent claims 1 and 6 that “Kang includes a recessed portion relative to the main gate and the pass gate, and thus the main gate and the pass gate have a varying width” and “Independent claim 6 recites features similar to those discussed above for claim 1. Thus, for at least the same reasons set forth earlier with respect to claim 1, Kang fails to teach all of the features of independent claim 6 and the dependent claims of independent claim 6 and thus cannot anticipate these claims.”. Remarks at pgs. 10 and 11, respectively.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111. The examiner finds Applicant’s remarks directed to differences in the shape/dimension configuration of the gates of the disclosure and the Kang reference. However, the claim as written reasonably encompasses configurations and interpretations beyond those contended by Applicant. Accordingly, the rejection is maintained in substantially the same way as before, with citations added as necessitated by claim amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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