Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/10/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/7/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-7, 9, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (US 20200243375 A1).
Regarding claim 1, Kang discloses a semiconductor integrated circuit device (Fig. 12A) comprising:
a semiconductor substrate (110; [0016]: “silicon”);
an isolation region (116);
an active region (118) defined by the isolation region in the semiconductor substrate, the active region including at least one contact region (SC/DC: there are two SN and one DC for each 118; See annotated figure); and
a word line (120) including a main gate (See annotated figure) and a pass gate (See annotated figure), the main gate formed in ([0101]: “trench”, therefore “in”) the active region (120 is overlapping 118) and the pass gate positioned away from the main gate (away in the X direction) and positioned in the isolation region (120 overlapping 116),
wherein the contact region is positioned at one side of the main gate (each of SC and DC are aside 120 in the XY plane), and sidewalls of the main gate comprises a first recessed portion (See annotated figure) configured to surround the contact region (partially surround, consistent with “surround” in relation to Fig. 8 of Applicant’s disclosure) while maintain a first distance (Fig. 12B: TS1) between the sidewall of the main gate and the contact region (between in the Y direction),
wherein the word line extends in a first direction (X direction) and the active region has a major axis extending in a diagonal direction (See annotated figure for “diagonal” direction designation) with respect to the first direction (this “diagonal” relation is shown by the direction legend included in the figure), and
wherein a width of the pass gate (width WY-1, See annotated Fig. 12A) in a second direction (Y direction) perpendicular to the first direction (this “perpendicular” relation is shown by the direction legend included in the figure) is wider than (Note: “wider than” is shown because WY-1 fully overlaps width WY-2 and extends beyond it each way in the Y direction) a width of the main gate (width WY-2, See annotated Fig. 12A) in the second direction, and the width of the pass gate is substantially uniform (this width is measured along the Y direction between two parallel dashed reference lines, which include a portion of the pass gate that is coplanar with these lines. Therefore, at least a portion of the pass gate is “substantially uniform”. Additionally, the examiner points to MPEP 2173.05(b)(I): Terms of Degree; MPEP 2173.05(b)(III)(D): Approximations: “Substantially”; MPEP 2111: Broadest Reasonable Interpretation for guidance regarding the interpretation of the claim term “substantially uniform” and the corresponding structures found in the prior art.).
Illustrated below are marked and annotated figures of Fig. 12A and Fig. 12B of Kang.
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Regarding claim 2, Kang discloses the semiconductor integrated circuit device of claim 1 (Fig. 12A), wherein the contact region comprises a storage node contact (SC; [0136]: “storage contacts SC may each connect a lower electrode SN of a capacitor”).
Regarding claim 4, Kang discloses the semiconductor integrated circuit device of claim 1 (Fig. 12A), wherein the contact region in the active region comprises a plurality of regions (SC/DC: there are two SN and one DC for each 118; See annotated figure), one of the contact regions is a storage node contact (SC) at a first side of the main gate (a side in the Y direction) and another of the contact regions is a bit line contact (DC) at a second side of the main gate (the opposing side in the Y direction).
Regarding claim 5, Kang discloses the semiconductor integrated circuit device of claim 4 (Fig. 12A),
wherein the first recessed portion is positioned at the first side of the main gate (a side in the Y direction),
the main gate further comprises a second recessed portion (See annotated figure) formed at the second side of the main gate across from the first recessed portion, and a second distance (Fig. 12B: TS1) is formed between the main gate and the bit line contact (between in the Y direction).
Regarding claim 18, Kang discloses the semiconductor integrated circuit device of claim 1 (Fig. 12A), further comprising: a gate insulation layer (122) disposed between the active region and the word line, wherein the gate insulation layer has a uniform thickness ([0033]: “approximately equal to”. Additionally, the examiner points to MPEP 2173.05(b)(I): Terms of Degree; MPEP 2173.05(b)(III): Approximations; MPEP 2111: Broadest Reasonable Interpretation for guidance regarding the interpretation of the claim term “substantially uniform” and the corresponding structures found in the prior art.).
Regarding independent claim 6, Kang discloses a semiconductor integrated circuit device (Fig. 12A) comprising:
an isolation region (116);
a plurality of active regions (118) defined by the isolation region,
each of the active regions including a first junction region (SC) electrically connected with a storage node contact ([0136]: “storage contacts SC may each connect a lower electrode SN of a capacitor”) and a second junction region (DC) electrically connected with a bit line contact ([0135]: “Each of the plurality of bit lines BL may be connected to each of the plurality of active regions 118 via a direct contact DC”);
a plurality of word lines (120), each of the plurality of word lines including a first gate (120 overlapping 118; See annotated figure) and a second gate (120 overlapping 116; See annotated figure), the first gate positioned between the first junction region and the second junction region (between in the Y direction) and the second gate positioned on the isolation region (on in the Z direction),
wherein the first gate comprises a first recessed portion positioned (See annotated figure) at a first sidewall of the first gate adjacent to the storage node contact (120 is adjacent to SC in the Y direction) and a second recessed portion (See annotated figure) across from the first recessed portion (across in the Y direction) and positioned at a second sidewall of the first gate adjacent to the bit line contact (120 is adjacent to DC in the Y direction),
wherein the plurality of word lines extends in parallel along a first direction (X direction) and the plurality of active regions has a major axis extending in a diagonal direction (See annotated figure for “diagonal” direction designation) with respect to the first direction (this “diagonal” relation is shown by the direction legend included in the figure), and
wherein a width of the second gate (width WY-1, See annotated Fig. 12A) in a second direction (Y direction) perpendicular to the first direction (this “perpendicular” relation is shown by the direction legend included in the figure) is wider than (Note: “wider than” is shown because WY-1 fully overlaps width WY-2 and extends beyond it each way in the Y direction) a width of the first gate (width WY-2, See annotated Fig. 12A), and the width in the second direction of the second gate is substantially uniform (this width is measured along the Y direction between two parallel dashed reference lines, which include a portion of the second gate that is coplanar with these lines. Therefore, at least a portion of the second gate is “substantially uniform”. Additionally, the examiner points to MPEP 2173.05(b)(I): Terms of Degree; MPEP 2173.05(b)(III)(D): Approximations: “Substantially”; MPEP 2111: Broadest Reasonable Interpretation for guidance regarding the interpretation of the claim term “substantially uniform” and the corresponding structures found in the prior art.).
Regarding claim 7, Kang discloses the semiconductor integrated circuit device of claim 6 (Fig. 12A), wherein the first sidewall of the first gate is configured to surround the storage node contact (partially surround, consistent with “surround” in relation to Fig. 8 of Applicant’s disclosure) along at least one of the first direction, the second direction, and the diagonal direction (along the Y direction which is the 2nd direction) within a first distance (Fig. 12B: distance TS1).
Regarding claim 9, Kang discloses the semiconductor integrated circuit device of claim 6 (Fig. 12B), wherein the second sidewall of the first gate including the second recessed portion is spaced apart from the bit line contact by a second distance (TS1).
Regarding claim 19, Kang discloses the semiconductor integrated circuit device of claim 6 (Fig. 12A), further comprising: a gate insulation layer (122) disposed between the active regions and the word lines, wherein the gate insulation layer has a uniform thickness ([0033]: “approximately equal to”. Additionally, the examiner points to MPEP 2173.05(b)(I): Terms of Degree; MPEP 2173.05(b)(III): Approximations; MPEP 2111: Broadest Reasonable Interpretation for guidance regarding the interpretation of the claim term “substantially uniform” and the corresponding structures found in the prior art.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to claim 1 above, and further in view of Chang (US 20190006368 A1).
Regarding claim 3, Kang discloses the semiconductor integrated circuit device of claim 1 (Fig. 12B), wherein the first distance is a maximum distance for inducing charge coupling between the word line and the contact region (The first distance TS1 is separating two conductive features with a dielectric 122, thus this feature is electrically equivalent to a capacitor. Therefore, the distance TS1 must necessarily be a maximum charge coupling distance for at least some set of electrical conditions, i.e., voltages applied to 120 and SC/DC. See additional remarks below.).
Further regarding claim 3, Kang discloses the word line, the contact region, and the first distance. However, Kang is silent regarding the claimed characteristic of the first distance “wherein the first distance is a maximum distance for inducing charge coupling between the word line and the contact region”.
Chang teaches a charge coupling characteristic ([0046]: “there may be charge accumulation and parasitic capacitance between the secondary gate electrode 52 (passing gate) and the active area 12”) between word lines (52) and contact regions (12). This teaching reasonably applies to the main gate of Kang because in each situation there is a word line and a contact region electrically equivalent to a capacitor. Thus, Chang teaches the first distance of Kang inherently is “a maximum distance for inducing charge coupling between the word line and the contact region”. Therefore, the claimed characteristic of the first distance would have been obvious to one of ordinary skill in the art before the effective filing date because it is a characteristic inherent to the prior art. MPEP 2112 (III).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to claim 7 above, and further in view of Chang.
Regarding claim 8, Kang discloses the semiconductor integrated circuit device of claim 7 (Fig. 12B), wherein the first distance is a maximum distance for inducing charge coupling between the first gate and the storage node contact (The first distance TS1 is separating two conductive features with a dielectric 122, thus this feature is electrically equivalent to a capacitor. Therefore, the distance TS1 must necessarily be a maximum charge coupling distance for at least some set of electrical conditions, i.e., voltages applied to 120 and SC/DC. See additional remarks below.).
Further regarding claim 8, Kang discloses the first gate, the storage node contact, and the first distance. However, Kang is silent regarding the claimed characteristic of the first distance “wherein the first distance is a maximum distance for inducing charge coupling between the first gate and the storage node contact”.
Chang teaches a charge coupling characteristic ([0046]: “there may be charge accumulation and parasitic capacitance between the secondary gate electrode 52 (passing gate) and the active area 12”) between word lines (52) and storage node contact (12). This teaching reasonably applies to the first gate of Kang because in each situation there is a word line and a storage node contact electrically equivalent to a capacitor. Thus, Chang teaches the first distance of Kang inherently is “a maximum distance for inducing charge coupling between the first gate and the storage node contact”. Therefore, the claimed characteristic of the first distance would have been obvious to one of ordinary skill in the art before the effective filing date because it is a characteristic inherent to the prior art. MPEP 2112 (III).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to claim 9 above, and further in view of Chang.
Regarding claim 10, Kang discloses the semiconductor integrated circuit device of claim 9, wherein the second distance is a minimum distance for preventing charge coupling (The second distance TS1 is separating two conductive features with a dielectric 122, thus this feature is electrically equivalent to a capacitor. Therefore, the distance TS1 must necessarily be a minimum distance for preventing charge coupling for at least some set of electrical conditions, i.e., voltages applied to 120 and SC/DC. See additional remarks below.).
Further regarding claim 10, Kang discloses the first gate, the storage node contact, and the first distance. However, Kang is silent regarding the claimed characteristic of the first distance “wherein the first distance is a maximum distance for inducing charge coupling between the first gate and the storage node contact”.
Chang teaches a charge coupling characteristic ([0046]: “there may be charge accumulation and parasitic capacitance between the secondary gate electrode 52 (passing gate) and the active area 12”) between word lines (52) and a contact (12). This teaching reasonably applies to the first gate and second distance of Kang because in each situation there is a word line and a contact electrically equivalent to a capacitor. Thus, Chang teaches the second distance of Kang inherently is “a minimum distance for preventing charge coupling”. Therefore, the claimed characteristic of the second distance would have been obvious to one of ordinary skill in the art before the effective filing date because it is a characteristic inherent to the prior art. MPEP 2112 (III).
Response to Arguments
Applicant's arguments filed 7/10/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “The Applicant respectfully submits that, as amended, independent claims 1 and 6 are allowable over the prior art”. Remarks at pg. 8.
Examiner’s reply:
The examiner does not find Applicant’s remarks persuasive. The examiner points to MPEP 2111: Broadest Reasonable Interpretation and finds the claim as written reasonably encompassing width configurations beyond Applicant’s disclosure, including the configurations cited in the prior art. Accordingly, the examiner maintains the rejection in substantially the same way as before, with adjustments to the cited features, as well as additional remarks and citations as necessitated by claim amendment, and to promote clarity of the record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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