DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Species A, identified as encompassing claims 1-8 is acknowledged.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-3 are rejected under 35 U.S.C. 103 as obvious over Salcedo et al. (US 2020/0286889 A1), hereinafter as S1, in view of Takahashi (US 2002/0001229 A1), hereinafter as T1
5. Regarding Claim 1, S1 discloses a semiconductor integrated circuit device (see in particular Fig. 6A) comprising:
a first protecting unit (element 258, see [0134] “reverse protection circuit 258”) including first to nth backward diodes (elements 269a, see [0137] “dual diode segment 269a” n is equal to 2) connected in series and disposed between a pad (element 203, see [0134] “signal pad 203”) and a first power line (element AVSS, see [0134] “power low rail (AVSS)”), wherein n is a natural number (two is a natural number); and
a second protecting unit (element 257, see [0134] “forward protection circuit 257”) including at least one forward diode (at least one of the elements 259a, see [0136] “dual diode segment 259a”) connected between the pad and a second power line (element AVDD, see [0134] “power high rail (AVDD)”),
wherein
the first to nth backward diodes include a first backward diode (first upper element 269a closer to the element 203) connected to the pad,
the at least one forward diode includes a first forward diode (first lower element 259a closer to the element 203) connected to the pad.
S1 does not disclose the first backward diode and the first forward diode are integrated in one conductive well and face each other with a shared common region.
T1 discloses (see Figs. 5-6) the first backward diode (element 14b, see [0079] “backward diode 14b”) and the first forward diode (element 16a, see [0079] “forward diode 16a”) are integrated in one conductive well (elements 32N,40N, see [0081] “deep n-well 40N … n-well 32N”) and face each other with a shared common region (see Figs. 5-6 and [0079, 0081] the shared common region is element 40N).
The implementation of the forward and backward diodes as taught by T1 is incorporated as the implementation of the forward and backward diodes of S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of T1 with S1 because the combination provides charge buildup damage reduction (see T1 [0078-0081]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known physical implementation of a forward diode and backward diode for another to obtain predictable results (see T1 [0021] “the damage reducer, which is a type of electrostatic discharge (ESD) shielding” and Figs. 5-6; and see S1 [0170] “Although various examples of FinFET devices are shown, the teachings herein are applicable to other implementations of protection devices. Accordingly, other implementations are possible”).
6. Regarding Claim 2, S1, T1 disclose the semiconductor integrated circuit device of claim 1, wherein the at least one forward diode of the second protecting unit comprises first to mth forward diodes (see S1 two forward diodes) connected in series and m is a natural number equal to or less than n (m and n are both equal to two).
7. Regarding Claim 3, S1, T1 disclose the semiconductor integrated circuit device of claim 1, wherein (see in particular T1 Figs. 5-6; and see S1 Figs. 7A-B and [0129] The conductivity type can be reversed between an n-type or a p-type device for the cathode and anode conductivity types; the implementation of the diodes as taught by T1 was incorporated for S1) each of the first to nth backward diodes includes a cathode (see T1 element 40N, DNW portion below element 32P, PW and element 42A, p+) and an anode (see T1 element 42A, p+ and 32P, PW portion below), the cathode includes an N-well (element 40N, DNW portion of the backward diode).
Allowable Subject Matter
8. Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
9. Claim 4, “the anode of the forward diode includes a P-well and the cathode of the forward diode includes an N-type impurity region having a high dopant concentration in the P-well” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on claim 4 incorporate the same allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure; pertinent prior art(s) and most relevant portion(s) is provided:
US 10,249,611 B1 (Fig. 4); US 6,084,272 (Fig. 4)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMUEL PARK/Examiner, Art Unit 2818
Prosecution Insights