DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. Applicant’s amendment to the claims, filed on August 27, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
3. Applicant’s arguments/remarks, see pgs. 6-11, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant’s arguments/remarks, pgs. 6-11, regarding the newly amended limitations to at least the independent claim:
The Examiner notes a new combination of prior art are presented in light of the amendments such that arguments directed solely to the previously presented prior art rejection(s) are now moot.
Note by the Examiner
4. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 1 is rejected under 35 U.S.C. 103 as obvious over Yun (US 2008/0123230 A1), hereinafter as Y1, in view of Ker et al. (US 2003/0139024 A1), hereinafter as K1
6. Regarding Claim 1, Y1 discloses a semiconductor integrated circuit device (see in particular Figs. 2-3 and [0050] “semiconductor device”) comprising: a first protecting unit (element 170, see [0046-0047] “The ESD circuit includes a transfer element 120 and a discharge element 140”, “The transfer element 120 includes a first diode string 170 and a second diode string 180”) comprising a first backward diode (element D11, see [0049] “at least including the diode D11, the anode of which is directly connected to the input/output pad 110”) including a first cathode (upper side) and a first anode (lower side) connected to a pad (pad element 110, see [0049]), and a second backward diode (element D1n, see [0047] “diodes D11 to D1n connected in series between an input/output pad 110 and an external voltage line (or VDD) 150”) including a second cathode (upper side) connected to a first power line (element 150, see [0047]) and a second anode (lower side) connected to the first cathode (see Fig. 2 and [0047]); and
a second protecting unit (element 180, see [0046-0047] “The ESD circuit includes a transfer element 120 and a discharge element 140”, “The transfer element 120 includes a first diode string 170 and a second diode string 180”) comprising a forward diode (element D2n, see [0047] “diodes D21 to D2n connected in series between the input/output pad 110 and a ground voltage line (or VSS) 160”) including a cathode (upper side) connected to the pad (see Fig. 2) and an anode connected to a second power line (element 160, VSS, see [0047]).
Y1 does not explicitly disclose wherein the first backward diode of the first protecting unit and the forward diode of the second protecting unit are integrated in a P-well and face each other with a shared common region.
K1 discloses (see Fig. 7G) wherein the first backward diode of the first protecting unit and the forward diode of the second protecting unit are integrated in a P-well and face each other with a shared common region (see Fig. 12 backward diode elements D1, D2 and forward diode elements D3, D4 and see Fig. 7G p-well element 202a with a shared common region of the p-well, see [0052-0053] “a diode with adjacent lateral P-N junction”)
The physical implementation of the diodes as taught by K1 is incorporated as a physical implementation of the diodes of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with Y1 because the combination allows for selection of any suitable reverse breakdown voltage of the ESD protection circuit by controlling the spacing (see K1 [0053]);
And the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known specific diode implementation in a similar device for another to obtain predictable results (see K1 Fig. 12, 7G).
7. Regarding Claim 16, Y1, K1 disclose the semiconductor integrated circuit device of claim 1, wherein the first and second backward diodes of the first protecting unit and the forward diode of the second protecting unit are electrically connected in series (see Y1 Fig. 2).
8. Regarding Claim 17, Y1, K1 disclose the semiconductor integrated circuit device of claim 1, wherein an internal voltage is provided to a connection node between the first backward diode and the second backward diode (see Y1 Fig. 2 element B connected to element 140;
Note, the manner in which the current claim is recited defines a function of applying voltage during use of the claimed device rather than providing structural limitations. See MPEP 2173.05(g), the limitations recite a feature “by what it does rather than by what it is” and “A functional limitation is often used in association with an element, ingredient, or step of a process to define a particular capability or purpose that is served by the recited element, ingredient or step. In Innova/Pure Water Inc. v. Safari Water Filtration Sys. Inc., 381 F.3d 1111, 1117-20, 72 USPQ2d 1001, 1006-08 (Fed. Cir. 2004)”. If the limitation is directed to a function, property or characteristic of the apparatus, then ''the examiner provides a basis in fact and/or technical reasoning to reasonably support the determination that the allegedly inherent characteristic necessarily flow from the teachings of the applied prior art'' (quoting Ex Parte Levy, 17 USPQ2s 1461, 1464 (Bd. Pat. App. & Inter. 1990 under Section 2112.IV of the MPEP), then the burden of proof is shifted to the Applicant to show that the apparatus taught by the prior art reference cannot function or does not have the property or characteristic as recited. The prior art relied upon teach all of the claimed structure features of the claimed semiconductor device, inherently can have the property or characteristic as claimed in said limitation above).
9. Regarding Claim 18, Y1, K1 disclose the semiconductor integrated circuit device of claim 17,
wherein the internal voltage is a value obtained by dividing a difference between a voltage of the first power line and a voltage of the pad by the number of the backward diodes of the first protecting unit (The current claim is further directed to functional language as described in claim 17 without any additional structural language – the prior art discloses structure which is capable of performing the claimed function).
Allowable Subject Matter
10. Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
11. Claim 3, “further comprising a first N-well in which the second backward diode is integrated, and a second N-well in which the first cathode is disposed, and wherein the P-well is disposed within a portion of the first N-well, and the second N-well is disposed within the P-well” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on claim 3 incorporate the same allowable subject matter.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMUEL PARK/Primary Examiner, Art Unit 2818
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