DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I which corresponds to claims 1-14 in the reply filed on 12/12/2025 is acknowledged. Claims 15-20 are withdrawn from further consideration, pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Inventions or Species.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/17/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “ forming an alternating stack of insulating layers and sacrificial material layers over a substrate;” and later recites forming “ initial vertical stacks of at least one initial insulating plate and at least one initial dielectric material plate”. The claim does not provide clear antecedent basis or clarification as to how the recited “dielectric material plate” relate to, or are derived from the previously recited “sacrificial material layer”. As written, the claim uses inconsistent terminology for the layers being patterned/stacked, rendering the scope of the claimed “dielectric material plate” unclear.
Claim 6 depends from claim 5 and recites that “ the final vertical stacks are laterally spaced from the backside trenches”. However, “backside trenches” lack proper antecedent basis in claim 5 and are not introduced in the dependency chain of claim 6. Therefore, the scope of claim 6 is indefinite.
Claim 11 depends from claim 9 and recites “…backside trenches..” which lack proper antecedent basis in claim 9 and are not introduced in the dependency chain of claim 11. Therefore, the scope of claim 11 is indefinite.
Claim 13 recites “… the spacer material plates ..” which lack proper antecedent basis and is not otherwise defined in the claim. As written it is unclear what structure is encompassed by “spacer material plates”. Therefore, the scope of claim 13 is indefinite.
Claim 14 recites “… the stepped surfaces ..” which lack proper antecedent basis in claim 2 and are not introduced in the dependency chain of claim 14. As written, the scope of “stepped surfaces” is indefinite.
Claims 2-5, 7-10, and 11-12 depends from claim 1 or it’s dependent claims so they are rejected for the same reason.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-15 and 20 of US-20240251560A1 (hereinafter US’560).
Application number 18/353,546 and Claim #
Application number US20240251560A1 (hereinafter US’560) and Claim #
1. A method of forming a semiconductor structure, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming a first patterned photoresist layer over the alternating stack, wherein the first patterned photoresist layer comprises a set of discrete photoresist material portions that are laterally spaced apart along a first horizontal direction;
forming initial vertical stacks of at least one initial insulating plate and at least one initial dielectric material plate by transferring a pattern in the first patterned photoresist layer through at least one insulating layer within the insulating layers and at least one sacrificial material layer within the sacrificial material layers;
performing a plurality of pattern transfer process sequences, wherein each of the plurality of pattern transfer process sequences comprises a respective patterned photoresist layer formation step that forms a respective patterned photoresist layer, a respective anisotropic etch process step that transfers a pattern in the respective patterned photoresist layer through at least one underlying insulating layer of the insulating layers and at least one sacrificial material layer of the sacrificial material layers, and a respective photoresist removal step that removes the respective patterned photoresist layer, wherein final vertical stacks of at least one final insulating plate and at least one final dielectric material plate are formed; and
replacing remaining portions of the sacrificial material layers that underlie the final vertical stacks with electrically conductive layers.
11. A method of forming a semiconductor structure, comprising:
forming an alternating stack of insulating layers and sacrificial material layers extending along a first horizontal direction through a first memory array region and a staircase region;
forming a first patterned photoresist layer over the alternating stack, wherein the first patterned photoresist layer comprises a set of discrete photoresist material portions that are laterally spaced apart along a first horizontal direction;
forming initial vertical stacks of at least one initial insulating plate and at least one initial dielectric material plate in the staircase region by transferring a pattern in the first patterned photoresist layer through at least one insulating layer within the insulating layers and at least one sacrificial material layer within the sacrificial material layers;
performing a plurality of pattern transfer process sequences, wherein each of the plurality of pattern transfer process sequences comprises a respective patterned photoresist layer formation step that forms a respective patterned photoresist layer, a respective anisotropic etch process step that transfers a pattern in the respective patterned photoresist layer through at least one underlying insulating layer of the insulating layers and at least one sacrificial material layer of the sacrificial material layers in the staircase region, and a respective photoresist removal step that removes the respective patterned photoresist layer, wherein final vertical stacks of at least one final insulating plate and at least one final dielectric material plate are formed in the staircase region; and
replacing remaining portions of the sacrificial material layers that underlie the final vertical stacks in the staircase region and that are located in the memory array region with electrically conductive layers.
Rejection Basis: Claim 11 of US’560 contains every limitation of claim 1 plus geographic context (staircase region, memory array region). (Claim 11 of US’560 is narrower than claim 1)
2. The method of claim 1, further comprising:
forming memory openings through a region of the alternating stack that is free of the final vertical stacks; and
forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a respective vertical semiconductor channel.
12. The method of claim 11, further comprising:
forming memory openings through the alternating stack in the first memory array region that is free of the final vertical stacks; and
forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a respective vertical semiconductor channel.
Rejection Basis: The only difference is that US’560 Claim 12 names the region as “first memory array region.” This is not patentable distinct . (Claim 12 of US’560 is narrower than claim 2)
3. The method of claim 1, further comprising:
forming backside trenches through the alternating stack; and
performing an isotropic etch process that etches a material of the sacrificial material layers selective to a material of the insulating layers by introducing an isotropic etchant into the backside trenches to form backside recesses.
4. The method of claim 3, further comprising depositing an electrically conductive material in the backside recesses through the backside trenches.
13. The method of claim 11, further comprising:
forming backside trenches through the alternating stack in the first memory array region and in the staircase region;
performing an isotropic etch process that etches a material of the sacrificial material layers selective to a material of the insulating layers by introducing an isotropic etchant into the backside trenches to form backside recesses;
depositing an electrically conductive material in the backside recesses through the backside trenches.
Rejection Basis: US’560 Claim 13 is a combination of Parent Claims 3 and claim 4 with added location specifically (memory array region + staircase region). (Claim 13 of US’560 is narrower than the combination of claim 3 and claim 4.)
5. The method of claim 1, further comprising:
forming a dielectric material portion having a stepped bottom surface directly on the final vertical stacks of at least one final insulating plate and at least one final dielectric material plate; and
forming layer contact via cavities through the dielectric material portion by performing an anisotropic etch process that includes a first etch step that etches a material of the dielectric material portion selective to at least one material within the final vertical stacks which is used as an etch stop.
14. The method of claim 11, further comprising:
forming a dielectric material portion having a stepped bottom surface directly on the final vertical stacks of at least one final insulating plate and at least one final dielectric material plate; and
forming layer contact via cavities through the dielectric material portion by performing an anisotropic etch process that includes a first etch step that etches a material of the dielectric material portion selective to at least one material within the final vertical stacks which is used as an etch stop.
6. The method of claim 5, wherein:
the final vertical stacks are laterally spaced from the backside trenches; and
the final dielectric material plates comprise a same material as a material of the sacrificial material layers after replacement of the remaining portions of the sacrificial material layers that underlie the final vertical stacks with the electrically conductive layers.
15. The method of claim 14, wherein:
the final vertical stacks are laterally spaced from the backside trenches; and
the final dielectric material plates comprise a same material as a material of the sacrificial material layers after replacement of the remaining portions of the sacrificial material layers that underlie the final vertical stacks with the electrically conductive layers.
7. The method of claim 6,
wherein the first etch step etches the material of the dielectric material portion selective to a material of the final dielectric material plates which is used as an etch stop.
14. The method of claim 11, further comprising:
…that includes a first etch step that etches a material of the dielectric material portion selective to at least one material within the final vertical stacks which is used as an etch stop.
Claim 7 is narrower than US’560 Claim 14.
8. The method of claim 7, wherein the anisotropic etch process further comprises at least one second etch step that etches a material of the final dielectric material plates selective to a material of the final insulating plates, and at least one third etch step that etches the material of the final insulating plates selective to the material of the final dielectric material plates or selective to a material of the electrically conductive layers.
9. The method of claim 5, further comprising replacing the final dielectric material plates with electrically conductive material plates concurrently with replacement of the sacrificial material layers with the electrically conductive layers,
wherein the first etch step etches the material of the dielectric material portion selective to a material of the electrically conductive material plates which is used as an etch stop.
17. The method of claim 14, further comprising replacing the final dielectric material plates with electrically conductive material plates concurrently with replacement of the sacrificial material layers with the electrically conductive layers.
Claim 9 is narrower than US’560 Claim 17.
10. The method of claim 9, wherein the anisotropic etch process further comprises at least one second etch step that etches the material of the electrically conductive material plates selective to a material of the final insulating plates, and at least one third etch step that etches the material of the final insulating plates selective to the material of the electrically conductive material plates and selective to a material of the electrically conductive layers.
11. The method of claim 9, further comprising depositing a dielectric backside trench fill material at least at a peripheral portion of each of the backside trenches, wherein all sidewall surfaces of the electrically conductive material plates are in contact with the dielectric backside trench fill material.
12. The method of claim 1, wherein each of the final vertical stacks comprises a vertically alternating sequence of a respective plurality of final insulating plates and a respective plurality of final dielectric material plates.
13. The method of claim 1, wherein:
a first portion of an alternating stack of the insulating layers and the electrically conductive layers comprises a first tier;
a second portion of the alternating stack of the insulating layers and the electrically conductive layers comprises a second tier located over the first tier; and
each of the vertical stacks in the first tier comprises a different number of the insulating plates and the spacer material plates than each of the vertical stacks in the second tier.
14. The method of claim 2, further comprising forming a first memory array region and a second memory array region that are laterally spaced apart by a staircase region containing the stepped surfaces, wherein the memory opening fill structures are located within the first memory array region and the second memory array region,
wherein the electrically conductive layers have a respective bridge region having a respective strip width within the staircase region, and the electrically conductive layers have a respective uniform width greater than the strip width in the first memory array region, the second memory array region, and portions of the staircase region located outside the bridge region.
20. The method of claim 11, further comprising forming a second memory array region that is laterally spaced apart from the first memory array region by the staircase region, wherein the memory opening fill structures are located within the first memory array region and the second memory array region,
wherein the electrically conductive layers have a respective bridge region having a respective strip width within the staircase region, and the electrically conductive layers have a respective uniform width greater than the strip width in the first memory array region, the second memory array region, and portions of the staircase region located outside the bridge region.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ohsawa et. al. - US-20230309298-A1
Iwai et. al. - US-20210134827-A1
Tokita et. al. - US-20210366920-A1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817