Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant’s election without traverse of Group I, Embodiment 1 (figs. 1A-17) which corresponds to claims 1-11 and 13 in the reply filed on 11/24/2025 is acknowledged. Therefore, claims 12 and 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-2, 5, 7-11 and 13 are rejected under 35 U.S.C. 102(a2) as being anticipated by Lee et al. (US 12,347,777; hereinafter Lee).
Regarding claim 1, Lee, in figs. 11A & 12, discloses a memory device 200, comprising: at least one alternating stack of insulating layers 225 and electrically conductive layers 227g; memory openings (memory opening fill structures 47 located in the memory openings) vertically extending through each layer within the at least one alternating stack (fig. 11A); memory opening fill structures 47 located in the memory openings (col. 22, lines 45-50 & fig. 3A) and comprising a respective vertical semiconductor channel 51 and a respective vertical stack of memory elements 49; and an electrically conductive side-contact via structure 289 vertically extending through each layer within the at least one alternating stack and contacting a sidewall of one of the electrically conductive layers 227g (fig. 12).
Regarding claim 2, Lee discloses wherein an entirety of an interface between the side-contact via structure 289 and the one of the electrically conductive layers 227g is located within a cylindrical vertical plane (fig. 12).
Regarding claim 5, Lee discloses wherein each of the insulating layers 225 within the at least one alternating stack comprises a respective cylindrical sidewall 225 that contacts the side-contact via structure 289 (fig. 12).
Regarding claim 7, Lee discloses wherein: each of the electrically conductive layers 227g comprises a respective combination of a metallic barrier liner and a metallic fill material portion (col. 22, lines 42-44 and col. 6, lines 54-59); and the side-contact via structure 289 is in contact with a metallic barrier liner of the one of the electrically conductive layers, and is laterally spaced from a metallic fill material portion of the one of the electrically conductive layers.
Regarding claim 8, Lee discloses further comprising a vertical stack of annular dielectric spacers 225 laterally surrounding the side-contact via structure 289, wherein the side-contact via structure 289 is in contact with an inner cylindrical sidewall of each annular dielectric spacer 225 within the vertical stack of annular dielectric spacers 225 (fig. 12).
Regarding claim 9, Lee discloses further comprising additional side-contact via structures 289 vertically extending through each layer within the at least one alternating stack and contacting a sidewall of a respective electrically conductive layer of the electrically conductive layers 227g (fig. 12).
Regarding claim 10, Lee discloses further comprising at least one semiconductor source layer 217 located below the alternating stack (col. 22, lines 50-53 and fig. 3A), wherein: each of the vertical semiconductor channels 51 comprises an end portion that is electrically connected to the at least one semiconductor source layer (17 in fig. 3A); and the first sidewall-contact via structure 289 is electrically isolated from the at least one semiconductor source layer by a semiconductor oxide plate 219a (fig. 11A).
Regarding claim 11, Lee discloses wherein the at least one semiconductor source layer comprises a layer stack including a lower source-level material layer 17a, a source contact layer 17b’contacting each of the vertical semiconductor channels 51, and an upper source-level material layer 17c (fig. 3A).
Regarding claim 13, Lee discloses further comprising: a substrate 204 vertically spaced from the at least one alternating stack 223’; a peripheral circuitry 208 located on the substrate 204; lower-level metal interconnect structures 211 embedded within lower-level dielectric layers 213 and located over the peripheral circuitry 208; source-level material layers 217 located over the lower-level dielectric layers 213 and underlying the at least one alternating stack 223’; and upper-level metal interconnect structures 287 embedded within upper-level dielectric layers 232 and located over the at least one alternating stack 223’, wherein the upper-level metal interconnect structures 287 are electrically connected to the peripheral circuitry 208 through the lower-level metal interconnect structures 211 (fig. 11A).
3. Claims 1-6 and 9 are rejected under 35 U.S.C. 102(a2) as being anticipated by Choi (US 12,550,323).
Regarding claim 1, Choi, in figs. 3A-3B, discloses memory device, comprising: at least one alternating stack of insulating layers IL and electrically conductive layers CP (fig. 3A); memory openings vertically extending through each layer within the at least one alternating stack; memory opening fill structures 155A located in the memory openings and comprising a respective vertical semiconductor channel 153A and a respective vertical stack of memory elements 151A; and an electrically conductive side-contact via structure 181A vertically extending through each layer within the at least one alternating stack and contacting a sidewall of one of the electrically conductive layers CP (fig. 3B).
Regarding claim 2, Choi discloses wherein an entirety of an interface between the side-contact via structure 181A and the one of the electrically conductive layers CP is located within a cylindrical vertical plane (fig. 3B).
Regarding claim 3, Choi discloses further comprising a vertical stack of annular dielectric spacers (IL portion between CP and 181A) laterally surrounding the side-contact via structure 181A, wherein each electrically conductive layer CP within the at least one alternating stack except the one of the electrically conductive layers CP is laterally spaced from the side-contact via structure 181A by a respective one of the annular dielectric spacers (IL portion between CP and 181A) (fig. 3B).
Regarding claim 4, Choi discloses wherein: each of the annular dielectric spacers (IL portion between CP and 181A) comprises a respective outer cylindrical sidewall that is laterally offset outward from a respective inner cylindrical sidewall by a respective lateral offset distance that is independent of an azimuthal angle from a vertical axis passing through a geometrical center of the side-contact via structure 181A; and all lateral offset distances of the annular dielectric spacers are the same (fig. 3B).
Regarding claim 5, Choi discloses wherein each of the insulating layers IL within the at least one alternating stack comprises a respective cylindrical sidewall that contacts the side-contact via structure 181A (fig. 3B).
Regarding claim 6, Choi discloses further comprising backside blocking dielectric layers 161 located between each vertically neighboring pair of an insulating layer IL and an electrically conductive layer CP within the at least one alternating stack, wherein the side-contact via structure 181A is in contact with two cylindrical surface segments of the backside blocking dielectric layers 161 (fig. 3B).
Regarding claim 9, Choi discloses further comprising additional side-contact via structures 181A vertically extending through each layer within the at least one alternating stack and contacting a sidewall of a respective electrically conductive layer of the electrically conductive layers CP (fig. 3B).
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818