CTFR 18/353,671 CTFR 86322 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Arguments 07-37 AIA Applicant's arguments filed April 7, 2026 have been fully considered but they are not persuasive. The second auxiliary chip is in electrical contact with the primary chip through electrical pathways that travel through the first auxiliary chip. Amendments to claim 16 overcome the cited references . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1,2,4-9 is/are rejected under 35 U.S.C. 102 (A)(1) as being anticipated by Fleischman et al. (US 20110291261 A1; Fleischman) . Regarding claim 1, Fleischman discloses a multiple integrated circuit (IC) stack, comprising: a primary IC (Fig. 6A/6B, 102; ¶95-97) a first auxiliary IC (Fig. 6A/6B, 114; ¶95-97) coupled to the primary IC through a first electrical conductor (Fig. 6A/6B, 118; ¶95-97) a second auxiliary IC (Fig. 6A/6B,510; ¶95-97) coupled to the primary IC through a second electrical conductor (Fig. 6A/6B, 606; ¶95-97) contacting (electrically) the second auxiliary IC and the primary IC, wherein the second electrical conductor is different from the first electrical conductor and a primary array of terminals (Fig. 6A/6BA/7,104; ¶98) extending a distance from the primary IC farther than distances that the first auxiliary IC and the second auxiliary IC are disposed from the primary IC wherein the first auxiliary IC and the second auxiliary IC overlap the primary IC, and wherein the first auxiliary IC is closer to the primary IC than the second auxiliary IC. Applicants’ auxiliary IC are stacked as 114/510 are also stacked. Regarding claim 2, Fleischman discloses the multiple IC stack of claim 1, wherein the terminals of the primary array of terminals (Fig. 6A/6BA/7,104; ¶98) are in a grid pattern, and the first auxiliary IC is rotated (to be parallel) with respect to the grid pattern of the primary array of terminals. Rotated with respect to the grid pattern is broad language. Is the IC rotated to where lateral surfaces of the auxiliary IC parallel to rows and columns of the claimed grid or at an angle (other than 180 or 90 degrees) to grid rows and columns? Regarding claim 4, Fleischman discloses the multiple IC stack of claim 1, wherein the second auxiliary IC (Fig. 6A/6B,510; ¶95-97) is positioned within a void region of the primary IC (Fig. 6A/6B, 102; ¶95-97) lacking terminals within the primary array of terminals. (Fig. 6A/6BA/7,104; ¶98) Regarding claim 5, Fleischman discloses multiple IC stack of claim 1, wherein the primary IC (Fig. 6A/6B, 102; ¶95-97) has a surface, and wherein the first electrical conductor (Fig. 6A/6B, 118; ¶95-97) , the second electrical conductor (Fig. 6A/6B, 606; ¶95-97) , and at least one of the terminals of the primary array of terminals (Fig. 6A/6BA/7,104; ¶98) extend from the surface. (stack below the primary IC). Regarding claim 6, Fleischman discloses the multiple IC stack of claim 1, wherein the second auxiliary IC (Fig. 6A,510; ¶95-97) is coupled to the first auxiliary IC (Fig. 6A, 114; ¶95-97) through one or more through-substrate vias. (Fig. 6A, 608; ¶95-97) At least one surface of the second auxiliary IC is connected to higher layers by through substrate vias 608. Regarding claim 7, Fleischman discloses multiple IC stack of claim 1 wherein the second auxiliary IC (Fig. 6A,510; ¶95-97) is coupled to the first auxiliary IC (Fig. 6A, 114; ¶95-97)through at least one terminal of an intervening array of terminals. (Fig. 6A, 606; ¶95 97) Regarding claim 8, Fleischman discloses multiple IC stack of claim 1 wherein the second auxiliary IC (Fig. 6A,510; ¶95-97) is coupled to the primary IC (Fig. 6A/6B, 102; ¶95-97) through an intervening array of terminals. (Fig. 6A, 606; ¶95-97) Regarding claim 9, Fleischman discloses the multiple IC stack of claim 1 wherein the second auxiliary IC (Fig. 6A,510; ¶95-97) is spaced apart from the first auxiliary IC. (Fig. 6A, 114; ¶95-97) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fleischman et al. (US 20110291261 A1; Fleischman) in view of Liu et al. (US-20110062597-A1; Liu) . Regarding claim 3, Fleischman discloses the multiple IC stack of claim 1, wherein the terminals of the primary array of terminals (Fig. 6A/6BA/7,104; ¶98) are in a grid pattern, but is silent on and the first auxiliary IC is rotated between about 30 0 and about 60 0 with respect to the grid pattern of the primary array of terminals. Liu discloses rotating a chip stack where a second chip (Fig. 4A, 210; ¶40) is rotated between about 30 and about 60 degrees. The invention of Liu is a FBGA. In such configurations the BGA is aligned with the edges of the substrate. When the chip is rotated relative to the chip or substrate edges it is also relative to the ball grid array. Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to rotate mounted chip between about 30 and about 60 degrees for the benefit of reducing stress in the package . 07-21-aia AIA Claim (s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fleischman et al. (US 20110291261 A1; Fleischman) in view of Park et al. (US 20210257324 A1; Park) . Regarding claim 10, Fleischman discloses the multiple IC stack of claim 1, but is silent on wherein the first auxiliary IC comprises a redistribution layer, and the multiple IC stack further comprises an additional array of terminals connected to respective portions of the redistribution layer. Park discloses an auxiliary IC (Fig. 3B, 150; ¶22) that includes a redistribution layer (Fig. 3B, 154; ¶24), and further including an array of terminals (Fig. 3B, 159; ¶29) connected to respective portions of the redistribution layer. Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to add a redistribution layer to the auxiliary IC for making multiple connections between auxiliary components, such as capacitors, and components of the primary IC . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 16-25 are allowed. The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14). The relevant art, US-20100123215-A1, discloses a multiple integrated circuit (IC) stack, including:(a) a primary IC with a primary array of terminals, a first auxiliary IC including at least one capacitor, a void region of the primary IC lacking terminals within the primary array of terminals. US-11342316-B2 discloses a primary chip and a second chip comprising a capacitor. US-20150123268-A1 discloses a primary chip, first auxiliary chip, and second auxiliary chip. Regarding claim 16, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: "and the overlapping portions of the first auxiliary IC and the second auxiliary IC are spaced apart by a gap devoid of mechanical or electrical coupling;”, as recited in Claim 16, with the remaining features. 13-03 Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAWRENCE C TYNES JR./ Examiner, Art Unit 2899 Application/Control Number: 18/353,671 Page 2 Art Unit: 2899 Application/Control Number: 18/353,671 Page 3 Art Unit: 2899 Application/Control Number: 18/353,671 Page 4 Art Unit: 2899 Application/Control Number: 18/353,671 Page 5 Art Unit: 2899 Application/Control Number: 18/353,671 Page 6 Art Unit: 2899
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