Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US-20190131273-A1; Chen) in view of Shen et al. (US-20170018510-A1; Shen).
Regarding claim 1, Chen discloses a semiconductor package comprising: a … interposer (Fig. 3, E1; ¶22); a redistribution layer (RDL) (Fig. 3, RDL2; ¶32) disposed on a first surface (TOP) of the… interposer; a plurality of computation nodes (Fig. 3, 300/400; ¶37) disposed on the RDL, each of the computation nodes comprising a computation die (logic/processor/SOC), wherein the RDL is between the computation nodes and the … interposer, and each of computation dies of the computation nodes comprises a plurality of micro bumps (Fig. 3, 110; ¶28), and the computation dies are bonded to the RDL through the micro bumps; a plurality of through … vias (Fig. 3, TIV ¶167) … passing through the … interposer; and a plurality of bumps (Fig. 3, 112; ¶33) disposed on a second surface of the …interposer and coupled to the RDL through the TSVs; wherein: each two adjacent computation nodes of the computation nodes are coupled to each other through the RDL (Fig. 3, RDL2 108; ¶22); and from the top view, the RDL comprises interconnect structures distributed in portions that overlap the computation nodes and portions free from overlapping the computation nodes.
The cross-sectional view shows the interconnect structures outside the boundaries of the chips. Therefore, from plan view perspective they will also be non-overlapping. Chen is silent on using a silicon interposer.
Applicant discloses the computation node is a SOC that include one or more computation cores (¶18) and a memory (¶20).
Chen discloses chips 300 and 400 are SOCs that include logic and memory.
Shen discloses a similar package using a silicon interposer (Fig. 4A, 420; ¶26) with TSVs. (Fig. 4A, 450; ¶29)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use silicon for the interposer material for thermal expansion properties.
Regarding claim 10, Chen in view of Shen discloses a semiconductor device comprising: a printed circuit board (PCB) (Fig. 6E, 120; ¶3,47 Shen) ; and a semiconductor package (Fig. 2, 2; ¶36 Chen) of claim 1 bonded to the PCB through the plurality of bumps. (Fig. 2, 112; ¶33 Chen)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to couple the package to a PCB in order to complete a high capacity computing configuration.
Regarding claim 11, Chen in view of Shen discloses a method for manufacturing a semiconductor package comprising: receiving a… interposer (Fig.7D, E1; ¶22,52); forming a plurality of through … vias (TSVs) (Fig. 7D, TIV ¶52) within the …interposer; forming a redistribution layer (RDL) (Fig. 7D, RDL2; ¶32,51) on a first surface (top) of the … interposer; receiving a plurality of computation nodes (Fig. 7D, 300/400; ¶37,51) wherein each of the computation nodes comprises a computation die (logic/processor/SOC), and each of computation dies of the computation nodes comprises a plurality of micro bumps (Fig. 7D, 300e/400e; ¶28); disposing the computation nodes on the RDL, comprising bonding the computation dies of the computation nodes to the RDL through the micro bumps, wherein the RDL is between the computation nodes and the … interposer; … and forming a plurality of bumps (Fig. 7D,105; ¶46) on a second surface of the … interposer and coupled to the plurality of TSVs, wherein the bumps are coupled to the RDL through the TSVs; wherein: each two adjacent computation nodes of the computation nodes are coupled to each other through the RDL (Fig. 7D, 108; ¶22); and from a top view, the RDL comprises interconnect structures distributed in portions that overlap the computation nodes and portions free from overlapping the computation nodes. (¶48)
Paragraph 48 discloses that RDL2 has the same dimensions as RDL1 as in figure 3. (Fig. 3, RDL2; ¶32) When RDL2 has the dimensions of as shown in figure 2 peripheral circuits are formed on RDL2 instead of RDL1 of Fig. 7FE.
Figure 3 shows interconnect structures outside the area of the nodes. Therefore Chen discloses this feature.
Applicant discloses the computation node is a SOC that include one or more computation cores (¶18) and a memory (¶20).
Chen discloses chips 300 and 400 are SOCs that include logic and memory.
Chen is silent on using a silicon interposer and TSVs; grinding a backside of the…interposer to expose the plurality of TSVs;
Shen discloses a similar package using a silicon interposer (Fig. 4A, 420; ¶26) with TSVs. (Fig. 4A, 450; ¶29) and grinding the backside of the interposer to expose the TSVs.(Fig. 6B, 420/450;¶42)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use silicon for the interposer material for thermal expansion properties; to expose the backside of the vias through grinding as an alternative to using a backside carrier because it is a known technique available to one of ordinary skill in the art, and the results would have been predictable to one of ordinary skill in the art. The Supreme Court in KSR noted that if the actual application of the technique would have been beyond the skill of one of ordinary skill in the art, then using the technique would not have been obvious. See MPEP 2143 (C) /(D)
Claim(s) 2-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US-20190131273-A1; Chen) in view of Shen et al. (US-20170018510-A1; Shen), and further in view of Liao et al. (US-20230352381-A1; Liao).
Regarding claim 2, Chen in view of Shen discloses the semiconductor package of claim 1, but is silent on wherein from the top view, the RDL comprises a plurality of first rectangular regions and a plurality of second rectangular regions, wherein the first rectangular regions have same sizes and same patterns of interconnect structures, the second rectangular regions have same sizes and same patterns of interconnect structures, and each of the first rectangular regions is adjacent to at least one of the second rectangular regions.
Chen discloses a multi-chip package, but only shows a cross sectional view. In three dimensions or in plan view the plurality of chips and chip attach areas would be visible.
Liao discloses a package where from a top view a RDL (Fig. 2B; 922; ¶46) comprises a plurality of first rectangular regions (Fig.2B, left side of UA; ¶50) and a plurality of second rectangular regions (Fig. 2B, right side of UA; ¶50), wherein the first rectangular regions have same sizes and same patterns of interconnect structures (Fig. 2B, 940; ¶50), the second rectangular regions have same sizes and same patterns of interconnect structures, and each of the first rectangular regions is adjacent to at least one of the second rectangular regions.
Liao’s interconnects are an equivalent to Chens interconnects (Fig. 1E, 110;¶22).
Before the effective filing date it would have been obvious to one having ordinary skill in the art to have the rectangular areas when providing multiple die attach areas in a multi-chip package to have a more powerful computing package.
Regarding claim 3, Chen in view of Shen and Liao discloses the semiconductor package of claim 2, wherein the interconnect structures (Fig. 1E, 110;¶22 Chen ) of the RDL comprise a plurality of conductive traces (Fig. 1E, 108 between 300 and 400;¶22 Chen ) that overlap boundaries of the first rectangular regions (Fig.2B, left side of UA; ¶50 Liao) and the second rectangular regions (Fig. 2B, right side of UA; ¶50 Liao) from the top view, and the conductive traces are all perpendicularly crossing the boundaries.(extends under chip 300/400)
Before the effective filing date it would have been obvious to one having ordinary skill in the art to have the rectangular areas when providing multiple die attach areas in a multi-chip package to have a more powerful computing package.
Regarding claim 4, Chen in view of Shen and Liao discloses the semiconductor package of claim 3, wherein the interconnect structures (Fig. 1E, 110;¶22 Chen ) of the RDL further comprise a plurality of vias (Fig. 1E, 110 connected to horizontal 108;¶22 Chen ), and from the top view, the vias are free from overlapping boundaries of the first rectangular regions (Fig. 2B, left side of UA; ¶50 Liao) and the second rectangular regions. (Fig. 2B, right side of UA; ¶50 Liao)
It is clear from the cross sectional view that vias connecting 110 to 108 do not extend horizontally and would not cross adjacent chip attach areas (claimed rectangular regions)
Before the effective filing date it would have been obvious to one having ordinary skill in the art to have multiple rectangular areas when providing multiple die attach areas in a multi-chip package to have a more powerful computing package.
Regarding claim 5, Chen in view of Shen and Liao discloses the semiconductor package of claim 2, wherein from the top view (not shown), each of the computation nodes overlaps (Fig. 1G, 300/400; ¶27 Chen) at least one of the first rectangular regions (Fig. 2B, left side of UA; ¶50 Liao) and at least one of the second rectangular regions. (Fig. 2B, right side of UA; ¶50 Liao)
The rectangular regions are chip attach areas. Therefore, associated chips would overlap rectangular regions.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to have multiple rectangular areas when providing multiple die attach areas in a multi-chip package to have a more powerful computing package.
Regarding claim 6, Chen in view of Shen and Liao discloses the semiconductor package of claim 2, wherein: from the top view, the RDL further comprises a plurality of third rectangular regions and a plurality of fourth rectangular regions; the third rectangular regions have same sizes and same patterns of interconnect structures, and the fourth rectangular regions have same sizes and same patterns of interconnect structures; each of the first rectangular regions is adjacent to at least one of the second rectangular regions and at least one of the third rectangular regions; and each of the second regions is adjacent to at least one of the first rectangular regions and at least one of the fourth rectangular regions.
The cited reference does not disclose the claimed third and fourth rectangular. One of ordinary skill in the art would add more rectangular areas to increase the computing power of the package. Unless a new and unexpected result is produced from adding third and fourth rectangular regions the mere duplication of parts holds no patentable significance.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to add the claimed third and fourth rectangular regions for increasing the overall operation capacity of the semiconductor package, since it has been held that a mere duplication of the essential working parts of a device involves only routine skill in the art. MPEP 2144.04 VI
Regarding claim 7, Chen in view of Shen and Liao discloses the discloses the semiconductor package of claim 6, wherein from the top of view, each of the computation nodes (Fig. 1G, 300/400; ¶27 Chen) overlaps a first rectangular region of the first rectangular regions (Fig. 2B, left side of UA; ¶50 Liao), a second rectangular region of the second rectangular regions (Fig. 2B, right side of UA; ¶50 Liao), but is silent on a third rectangular region of the third rectangular regions, and a fourth rectangular region of the fourth rectangular regions.
Liao discloses multiple sets of computation nodes (700/800) are bonded to the redistribution layer 920. ( ¶51) Therefore, there will be multiple rectangular regions.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to have the rectangular areas when providing multiple die attach areas in a multi-chip package to have a more powerful computing package. Also, It would have been obvious to one having ordinary skill in the art before the effective filing date to add the claimed third and fourth rectangular regions for increasing the overall operation capacity of the semiconductor package, since it has been held that a mere duplication of the essential working parts of a device involves only routine skill in the art. MPEP 2144.04 VI
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US-20190131273-A1; Chen) in view of Shen et al. (US-20170018510-A1; Shen), Liao et al. (US-20230352381-A1; Liao), and further in view of Yu et al. (US-20140203429-A1; Yu).
Regarding claim 8, Chen in view of Shen discloses the semiconductor package of claim 1, wherein each of the computation nodes further comprises a plurality of high bandwidth memory (HBM) dies, each disposed on the RDL in close proximity to the computation die and coupled to the computation die through the RDL.
Chen discloses the computation nodes but is silent on how the specific node configuration. Chen discloses at least one HBM with a computation die.
Liao discloses a computer node on a redistribution layer where a plurality of high bandwidth memory (HBM) dies (Fig. 3B, 800; ¶51 Liao), each disposed on the RDL s (Fig. 3AB, 920; ¶51 Liao) in close proximity to the computation die s (Fig. 3B, 700; ¶51 Liao) and coupled to the computation die through the RDL.
Liao does not specifically disclose the HBM are connected to a computation die. However in the art the node would not work if the HBM is not coupled to the computation die. In the case of Liao, coupled through the RDL 920.
Yu discloses a package where a computer chip (Fig. 7, 24; ¶18) is coupled to HBM (Fig. 7, 124; ¶18) through the RDL (Fig. 7, 42; ¶18)
Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to couple the HBM to the computation die through the RDL for optimal die to die communication and package functionality.
Regarding claim 18, Chen in view of Shen discloses the method of claim 11, wherein each of the computation nodes (Fig. 7G, 300/400; ¶52 Chen) further comprises a plurality of high bandwidth memory (HBM) dies, and the step of disposing the computation nodes on the RDL further comprises bonding the HBM dies of each of the computation nodes to the RDL in close proximity to the computation die of each of the computation nodes.
Chen discloses the computation nodes but is silent on how the specific node configuration. Chen discloses at least one HBM with a computation die.
Liao discloses a computer node on a redistribution layer where a plurality of high bandwidth memory (HBM) dies (Fig. 3B, 800; ¶51 Liao), each disposed on the RDL s (Fig. 3AB, 920; ¶51 Liao) in close proximity to the computation die s (Fig. 3B, 700; ¶51 Liao) and coupled to the computation die through the RDL.
Liao does not specifically disclose the HBM are connected to a computation die. However in the art the node would not work if the HBM is not coupled to the computation die. In the case of Liao, coupled through the RDL 920.
Yu discloses a package where a computer chip (Fig. 7, 24; ¶18) is coupled to HBM (Fig. 7, 124; ¶18) through the RDL (Fig. 7, 42; ¶18)
Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to couple the HBM to the computation die through the RDL for optimal die to die communication and package functionality.
Allowable Subject Matter
Claim 9, 12-17, 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 20 is objected to solely due to its dependence on claim 19. Claims 13-17 are objected to solely due dependence on claim 12
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Lin et al. (US-20210090983-A1; Lin) discloses input/output dies surrounding computation nodes but is silent on being coupled through an RDL.
Regarding claim 9, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " herein each of the computation nodes is coupled to at least one corresponding input/output die of the input/output dies through the RDL.”, as recited in Claim 9, with the remaining features.
Regarding claim 12, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " forming a plurality of first rectangular regions of the RDL by utilizing a first series of masks; and forming a plurality of second rectangular regions of the RDL by utilizing a second series of masks;”, as recited in Claim 12, with the remaining features.
Regarding claim 19, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " and each of the computation nodes is coupled to at least one corresponding input/output die of the input/output dies through the RDL.”, as recited in Claim 19, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899