DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over YOUN (US 20080248632) in view of MOULI (US 20080272363).
Regarding claim 1, YOUN discloses a memory device, comprising:
a first interconnection extending in a first direction (the left word line WL 55 in fig 3 shown in fig 9, see para 37);
a first layer including tungsten nitride, the first layer being provided on the first interconnection (71 can be a WN layer and is directly on 55, see fig 9, para 41), the first layer being connected to the first interconnection (71 is directly connected to 55, see fig 9),
a stacked body layer provided on the first layer (the stack of layers comprising at least 73, 81, 83, 85 and 87, see fig 9, para 47 and 60), the stacked body layer comprising
a first material layer including a first material, the first material being different from a material of the first layer (81 which can be MoAlN or TiSiN, see fig 9, para 63), and
a second material layer including a second material which is different from the first material and the material of the first layer (85, which can be TiAlN, see fig 9, para 63');
a second layer provided on the stacked body layer, the second layer including tungsten (75, which can be a WN layer, see fig 9, para 63);
a first memory cell including a germanium tellurium antimony alloy and having a lower surface and an upper surface (the phase change memory layer 77 which can comprise GeSbTe alloy, see fig 9, para 47), wherein the lower surface is provided on the second layer (the lower surface of 77 is on 75, see fig 9);
a second interconnection provided above the first memory cell and extending in a second direction intersecting the first direction (the bit line BL 97 above 95 which is shown in fig 9 and is the lower BL in fig 3, see para 51);
a third layer including tungsten disposed between the first memory cell and the second interconnection (the layer 95 which can be WN, see fig 9, para 50),
a third interconnection adjacent the second interconnection in the first direction and extending in the second direction (the upper connection BL shown in fig 3, not show in cross-section, which extends in the same direction as the lower BL shown in fig 3, see fig 3, para 51); and
a second memory cell provided above the first interconnection and including a germanium tellurium antimony alloy (the phase change memory layer 77 in the data storage element Rp formed at the intersection of the upper BL and the left WL in fig 3, not shown in cross-section, see fig 9, para 36 and 47), the second memory cell being provided between the first interconnection and the third interconnection,
wherein the second layer completely covers the lower surface of the first memory cell (75 completely covers the lower surface of 77, see fig 9), and
the third layer completely covers the upper surface of the memory cell (95 completely covers a top surface of 77, see fig 9).
YOUN fails to explicitly disclose a device comprising a circuit.
wherein the first interconnection being provided between the circuit and the first layer;
MOULI teaches a device comprising a circuit (the substrate 12 can include a circuit, see fig 6, para 32);
wherein the first interconnection being provided between the circuit and the first layer (the first interconnection 22 is between the conductive layer 32 and the circuit 12, see fig 6, para 33).
YOUN and MOULI are analogous art because they both are directed towards 3-D memory array devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of YOUN with the substrate circuit of MOULI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of YOUN with the substrate circuit of MOULI in order to reduce the real estate consumption attributed to individual memory cells (see MOULI para 26).
Regarding claim 2, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, wherein
a length of the first interconnection in the first direction is longer than a length of the first memory cell in the first direction (BL extends further in the left-right direction in fig 3 than does Rp, of which 77 is a part, see fig 3, para 54), and
a length of the second interconnection in the second direction is longer than a length of the first memory cell in the second direction (WL extends in the up-down direction further than does Rp, of which 77 is a part, see fig 3, para 54).
Regarding claim 3, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, wherein the first layer is provided directly on the stacked body layer (71 is directly on 73, which an be part of the stacked body layer, see fig 9).
Regarding claim 4, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, wherein the first memory cell is a resistance change layer (77 has a changing resistance, see para 53-55).
Regarding claim 6, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, wherein the first material includes a metal element (81 can be MoAlN which includes metal element Al, see fig 9, para 63).
Regarding claim 7, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, wherein the first material includes nitrogen (81 can be MoAlN which includes N, see fig 9, para 63).
Regarding claim 8, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, wherein
the first material includes one or more selected from the group consisting of silicon, titanium, tantalum, zirconium, aluminum (81 can be MoAlN which includes Al, see fig 9, para 63)., hafnium, molybdenum, tungsten, and vanadium, and
the second material includes a nitride or an oxide of one or more selected from the group consisting of silicon, titanium, tantalum, zirconium, aluminum (85 can be TiAlN which is an aluminum nitride, see fig 9, para 63), hafnium, molybdenum, tungsten, and vanadium.
Regarding claim 9, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, wherein the first material includes silicon (81 can be TiSiN, which includes Si, see fig 9, para 63).
Regarding claim 10, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, wherein
the first material includes aluminum (81 can be MoAlN which includes Al, see fig 9, para 63), and
the second material includes an aluminum nitride (85 can be TiAlN which is an aluminum nitride, see fig 9, para 63).
Regarding claim 11, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, wherein the first interconnection is provided between a substrate and the first layer (the first interconnection 55 is provided between the substrate 51 and the first layer 71, see fig 9, para 37).
Regarding claim 12, YOUN and MOULI disclose the device according to claim 1.
YOUN further discloses a device, further comprising:
a fourth layer including tungsten nitride, the fourth layer being provided on the first interconnection (the WN electrode 71 in the resistance device Rp formed in the upper-left device in fig 3, see fig 3 and 9, para 41); and
a fifth layer including tungsten disposed between the second memory cell and the third interconnection (the WN electrode 95 in the resistance device Rp formed in the upper-left device in fig 3, see fig 3 and 9, para 50).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over YOUN (US 20080248632) in view of MOULI (US 20080272363) and further in view of RINERSON (US 20040159828).
Regarding claim 5, YOUN and MOULI disclose the device according to claim 1.
YOUN and MOULI fail to explicitly disclose a device, wherein the stacked body layer has a resistivity higher than a resistivity of the first interconnection.
RINERSON teaches a device, wherein the stacked body layer has a resistivity higher than a resistivity of the first interconnection (stacked body layer 1045 includes Al2O3 which has a higher resistivity than Al/Cu of the first interconnect 1070, see fig 10, para 92 and 97).
YOUN, MOULI and RINERSON are analogous art because they both are directed towards 3-D arrays of memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of YOUN and MOULI with the resistivities of RINERSON because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of YOUN and MOULI with the resistivities of RINERSON in order to improve the memory and switching properties (see RINERSON para 31).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811