DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIYOTOSHI (US 20090294751) in view of MOULI (US 20080272363).
Regarding claim 1, KIYOTOSHI discloses a memory device, comprising:
a first interconnection (bit line 101, see fig 9B and 13, para 122) extending in a first direction (101 extends longitudinally in the x-direction, see fig 9B and 13);
a first layer including tungsten nitride (102 can be WN, see fig 9A and 13, para 119 and 142), the first layer being provided on the first interconnection (102 is directly on 101, see fig 9B and 13), the first layer being connected to the first interconnection,
a stacked body layer provided on the first layer (the stack of layers 103-113, see fig 13, para 119-125), the stacked body layer comprising
a first material layer including a first material (TiN layer 107, see fig 13, para 121), the first material being different from a material of the first layer, and
a second material layer including a second material (Si layer 105, see fig 13, para 121) which is different from the first material and the material of the first layer;
a second layer provided on the stacked body layer, the second layer including tungsten (114 can be a WN layer, see fig 13, para 125 and 142);
a first memory cell including a germanium tellurium antimony alloy (resistance change layer 115 can be GeSbTe, see fig 13, para 125 and 141) and having a lower surface (the lower surface of 115, see fig 13) and an upper surface (the upper surface of 115, see fig 13), wherein the lower surface is provided on the second layer (the lower surface of 115 is directly on 114, see fig 13);
a second interconnection (fig 13, 128, para 131) provided above the first memory cell (128 is above 115, see fig 13) and extending in a second direction intersecting the first direction (128 extends longitudinally in the y direction, see fig 12 and 13);
a third layer including tungsten (116 can be WN, see fig 13, para 125 and 141) disposed between the first memory cell and the second interconnection (116 is between 115 and 128, see fig 13);
a third interconnection (fig 13, 137, para 135) provided above the second interconnection in a third direction crossing the first direction and the second direction (137 is above 128 in the z direction, see fig 13), and extending in the first direction (137 extends longitudinally in the x-direction); and
a second memory cell including a germanium tellurium antimony alloy (resistance change layer 133 can be GeSbTe, see fig 13, para 133 and 141), the second memory cell being provided between the second interconnection and the third interconnection (133 is between 128 and 137, see fig 13),
wherein
the second layer completely covers the lower surface of the first memory cell (114 completely covers the bottom layer of 115, see fig 13 and 10), and.
the third layer completely covers the upper surface of the first memory cell (116 covers a top surface of 115, see fig 13 and 10).
KIYOTOSHI fails to explicitly disclose a device comprising a circuit;
the first interconnection being provided between the circuit and the first layer.
MOULI teaches a device comprising a circuit (the substrate 12 can include a circuit, see fig 6, para 32);
the first interconnection being provided between the circuit and the first layer (the first interconnection 22 is between the conductive layer 32 and the circuit 12, see fig 6, para 33).
KIYOTOSHI and MOULI are analogous art because they both are directed towards storage devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIYOTOSHI with the substrate circuit of MOULI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIYOTOSHI with the substrate circuit of MOULI in order to reduce the real estate consumption attributed to individual memory cells (see MOULI para 26).
Regarding claim 2, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI further discloses a device, wherein
a length of the first interconnection in the first direction is longer than a length of the first memory cell in the first direction (the length of 101 in the x-direction is longer than that of 115, see fig 13), and
a length of the second interconnection in the second direction is longer than a length of the first memory cell in the second direction (the length of 128 in the y-direction is longer than that of 115, see fig 13).
Regarding claim 3, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI further discloses a device, wherein the first layer is provided directly on the stacked body layer (102 is directly on 103 which is part of the stacked body layer, see fig 13).
Regarding claim 4, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI further discloses a device, wherein the first memory cell is a resistance change layer (115 is a resistance change layer, see para 125 and 141).
Regarding claim 5, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI further discloses a device, wherein the stacked body layer has a resistivity higher than a resistivity of the first interconnection (the stacked body layer includes TiN layer 107 which will have a higher resistivity than the W layer 101, see fig 13).
Regarding claim 6, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI further discloses a device, wherein the first material includes a metal element (107 can be TiN, see para 121).
Regarding claim 7, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI further discloses a device, wherein the first material includes nitrogen (107 can be TiN, see para 121).
Regarding claim 11, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI further discloses a device, wherein the first interconnection is provided between a substrate and the first layer (101 is on a substrate not shown, see fig 9, para 118).
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIYOTOSHI (US 20090294751) in view of MOULI (US 20080272363) and further in view of YOUN (US 20080248632).
Regarding claim 8, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI fails to explicitly disclose a device, wherein
the first material includes one or more selected from the group consisting of silicon, titanium, tantalum, zirconium, aluminum, hafnium, molybdenum, tungsten, and vanadium, and
the second material includes a nitride or an oxide of one or more selected from the group consisting of silicon, titanium, tantalum, zirconium, aluminum, hafnium, molybdenum, tungsten, and vanadium.
YOUN teaches a device, wherein
the first material includes one or more selected from the group consisting of silicon, titanium, tantalum, zirconium, aluminum (81 can be MoAlN which includes Al, see fig 9, para 63)., hafnium, molybdenum, tungsten, and vanadium, and
the second material includes a nitride or an oxide of one or more selected from the group consisting of silicon, titanium, tantalum, zirconium, aluminum (85 can be TiAlN which is an aluminum nitride, see fig 9, para 63), hafnium, molybdenum, tungsten, and vanadium.
YOUN, KIYOTOSHI and MOULI are analogous art because they both are directed towards storage devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIYOTOSHI and MOULI with the specific materials of YOUN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIYOTOSHI and MOULI with the specific materials of YOUN in order to improve the current drivability of the switching device (see YOUN para 7).
Regarding claim 9, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI fails to explicitly disclose a device, wherein the first material includes silicon.
YOUN teaches a device, wherein the first material includes silicon (81 can be TiSiN, which includes Si, see fig 9, para 63).
YOUN, KIYOTOSHI and MOULI are analogous art because they both are directed towards storage devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIYOTOSHI and MOULI with the specific materials of YOUN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIYOTOSHI and MOULI with the specific materials of YOUN in order to improve the current drivability of the switching device (see YOUN para 7).
Regarding claim 10, KIYOTOSHI and MOULI disclose the device according to claim 1.
KIYOTOSHI fails to explicitly disclose a device, wherein
the first material includes aluminum, and
the second material includes an aluminum nitride.
YOUN teaches a device, wherein
the first material includes aluminum (81 can be MoAlN which includes Al, see fig 9, para 63), and
the second material includes an aluminum nitride (85 can be TiAlN which is an aluminum nitride, see fig 9, para 63).
YOUN, KIYOTOSHI and MOULI are analogous art because they both are directed towards storage devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIYOTOSHI and MOULI with the specific materials of YOUN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIYOTOSHI and MOULI with the specific materials of YOUN in order to improve the current drivability of the switching device (see YOUN para 7).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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