Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-14, in the reply filed on December 12, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cui et al. (US 2020/0335518).
Regarding claim 1, Cui discloses a three-dimensional memory device, comprising:
an alternating stack of insulating layers (32) and composite layers (44/46) that alternate along a vertical direction [Figs. 13A-14, and 17A-18], wherein each of the composite layers comprises a combination of a dielectric connection plate (44) and a plurality of electrically conductive strips (46) that laterally extend along a first horizontal direction [Figs. 13A-14, and 17a-18], are laterally spaced apart along a second horizontal direction by backside trenches (79) that laterally extend along the first horizontal direction [Fig. 12 and 17A-18], and have a respective sidewall adjoined to a respective sidewall surface segment of the dielectric connection plate (44) [Figs. 12-13D and 17A-18], wherein end portions of the backside trenches (79) are laterally bounded by the dielectric connection plates (44) of the composite layers [Figs. 15 and 17A-18];
arrays of memory openings (49) vertically extending through the alternating stack [Figs. 4A-4B and 8A-9A], and ;
memory opening fill structures (55) located in the memory openings, wherein each of the memory opening fill structures (55) comprises a vertical semiconductor channel (60) and a respective vertical stack of memory elements (50) located at levels of the electrically conductive strips [Figs. 9A-10A, 12 and 17A-18];
backside trench fill structures (76) located in the backside trenches and vertically extending at least from a first horizontal plane including bottommost surfaces of the alternating stacks and at least to a second horizontal plane including topmost surfaces of the alternating stacks [Figs. 16A-16B and 17A-18]; and
dielectric etch stop structures (171) located within or outside a respective one of the backside trenches (79), wherein each of the dielectric etch stop structures comprises a respective pair of dielectric sidewalls that are located within a pair of lengthwise sidewalls of the respective one of the backside trenches (79), wherein the dielectric sidewalls of the dielectric etch stop structures (171) laterally extend along the first horizontal direction and vertically extend at least from the first horizontal plane and at least to the second horizontal plane [Figs. 17B and 18].
Regarding claim 2, Cui discloses wherein each of the electrically conductive strips (46) has a respective lateral extent along the second horizontal direction that is not greater than a lateral spacing between a pair of most proximal pair of the backside trenches (79) [Figs. 17B and 18].
Regarding claim 14, Cui discloses wherein the alternating stacks (32/44/46) are located in different memory blocks (100) which are electrically isolated from each other by the backside trenches (79) and the dielectric etch stop structures (171) 9Fig. 17B and 18].
Allowable Subject Matter
Claims 3-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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