DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9-10 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tokuno (JP H10-173089).
Regarding claim 1, Tokuno teaches a flip chip semiconductor package comprising:
a wiring substrate (Fig. 1, wiring substrate 1) that includes a core layer (not labeled, but see layer with wiring layer in it) and a lower protection layer (not labeled, but see bottom-most layer) on a lower surface of the core layer (Fig. 1);
a trench group (trenches not labeled in Fig. 1, but see where vias are located) that includes a plurality of trenches spaced apart from one another on the lower protection layer (Fig. 1), wherein an entire perimeter of each trench of the trench group is within the core layer (see Fig. 1);
a flip chip (2) on the wiring substrate and the trench group (Fig. 1); and
a molding layer (7) that is on the flip chip and the wiring substrate, and extends into the plurality of trenches (Fig. 1).
Regarding claim 2, Tokuno teaches the flip chip semiconductor package of claim 1, wherein the plurality of trenches extend in a first direction parallel to the wiring substrate from a first region to a second region (see Fig. 13), the first region being adjacent to a front surface of the flip chip, and the second region being adjacent to a rear surface of the flip chip (see Fig. 13, they extend from one side of the chip to the other side, i.e. front surface to rear surface).
Regarding claim 3, Tokuno teaches the flip chip semiconductor package of claim 2, wherein the plurality of trenches are spaced apart from one another (Fig. 1 and 13), in a second direction that is perpendicular to the first direction and parallel to the wiring substrate, at a center portion of the wiring substrate (see Fig. 13).
Regarding claim 4, Tokuno teaches the flip chip semiconductor package of claim 1, wherein ones of the plurality of trenches are between portions of the core layer and extend in a direction perpendicular to the wiring substrate (Fig. 1 and 13, between sections of the core where the chip is located).
Regarding claim 5, Tokuno teaches the flip chip semiconductor package of claim 1, wherein the plurality of trenches comprise vertical sidewalls (Fig. 1), and
wherein respective upper widths and respective lower widths of respective ones of the plurality of trenches are equal to each other (see Fig. 1).
Regarding claim 9, Tokuno teaches a flip chip semiconductor package comprising:
a wiring substrate (Fig. 1, substrate 1) that comprises:
a core layer (unlabeled layer with wiring layers in it);
a wiring layer on the core layer (see Fig. 1, wiring 4);
an upper protection layer on the wiring layer (unlabeled top-most layer of 1);
a lower protection layer (unlabeled bottom-most layer of 1) on a lower surface of the core layer; and a plurality of internal wiring pads spaced apart from one another (pads 4);
a trench group (trenches at vias) that includes a plurality of trenches spaced apart from one another (Fig. 1), wherein the plurality of trenches are on the lower protection layer and at least partially penetrate the wiring layer and the core layer (Fig. 1);
a flip chip (flip chip 2) on the wiring layer, the upper protection layer, and the trench group (Fig. 1), the flip chip including a plurality of internal solder balls (solder balls 3) spaced apart from one another and on the plurality of internal wiring pads (Fig. 1), wherein the trench group is positioned below the flip chip (Fig. 1); and
a molding layer (molding layer 7) on the flip chip and the wiring substrate, wherein the molding layer extends into the plurality of trenches (Fig. 1), a region between respective ones of the plurality of internal wiring pads (Fig. 1), and a region between respective ones of the plurality of internal solder balls (Fig. 1).
Regarding claim 10, Tokuno teaches the flip chip semiconductor package of claim 9, further comprising a plurality of external wiring pads (shown in Fig. 6, bottom pads 10) spaced apart from one another and insulated from one another by the lower protection layer (Fig. 6), and a plurality of external solder balls electrically connected to the plurality of external wiring pads (not shown, but inherent that solder balls would connect to the pads once it is in use because electrical connection is necessary for functionality of the device).
Regarding claim 14, Tokuno teaches the flip chip semiconductor package of claim 9, wherein the plurality of trenches are spaced apart from one another at a center portion of the wiring substrate (Fig. 1), and
wherein respective separation distances between adjacent ones of the plurality of trenches are equal to one another (Fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Koh in view of Lin et al. (U.S. Publication No. 2024/003076).
Regarding claim 6, Tokuno teaches the flip chip semiconductor package of claim 1, but does not teach wherein the plurality of trenches comprise inclined sidewalls, and
wherein respective upper widths of respective ones of the plurality of trenches are greater than respective lower widths of the respective ones of the plurality of trenches.
However, Lin teaches a similar package in which the plurality of trenches comprise inclined sidewalls (see Lin Fig. 5C), and wherein respective upper widths of respective ones of the plurality of trenches are greater than respective lower widths of the respective ones of the plurality of trenches (Lin Fig. 5C). It would have been obvious to a person of skill in the art at the time of the effective filing date that the sidewalls of the trenches could have been inclined because this reduces the risk of forming voids/gaps where the corners meet at 90°.
Regarding claim 11, Tokuno teaches the flip chip semiconductor package of claim 9, but does not teach wherein the flip chip further comprises a plurality of chip bumps on the plurality of internal solder balls, and the molding layer extends between respective ones of the plurality of chip bumps and between respective ones of the plurality of internal solder balls without leaving a void therebetween.
However, Lin teaches a similar package wherein the flip chip further comprises a plurality of chip bumps on the plurality of internal solder balls (see Lin Fig. 8A, bumps 788), and the molding layer extends between respective ones of the plurality of chip bumps and between respective ones of the plurality of internal solder balls without leaving a void therebetween (Lin Fig. 8A, molding layer 792 is between bumps without any voids). It would have been obvious to a person of skill in the art at the time of the effective filing date that the chip could have had bumps because some sort of electrical connection to the solder is necessary, and external bumps allows for more surface contact between the bumps and solder.
Response to Arguments
Applicant’s arguments with respect to all claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 15-20, the prior art, alone or in combination, fails to teach or suggest a plurality of internal wiring pads spaced apart from one another in the opening region, and wherein an entire perimeter of at least one trench of the trench group is within the core layer.
Claims 7-8 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior art, alone or in combination, fails to teach or suggest wherein respective widths of ones of the plurality of trenches are a combination of being different and equal to one another.
Regarding claim 8, the prior art, alone or in combination, fails to teach or suggest wherein the molding layer is on a top surface of the lower protection layer, but does not extend below the lower surface of the core layer.
Regarding claim 12, the prior art, alone or in combination, fails to teach or suggest wherein the plurality of internal solder balls comprise a plurality of signal internal solder balls at a center portion of the wiring substrate and a plurality of chip supporting internal solder balls at a peripheral portion of the wiring substrate.
Regarding claim 13, the prior art, alone or in combination, fails to teach or suggest wherein respective first widths of first ones of the plurality of trenches are equal to one another, wherein respective second widths of second ones of the plurality of trenches are equal to one another, and wherein the first widths are different from the second widths.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899