DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1- Fig 3, encompassing Claims 1, 2, 5-16, 17 and 18 in the reply filed on 10/29/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-16, 17 and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by DU et al. 20220399423.
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Regarding claim 1, figs. 1-4F of Du discloses a display device comprising:
a substrate 101;
a first wiring layer 202 on the substrate, the first wiring layer comprising a first wire 221 and a second wire Ca each extending along the substrate, along a first direction (D2 in fig. 4E and into the page – fig. 4F), the first wire and the second wire spaced apart from each other along a second direction (D1 in fig. 4E and across the page in fig. 4F) crossing the first direction;
a planarization layer 107 on the first wiring layer;
a first pixel electrode 134a which is on the planarization layer;
a pixel-defining layer 430 on the planarization layer and overlapping the first pixel electrode; and
a first pixel opening 401/4012 which is defined in the pixel-defining layer and exposes the first pixel electrode to outside the pixel-defining layer, wherein the pixel-defining layer comprises:
first edges which define the first pixel opening, and among the first edges of the pixel-defining layer:
a 1-1 edge and a 1-2 edge each extends along the first direction,
the 1-1 edge and the 1-2 edge are spaced apart from each other along the second direction, and the 1-1 edge overlaps the first wire 221.
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Regarding claim 17, figs. 1-4F of Du discloses a display device comprising:
a substrate 101;
a pixel electrode 134a of a light-emitting element 120, on the substrate;
a pixel-defining layer 430 which overlaps the pixel electrode;
a pixel opening 401/4012 which is defined by a plurality of edges (4 edges – fig. 4E) of the pixel-defining layer, the pixel opening exposing the pixel electrode 134a to outside the pixel-defining layer;
a wiring layer 202 between the substrate and the pixel electrode, the wiring layer comprising a plurality of wires (221/Ca) each extending along the substrate in a first direction D2 (fig. 4B), the plurality of wires being spaced apart from each other along a second direction crossing the first direction (D1); and
a planarization layer 107 which is between the wiring layer and the pixel electrode, and between the wiring layer and the pixel-defining layer;
wherein among the plurality of edges of the pixel-defining layer which define the pixel opening:
a first edge (as labeled by examiner above) extends along the first direction, and a second edge (as labeled by examiner above) extends along the second direction and is connected to the first edge at a corner of the pixel opening (as labeled by examiner above), and
the plurality of wires (221/Ca) of the wiring layer overlap the second edge of the pixel-defining layer to define an overlapping area of the second edge, together with a non-overlapping area of the second edge which is between the plurality of first wires along the second direction.
Regarding claim 2, figs. 4E and 4F of Du discloses wherein the 1-2 edge overlaps the second wire.
Regarding claim 5, figs. 4B/4F of Du discloses wherein the first wiring layer further comprises:
a third wire 240 and a fourth wire 240/VT (on the top of fig. 4E) each extending along the substrate along the first direction, and the first wire, the second wire, the third wire and the fourth wire in order along the second direction and spaced apart from each other along the second direction.
Regarding claim 6, fig. 4E of Du discloses further comprising a second pixel electrode 134b which is on the planarization layer and is spaced apart from the first pixel electrode 134a along the second direction D1,
wherein the pixel-defining layer overlaps the second pixel electrode,
a second pixel opening 401/4013 is defined in the pixel-defining layer which exposes the second pixel electrode to outside the pixel-defining layer, and the pixel-defining layer further comprises:
second edges which define the second pixel opening, and among the second edges of the pixel-defining layer,
a 2-1 edge extends along the first direction and overlaps the third wire 240/VT.
Regarding claim 7, fig. 4E of Du discloses wherein among the second edges of the pixel-defining layer, a 2-2 edge extends along the first direction, is spaced apart from the 2-1 edge and overlaps the fourth wire.
Regarding claim 8, fig. 4E of Du discloses further comprising a second pixel electrode 134b which is on the planarization layer and is spaced apart from the first pixel electrode 134a,
wherein the pixel-defining layer overlaps the second pixel electrode, a second pixel opening is defined in the pixel-defining layer which exposes the second pixel electrode to outside the pixel-defining layer, and the pixel-defining layer further comprises:
second edges which define the second pixel opening, and among the second edges of the pixel-defining layer:
a 2-1 edge and a 2-2 edge each extend along the first direction, the 2-1 edge and the 2-2 edge are spaced apart from each other along the second direction with the third wire 240 therebetween, and
the 2-1 edge and the 2-2 edge are spaced apart from the third wire along the second direction.
Regarding claim 9, fig. 4E of Du discloses wherein the fourth wire is between the 2-1 edge and the 2-2 edge along the second direction, and the fourth wire (240 on top of fig. 4B) is spaced apart from each of the 2-1 edge, the 2-2 edge and the third wire along the second direction.
Regarding claim 10 (see rejection of claim 6 with the word second equivalent to the word third), Du discloses further comprising a third pixel electrode which is on the planarization layer and is spaced apart from the first pixel electrode along the first direction, wherein the pixel-defining layer overlaps the third pixel electrode, a third pixel opening is defined in the pixel-defining layer which exposes the third pixel electrode to outside the pixel-defining layer, and the pixel-defining layer further comprises: third edges which define the third pixel opening, and among the third edges of the pixel-defining layer a 3-1 edge extends along the first direction and overlaps the first wire.
Regarding claim 11 (see rejection of claim 6 with the word second equivalent to the word third), Du discloses wherein among the third edges of the pixel-defining layer, a 3-2 edge extends along the first direction, is spaced apart from the 3-1 edge and overlaps the second wire.
Regarding claim 12, figs. 4A/F of Du discloses further comprising: a second wiring layer 201 on the substrate, the second wiring layer comprising a fifth wire 210 and a sixth wire 230 each extending along the substrate along the second direction D1, the fifth wire and the second wire spaced apart from each other along the first direction D2; an organic insulating layer 106 and an interlayer insulating layer 103, on the substrate; and
in order from the substrate, along a thickness direction of the display device, the interlayer insulating layer 103, the second wiring layer, the organic insulating layer 106, the first wiring layer 203 and the planarization layer 107.
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Regarding claim 13, wherein among the first edges of the pixel-defining layer which define the first pixel opening: a 1-3 edge and a 1-4 edge each extend along the second direction, the 1-3 edge and the 1-4 edge are spaced apart from each other along the first direction, and the 1-3 edge overlaps the fifth wire 210.
Regarding claim 14, fig. 4E of Du discloses wherein the 1-4 edge overlaps the sixth wire (see edges overlap).
Regarding claim 15, Du discloses wherein the fifth wire is between the 1-3 edge and the 1-4 edge along the first direction, and the fifth wire is spaced apart (vertical spaced) from each of the 1-3 edge and the 1-4 edge along the first direction (vertical is along the first direction).
Regarding claim 16, fig. 4E of Du discloses wherein the sixth wire 230 is between the 1-3 edge and the 1-4 edge along the first direction (see fig. 4F with 230 below which is between), and the sixth wire is spaced apart (vertical spaced) from each of the 1-3 edge, the 1-4 edge, and the fifth wire along the first direction (vertical is along the first direction).
Regarding claim 18, fig. 4E of Du discloses wherein the overlapping area is further defined at the corner of the pixel opening and along the first edge.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893